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GET /api/patches/91423/?format=api
{ "id": 91423, "url": "https://patches.dpdk.org/api/patches/91423/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618385649-44717-3-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618385649-44717-3-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618385649-44717-3-git-send-email-wenzhuo.lu@intel.com", "date": "2021-04-14T07:34:07", "name": "[v5,2/4] net/iavf: add offload path for Tx AVX512", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "22ed9e29c5396e686b20d168dae070f3e5c348f7", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618385649-44717-3-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 16361, "url": "https://patches.dpdk.org/api/series/16361/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16361", "date": "2021-04-14T07:34:05", "name": "add Rx/Tx offload paths for IAVF AVX512", "version": 5, "mbox": "https://patches.dpdk.org/series/16361/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91423/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91423/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9EBFA0524;\n\tWed, 14 Apr 2021 09:34:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AB91E16179B;\n\tWed, 14 Apr 2021 09:34:28 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 04B2A160FE5\n for <dev@dpdk.org>; Wed, 14 Apr 2021 09:34:24 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Apr 2021 00:34:23 -0700", "from dpdk-wenzhuo-haswell.sh.intel.com ([10.67.111.137])\n by FMSMGA003.fm.intel.com with ESMTP; 14 Apr 2021 00:34:21 -0700" ], "IronPort-SDR": [ "\n /ShMj4PR1jf5bt4FAt54HMG1HHBkMghVnGl+8m8EHA3Qt5Pl2JjXokHytohnMF32jSMUkYCxMu\n F3ebMS0qz6ig==", "\n HiQA33wgUNIKDsry3WhUjql+lBg0dQLHkRvPzazTahF37JKwvcqU8MeC+QaLMJhoY/QsidD0xn\n QDAQ7VFqSRoQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"174084748\"", "E=Sophos;i=\"5.82,221,1613462400\"; d=\"scan'208\";a=\"174084748\"", "E=Sophos;i=\"5.82,221,1613462400\"; d=\"scan'208\";a=\"450705154\"" ], "X-ExtLoop1": "1", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "Date": "Wed, 14 Apr 2021 15:34:07 +0800", "Message-Id": "<1618385649-44717-3-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1618385649-44717-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1617947944-130983-1-git-send-email-wenzhuo.lu@intel.com>\n <1618385649-44717-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 2/4] net/iavf: add offload path for Tx AVX512", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add a specific path for TX AVX512.\nIn this path, support the HW offload features, like,\nchecksum insertion, VLAN insertion.\nThis path is chosen automatically according to the\nconfiguration.\n\n'inline' is used, then the duplicate code is generated\nby the compiler.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/iavf/iavf_rxtx.c | 57 +++++++++++------\n drivers/net/iavf/iavf_rxtx.h | 14 +++-\n drivers/net/iavf/iavf_rxtx_vec_avx512.c | 110 +++++++++++++++++++-------------\n drivers/net/iavf/iavf_rxtx_vec_common.h | 98 ++++++++++++++++++++++++++--\n 4 files changed, 210 insertions(+), 69 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\nindex bd0b7ee..099ede7 100644\n--- a/drivers/net/iavf/iavf_rxtx.c\n+++ b/drivers/net/iavf/iavf_rxtx.c\n@@ -160,7 +160,7 @@\n static inline bool\n check_tx_vec_allow(struct iavf_tx_queue *txq)\n {\n-\tif (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&\n+\tif (!(txq->offloads & IAVF_TX_NO_VECTOR_FLAGS) &&\n \t txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&\n \t txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {\n \t\tPMD_INIT_LOG(DEBUG, \"Vector tx can be enabled on this txq.\");\n@@ -2498,17 +2498,23 @@\n #ifdef RTE_ARCH_X86\n \tstruct iavf_tx_queue *txq;\n \tint i;\n+\tint check_ret;\n+\tbool use_sse = false;\n \tbool use_avx2 = false;\n-#ifdef CC_AVX512_SUPPORT\n \tbool use_avx512 = false;\n-#endif\n \n-\tif (!iavf_tx_vec_dev_check(dev) &&\n-\t\t\trte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n-\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n-\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n-\t\t\t\trte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)\n-\t\t\tuse_avx2 = true;\n+\tcheck_ret = iavf_tx_vec_dev_check(dev);\n+\n+\tif (check_ret >= 0 &&\n+\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {\n+\t\t/* SSE and AVX2 not support offload path yet. */\n+\t\tif (check_ret == IAVF_VECTOR_PATH) {\n+\t\t\tuse_sse = true;\n+\t\t\tif ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&\n+\t\t\t rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)\n+\t\t\t\tuse_avx2 = true;\n+\t\t}\n #ifdef CC_AVX512_SUPPORT\n \t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&\n \t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 &&\n@@ -2516,15 +2522,29 @@\n \t\t\tuse_avx512 = true;\n #endif\n \n-\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n-\t\t\t use_avx2 ? \"avx2 \" : \"\",\n-\t\t\t dev->data->port_id);\n-\t\tdev->tx_pkt_burst = use_avx2 ?\n-\t\t\t\t iavf_xmit_pkts_vec_avx2 :\n-\t\t\t\t iavf_xmit_pkts_vec;\n+\t\tif (!use_sse && !use_avx2 && !use_avx512)\n+\t\t\tgoto normal;\n+\n+\t\tif (!use_avx512) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n+\t\t\t\t use_avx2 ? \"avx2 \" : \"\",\n+\t\t\t\t dev->data->port_id);\n+\t\t\tdev->tx_pkt_burst = use_avx2 ?\n+\t\t\t\t\t iavf_xmit_pkts_vec_avx2 :\n+\t\t\t\t\t iavf_xmit_pkts_vec;\n+\t\t}\n #ifdef CC_AVX512_SUPPORT\n-\t\tif (use_avx512)\n-\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;\n+\t\tif (use_avx512) {\n+\t\t\tif (check_ret == IAVF_VECTOR_PATH) {\n+\t\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512;\n+\t\t\t\tPMD_DRV_LOG(DEBUG, \"Using AVX512 Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t} else {\n+\t\t\t\tdev->tx_pkt_burst = iavf_xmit_pkts_vec_avx512_offload;\n+\t\t\t\tPMD_DRV_LOG(DEBUG, \"Using AVX512 OFFLOAD Vector Tx (port %d).\",\n+\t\t\t\t\t dev->data->port_id);\n+\t\t\t}\n+\t\t}\n #endif\n \t\tdev->tx_pkt_prepare = NULL;\n \n@@ -2544,8 +2564,9 @@\n \n \t\treturn;\n \t}\n-#endif\n \n+normal:\n+#endif\n \tPMD_DRV_LOG(DEBUG, \"Using Basic Tx callback (port=%d).\",\n \t\t dev->data->port_id);\n \tdev->tx_pkt_burst = iavf_xmit_pkts;\ndiff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h\nindex f56dd74..bead119 100644\n--- a/drivers/net/iavf/iavf_rxtx.h\n+++ b/drivers/net/iavf/iavf_rxtx.h\n@@ -23,14 +23,21 @@\n #define IAVF_VPMD_DESCS_PER_LOOP 4\n #define IAVF_VPMD_TX_MAX_FREE_BUF 64\n \n-#define IAVF_NO_VECTOR_FLAGS (\t\t\t\t \\\n+#define IAVF_TX_NO_VECTOR_FLAGS (\t\t\t\t \\\n \t\tDEV_TX_OFFLOAD_MULTI_SEGS |\t\t \\\n+\t\tDEV_TX_OFFLOAD_TCP_TSO)\n+\n+#define IAVF_TX_VECTOR_OFFLOAD (\t\t\t\t \\\n \t\tDEV_TX_OFFLOAD_VLAN_INSERT |\t\t \\\n+\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\t\t \\\n+\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\t\t \\\n \t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\t\t \\\n \t\tDEV_TX_OFFLOAD_UDP_CKSUM |\t\t \\\n-\t\tDEV_TX_OFFLOAD_TCP_TSO |\t\t \\\n \t\tDEV_TX_OFFLOAD_TCP_CKSUM)\n \n+#define IAVF_VECTOR_PATH 0\n+#define IAVF_VECTOR_OFFLOAD_PATH 1\n+\n #define DEFAULT_TX_RS_THRESH 32\n #define DEFAULT_TX_FREE_THRESH 32\n \n@@ -488,6 +495,9 @@ uint16_t iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,\n \t\t\t\t\t\t uint16_t nb_pkts);\n uint16_t iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t uint16_t nb_pkts);\n+uint16_t iavf_xmit_pkts_vec_avx512_offload(void *tx_queue,\n+\t\t\t\t\t struct rte_mbuf **tx_pkts,\n+\t\t\t\t\t uint16_t nb_pkts);\n int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);\n \n uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);\ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\nindex 385f44e..f4dd222 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n@@ -1518,14 +1518,16 @@\n \t\ttxep[i].mbuf = tx_pkts[i];\n }\n \n-static inline void\n+static __rte_always_inline void\n iavf_vtx1(volatile struct iavf_tx_desc *txdp,\n-\t struct rte_mbuf *pkt, uint64_t flags)\n+\t struct rte_mbuf *pkt, uint64_t flags, bool offload)\n {\n \tuint64_t high_qw =\n \t\t(IAVF_TX_DESC_DTYPE_DATA |\n \t\t ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |\n \t\t ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));\n+\tif (offload)\n+\t\tiavf_txd_enable_offload(pkt, &high_qw);\n \n \t__m128i descriptor = _mm_set_epi64x(high_qw,\n \t\t\t\t\t pkt->buf_iova + pkt->data_off);\n@@ -1534,62 +1536,70 @@\n \n #define IAVF_TX_LEN_MASK 0xAA\n #define IAVF_TX_OFF_MASK 0x55\n-static inline void\n+static __rte_always_inline void\n iavf_vtx(volatile struct iavf_tx_desc *txdp,\n-\t struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n+\t struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags,\n+\t bool offload)\n {\n \tconst uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |\n \t\t\t((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT));\n \n \t/* if unaligned on 32-bit boundary, do one to align */\n \tif (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {\n-\t\tiavf_vtx1(txdp, *pkt, flags);\n+\t\tiavf_vtx1(txdp, *pkt, flags, offload);\n \t\tnb_pkts--, txdp++, pkt++;\n \t}\n \n \t/* do 4 at a time while possible, in bursts */\n \tfor (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {\n-\t\t__m512i desc4 =\n-\t\t\t_mm512_set_epi64\n-\t\t\t\t((uint64_t)pkt[3]->data_len,\n-\t\t\t\t pkt[3]->buf_iova,\n-\t\t\t\t (uint64_t)pkt[2]->data_len,\n-\t\t\t\t pkt[2]->buf_iova,\n-\t\t\t\t (uint64_t)pkt[1]->data_len,\n-\t\t\t\t pkt[1]->buf_iova,\n-\t\t\t\t (uint64_t)pkt[0]->data_len,\n-\t\t\t\t pkt[0]->buf_iova);\n-\t\t__m512i hi_qw_tmpl_4 = _mm512_set1_epi64(hi_qw_tmpl);\n-\t\t__m512i data_off_4 =\n+\t\tuint64_t hi_qw3 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[3]->data_len <<\n+\t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[3], &hi_qw3);\n+\t\tuint64_t hi_qw2 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[2]->data_len <<\n+\t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[2], &hi_qw2);\n+\t\tuint64_t hi_qw1 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[1]->data_len <<\n+\t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[1], &hi_qw1);\n+\t\tuint64_t hi_qw0 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[0]->data_len <<\n+\t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n+\t\tif (offload)\n+\t\t\tiavf_txd_enable_offload(pkt[0], &hi_qw0);\n+\n+\t\t__m512i desc0_3 =\n \t\t\t_mm512_set_epi64\n-\t\t\t\t(0,\n-\t\t\t\t pkt[3]->data_off,\n-\t\t\t\t 0,\n-\t\t\t\t pkt[2]->data_off,\n-\t\t\t\t 0,\n-\t\t\t\t pkt[1]->data_off,\n-\t\t\t\t 0,\n-\t\t\t\t pkt[0]->data_off);\n-\n-\t\tdesc4 = _mm512_mask_slli_epi64(desc4, IAVF_TX_LEN_MASK, desc4,\n-\t\t\t\t\t IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);\n-\t\tdesc4 = _mm512_mask_or_epi64(desc4, IAVF_TX_LEN_MASK, desc4,\n-\t\t\t\t\t hi_qw_tmpl_4);\n-\t\tdesc4 = _mm512_mask_add_epi64(desc4, IAVF_TX_OFF_MASK, desc4,\n-\t\t\t\t\t data_off_4);\n-\t\t_mm512_storeu_si512((void *)txdp, desc4);\n+\t\t\t\t(hi_qw3,\n+\t\t\t\t pkt[3]->buf_iova + pkt[3]->data_off,\n+\t\t\t\t hi_qw2,\n+\t\t\t\t pkt[2]->buf_iova + pkt[2]->data_off,\n+\t\t\t\t hi_qw1,\n+\t\t\t\t pkt[1]->buf_iova + pkt[1]->data_off,\n+\t\t\t\t hi_qw0,\n+\t\t\t\t pkt[0]->buf_iova + pkt[0]->data_off);\n+\t\t_mm512_storeu_si512((void *)txdp, desc0_3);\n \t}\n \n \t/* do any last ones */\n \twhile (nb_pkts) {\n-\t\tiavf_vtx1(txdp, *pkt, flags);\n+\t\tiavf_vtx1(txdp, *pkt, flags, offload);\n \t\ttxdp++, pkt++, nb_pkts--;\n \t}\n }\n \n-static inline uint16_t\n+static __rte_always_inline uint16_t\n iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t\t uint16_t nb_pkts)\n+\t\t\t\t uint16_t nb_pkts, bool offload)\n {\n \tstruct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;\n \tvolatile struct iavf_tx_desc *txdp;\n@@ -1620,11 +1630,11 @@\n \tif (nb_commit >= n) {\n \t\ttx_backlog_entry_avx512(txep, tx_pkts, n);\n \n-\t\tiavf_vtx(txdp, tx_pkts, n - 1, flags);\n+\t\tiavf_vtx(txdp, tx_pkts, n - 1, flags, offload);\n \t\ttx_pkts += (n - 1);\n \t\ttxdp += (n - 1);\n \n-\t\tiavf_vtx1(txdp, *tx_pkts++, rs);\n+\t\tiavf_vtx1(txdp, *tx_pkts++, rs, offload);\n \n \t\tnb_commit = (uint16_t)(nb_commit - n);\n \n@@ -1639,7 +1649,7 @@\n \n \ttx_backlog_entry_avx512(txep, tx_pkts, nb_commit);\n \n-\tiavf_vtx(txdp, tx_pkts, nb_commit, flags);\n+\tiavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);\n \n \ttx_id = (uint16_t)(tx_id + nb_commit);\n \tif (tx_id > txq->next_rs) {\n@@ -1657,9 +1667,9 @@\n \treturn nb_pkts;\n }\n \n-uint16_t\n-iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t\t uint16_t nb_pkts)\n+static __rte_always_inline uint16_t\n+iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts, bool offload)\n {\n \tuint16_t nb_tx = 0;\n \tstruct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;\n@@ -1669,7 +1679,7 @@\n \n \t\tnum = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);\n \t\tret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],\n-\t\t\t\t\t\t num);\n+\t\t\t\t\t\t num, offload);\n \t\tnb_tx += ret;\n \t\tnb_pkts -= ret;\n \t\tif (ret < num)\n@@ -1679,6 +1689,13 @@\n \treturn nb_tx;\n }\n \n+uint16_t\n+iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\treturn iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);\n+}\n+\n static inline void\n iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)\n {\n@@ -1709,3 +1726,10 @@\n \ttxq->ops = &avx512_vec_txq_ops;\n \treturn 0;\n }\n+\n+uint16_t\n+iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\t uint16_t nb_pkts)\n+{\n+\treturn iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);\n+}\ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_common.h b/drivers/net/iavf/iavf_rxtx_vec_common.h\nindex 816e16a..62a333f 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_common.h\n+++ b/drivers/net/iavf/iavf_rxtx_vec_common.h\n@@ -240,14 +240,17 @@\n \tif (!txq)\n \t\treturn -1;\n \n-\tif (txq->offloads & IAVF_NO_VECTOR_FLAGS)\n-\t\treturn -1;\n-\n \tif (txq->rs_thresh < IAVF_VPMD_TX_MAX_BURST ||\n \t txq->rs_thresh > IAVF_VPMD_TX_MAX_FREE_BUF)\n \t\treturn -1;\n \n-\treturn 0;\n+\tif (txq->offloads & IAVF_TX_NO_VECTOR_FLAGS)\n+\t\treturn -1;\n+\n+\tif (txq->offloads & IAVF_TX_VECTOR_OFFLOAD)\n+\t\treturn IAVF_VECTOR_OFFLOAD_PATH;\n+\n+\treturn IAVF_VECTOR_PATH;\n }\n \n static inline int\n@@ -270,14 +273,97 @@\n {\n \tint i;\n \tstruct iavf_tx_queue *txq;\n+\tint ret;\n+\tint result = 0;\n \n \tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n \t\ttxq = dev->data->tx_queues[i];\n-\t\tif (iavf_tx_vec_queue_default(txq))\n+\t\tret = iavf_tx_vec_queue_default(txq);\n+\n+\t\tif (ret < 0)\n \t\t\treturn -1;\n+\t\tif (ret > result)\n+\t\t\tresult = ret;\n \t}\n \n-\treturn 0;\n+\treturn result;\n+}\n+\n+/******************************************************************************\n+ * If user knows a specific offload is not enabled by APP,\n+ * the macro can be commented to save the effort of fast path.\n+ * Currently below 2 features are supported in TX path,\n+ * 1, checksum offload\n+ * 2, VLAN/QINQ insertion\n+ ******************************************************************************/\n+#define IAVF_TX_CSUM_OFFLOAD\n+#define IAVF_TX_VLAN_QINQ_OFFLOAD\n+\n+static __rte_always_inline void\n+iavf_txd_enable_offload(__rte_unused struct rte_mbuf *tx_pkt,\n+\t\t\tuint64_t *txd_hi)\n+{\n+#if defined(IAVF_TX_CSUM_OFFLOAD) || defined(IAVF_TX_VLAN_QINQ_OFFLOAD)\n+\tuint64_t ol_flags = tx_pkt->ol_flags;\n+#endif\n+\tuint32_t td_cmd = 0;\n+#ifdef IAVF_TX_CSUM_OFFLOAD\n+\tuint32_t td_offset = 0;\n+#endif\n+\n+#ifdef IAVF_TX_CSUM_OFFLOAD\n+\t/* Set MACLEN */\n+\ttd_offset |= (tx_pkt->l2_len >> 1) <<\n+\t\t IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;\n+\n+\t/* Enable L3 checksum offloads */\n+\tif (ol_flags & PKT_TX_IP_CKSUM) {\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;\n+\t\ttd_offset |= (tx_pkt->l3_len >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;\n+\t} else if (ol_flags & PKT_TX_IPV4) {\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;\n+\t\ttd_offset |= (tx_pkt->l3_len >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;\n+\t} else if (ol_flags & PKT_TX_IPV6) {\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;\n+\t\ttd_offset |= (tx_pkt->l3_len >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;\n+\t}\n+\n+\t/* Enable L4 checksum offloads */\n+\tswitch (ol_flags & PKT_TX_L4_MASK) {\n+\tcase PKT_TX_TCP_CKSUM:\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;\n+\t\ttd_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\tbreak;\n+\tcase PKT_TX_SCTP_CKSUM:\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;\n+\t\ttd_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\tbreak;\n+\tcase PKT_TX_UDP_CKSUM:\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;\n+\t\ttd_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<\n+\t\t\t IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t*txd_hi |= ((uint64_t)td_offset) << IAVF_TXD_QW1_OFFSET_SHIFT;\n+#endif\n+\n+#ifdef IAVF_TX_VLAN_QINQ_OFFLOAD\n+\tif (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {\n+\t\ttd_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;\n+\t\t*txd_hi |= ((uint64_t)tx_pkt->vlan_tci <<\n+\t\t\t IAVF_TXD_QW1_L2TAG1_SHIFT);\n+\t}\n+#endif\n+\n+\t*txd_hi |= ((uint64_t)td_cmd) << IAVF_TXD_QW1_CMD_SHIFT;\n }\n \n #ifdef CC_AVX2_SUPPORT\n", "prefixes": [ "v5", "2/4" ] }