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{
    "id": 91315,
    "url": "https://patches.dpdk.org/api/patches/91315/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-17-git-send-email-timothy.mcdaniel@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1618344896-2090-17-git-send-email-timothy.mcdaniel@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1618344896-2090-17-git-send-email-timothy.mcdaniel@intel.com",
    "date": "2021-04-13T20:14:46",
    "name": "[v3,16/26] event/dlb2: add v2.5 finish map/unmap",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "da4262f5f0b540d5b0c9f18ad7a6f9fd33375fb3",
    "submitter": {
        "id": 826,
        "url": "https://patches.dpdk.org/api/people/826/?format=api",
        "name": "Timothy McDaniel",
        "email": "timothy.mcdaniel@intel.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-17-git-send-email-timothy.mcdaniel@intel.com/mbox/",
    "series": [
        {
            "id": 16345,
            "url": "https://patches.dpdk.org/api/series/16345/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16345",
            "date": "2021-04-13T20:14:31",
            "name": "Add DLB V2.5",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/16345/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/91315/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/91315/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E4816A0524;\n\tTue, 13 Apr 2021 22:18:31 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7A7C7161346;\n\tTue, 13 Apr 2021 22:16:40 +0200 (CEST)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id EAEB41612D8\n for <dev@dpdk.org>; Tue, 13 Apr 2021 22:16:18 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 13:16:18 -0700",
            "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:18 -0700"
        ],
        "IronPort-SDR": [
            "\n 7JgcsLAr2r91hwwFNIUZoLJU5rBL8oV6pdquto6AVPplu47lJbC3BSgjlTsChnN/t2iJpGvvq+\n 1Pu1crTnTSMg==",
            "\n u92GVzouizvApM8UR1I4kMHVJGjYfLBtItuz7TlyFiSHxNXJ8kRaHUYtyeEl5c6+1bBvJUKXtY\n 1Z8rYRg1o+hw=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,9953\"; a=\"194519724\"",
            "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"194519724\"",
            "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"424406553\""
        ],
        "X-ExtLoop1": "1",
        "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>",
        "To": "",
        "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net",
        "Date": "Tue, 13 Apr 2021 15:14:46 -0500",
        "Message-Id": "<1618344896-2090-17-git-send-email-timothy.mcdaniel@intel.com>",
        "X-Mailer": "git-send-email 1.7.10",
        "In-Reply-To": "<1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>",
        "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 16/26] event/dlb2: add v2.5 finish map/unmap",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update low level hardware funcs with map/unmap interfaces,\naccounting for new combined register file and hardware access macros.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c    | 1054 -----------------\n .../event/dlb2/pf/base/dlb2_resource_new.c    |   50 +\n 2 files changed, 50 insertions(+), 1054 deletions(-)",
    "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 8c1d8c782..f05f750f5 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -54,1060 +54,6 @@ void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n \tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n }\n \n-/*\n- * The PF driver cannot assume that a register write will affect subsequent HCW\n- * writes. To ensure a write completes, the driver must read back a CSR. This\n- * function only need be called for configuration that can occur after the\n- * domain has started; prior to starting, applications can't send HCWs.\n- */\n-static inline void dlb2_flush_csr(struct dlb2_hw *hw)\n-{\n-\tDLB2_CSR_RD(hw, DLB2_SYS_TOTAL_VAS);\n-}\n-\n-static void dlb2_ldb_port_cq_enable(struct dlb2_hw *hw,\n-\t\t\t\t    struct dlb2_ldb_port *port)\n-{\n-\tunion dlb2_lsp_cq_ldb_dsbl reg;\n-\n-\t/*\n-\t * Don't re-enable the port if a removal is pending. The caller should\n-\t * mark this port as enabled (if it isn't already), and when the\n-\t * removal completes the port will be enabled.\n-\t */\n-\tif (port->num_pending_removals)\n-\t\treturn;\n-\n-\treg.field.disabled = 0;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n-static void dlb2_ldb_port_cq_disable(struct dlb2_hw *hw,\n-\t\t\t\t     struct dlb2_ldb_port *port)\n-{\n-\tunion dlb2_lsp_cq_ldb_dsbl reg;\n-\n-\treg.field.disabled = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_DSBL(port->id.phys_id), reg.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n-static struct dlb2_ldb_queue *\n-dlb2_get_ldb_queue_from_id(struct dlb2_hw *hw,\n-\t\t\t   u32 id,\n-\t\t\t   bool vdev_req,\n-\t\t\t   unsigned int vdev_id)\n-{\n-\tstruct dlb2_list_entry *iter1;\n-\tstruct dlb2_list_entry *iter2;\n-\tstruct dlb2_function_resources *rsrcs;\n-\tstruct dlb2_hw_domain *domain;\n-\tstruct dlb2_ldb_queue *queue;\n-\tRTE_SET_USED(iter1);\n-\tRTE_SET_USED(iter2);\n-\n-\tif (id >= DLB2_MAX_NUM_LDB_QUEUES)\n-\t\treturn NULL;\n-\n-\trsrcs = (vdev_req) ? &hw->vdev[vdev_id] : &hw->pf;\n-\n-\tif (!vdev_req)\n-\t\treturn &hw->rsrcs.ldb_queues[id];\n-\n-\tDLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iter1) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_queues, queue, iter2)\n-\t\t\tif (queue->id.virt_id == id)\n-\t\t\t\treturn queue;\n-\t}\n-\n-\tDLB2_FUNC_LIST_FOR(rsrcs->avail_ldb_queues, queue, iter1)\n-\t\tif (queue->id.virt_id == id)\n-\t\t\treturn queue;\n-\n-\treturn NULL;\n-}\n-\n-static struct dlb2_hw_domain *dlb2_get_domain_from_id(struct dlb2_hw *hw,\n-\t\t\t\t\t\t      u32 id,\n-\t\t\t\t\t\t      bool vdev_req,\n-\t\t\t\t\t\t      unsigned int vdev_id)\n-{\n-\tstruct dlb2_list_entry *iteration;\n-\tstruct dlb2_function_resources *rsrcs;\n-\tstruct dlb2_hw_domain *domain;\n-\tRTE_SET_USED(iteration);\n-\n-\tif (id >= DLB2_MAX_NUM_DOMAINS)\n-\t\treturn NULL;\n-\n-\tif (!vdev_req)\n-\t\treturn &hw->domains[id];\n-\n-\trsrcs = &hw->vdev[vdev_id];\n-\n-\tDLB2_FUNC_LIST_FOR(rsrcs->used_domains, domain, iteration)\n-\t\tif (domain->id.virt_id == id)\n-\t\t\treturn domain;\n-\n-\treturn NULL;\n-}\n-\n-static int dlb2_port_slot_state_transition(struct dlb2_hw *hw,\n-\t\t\t\t\t   struct dlb2_ldb_port *port,\n-\t\t\t\t\t   struct dlb2_ldb_queue *queue,\n-\t\t\t\t\t   int slot,\n-\t\t\t\t\t   enum dlb2_qid_map_state new_state)\n-{\n-\tenum dlb2_qid_map_state curr_state = port->qid_map[slot].state;\n-\tstruct dlb2_hw_domain *domain;\n-\tint domain_id;\n-\n-\tdomain_id = port->domain_id.phys_id;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, false, 0);\n-\tif (domain == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s()] Internal error: unable to find domain %d\\n\",\n-\t\t\t    __func__, domain_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tswitch (curr_state) {\n-\tcase DLB2_QUEUE_UNMAPPED:\n-\t\tswitch (new_state) {\n-\t\tcase DLB2_QUEUE_MAPPED:\n-\t\t\tqueue->num_mappings++;\n-\t\t\tport->num_mappings++;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_MAP_IN_PROG:\n-\t\t\tqueue->num_pending_additions++;\n-\t\t\tdomain->num_pending_additions++;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tgoto error;\n-\t\t}\n-\t\tbreak;\n-\tcase DLB2_QUEUE_MAPPED:\n-\t\tswitch (new_state) {\n-\t\tcase DLB2_QUEUE_UNMAPPED:\n-\t\t\tqueue->num_mappings--;\n-\t\t\tport->num_mappings--;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n-\t\t\tport->num_pending_removals++;\n-\t\t\tdomain->num_pending_removals++;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_MAPPED:\n-\t\t\t/* Priority change, nothing to update */\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tgoto error;\n-\t\t}\n-\t\tbreak;\n-\tcase DLB2_QUEUE_MAP_IN_PROG:\n-\t\tswitch (new_state) {\n-\t\tcase DLB2_QUEUE_UNMAPPED:\n-\t\t\tqueue->num_pending_additions--;\n-\t\t\tdomain->num_pending_additions--;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_MAPPED:\n-\t\t\tqueue->num_mappings++;\n-\t\t\tport->num_mappings++;\n-\t\t\tqueue->num_pending_additions--;\n-\t\t\tdomain->num_pending_additions--;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tgoto error;\n-\t\t}\n-\t\tbreak;\n-\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n-\t\tswitch (new_state) {\n-\t\tcase DLB2_QUEUE_UNMAPPED:\n-\t\t\tport->num_pending_removals--;\n-\t\t\tdomain->num_pending_removals--;\n-\t\t\tqueue->num_mappings--;\n-\t\t\tport->num_mappings--;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_MAPPED:\n-\t\t\tport->num_pending_removals--;\n-\t\t\tdomain->num_pending_removals--;\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:\n-\t\t\t/* Nothing to update */\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tgoto error;\n-\t\t}\n-\t\tbreak;\n-\tcase DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP:\n-\t\tswitch (new_state) {\n-\t\tcase DLB2_QUEUE_UNMAP_IN_PROG:\n-\t\t\t/* Nothing to update */\n-\t\t\tbreak;\n-\t\tcase DLB2_QUEUE_UNMAPPED:\n-\t\t\t/*\n-\t\t\t * An UNMAP_IN_PROG_PENDING_MAP slot briefly\n-\t\t\t * becomes UNMAPPED before it transitions to\n-\t\t\t * MAP_IN_PROG.\n-\t\t\t */\n-\t\t\tqueue->num_mappings--;\n-\t\t\tport->num_mappings--;\n-\t\t\tport->num_pending_removals--;\n-\t\t\tdomain->num_pending_removals--;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tgoto error;\n-\t\t}\n-\t\tbreak;\n-\tdefault:\n-\t\tgoto error;\n-\t}\n-\n-\tport->qid_map[slot].state = new_state;\n-\n-\tDLB2_HW_DBG(hw,\n-\t\t    \"[%s()] queue %d -> port %d state transition (%d -> %d)\\n\",\n-\t\t    __func__, queue->id.phys_id, port->id.phys_id,\n-\t\t    curr_state, new_state);\n-\treturn 0;\n-\n-error:\n-\tDLB2_HW_ERR(hw,\n-\t\t    \"[%s()] Internal error: invalid queue %d -> port %d state transition (%d -> %d)\\n\",\n-\t\t    __func__, queue->id.phys_id, port->id.phys_id,\n-\t\t    curr_state, new_state);\n-\treturn -EFAULT;\n-}\n-\n-static bool dlb2_port_find_slot(struct dlb2_ldb_port *port,\n-\t\t\t\tenum dlb2_qid_map_state state,\n-\t\t\t\tint *slot)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n-\t\tif (port->qid_map[i].state == state)\n-\t\t\tbreak;\n-\t}\n-\n-\t*slot = i;\n-\n-\treturn (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);\n-}\n-\n-static bool dlb2_port_find_slot_queue(struct dlb2_ldb_port *port,\n-\t\t\t\t      enum dlb2_qid_map_state state,\n-\t\t\t\t      struct dlb2_ldb_queue *queue,\n-\t\t\t\t      int *slot)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n-\t\tif (port->qid_map[i].state == state &&\n-\t\t    port->qid_map[i].qid == queue->id.phys_id)\n-\t\t\tbreak;\n-\t}\n-\n-\t*slot = i;\n-\n-\treturn (i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ);\n-}\n-\n-/*\n- * dlb2_ldb_queue_{enable, disable}_mapped_cqs() don't operate exactly as\n- * their function names imply, and should only be called by the dynamic CQ\n- * mapping code.\n- */\n-static void dlb2_ldb_queue_disable_mapped_cqs(struct dlb2_hw *hw,\n-\t\t\t\t\t      struct dlb2_hw_domain *domain,\n-\t\t\t\t\t      struct dlb2_ldb_queue *queue)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_ldb_port *port;\n-\tint slot, i;\n-\tRTE_SET_USED(iter);\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n-\t\t\tenum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;\n-\n-\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n-\t\t\t\t\t\t       queue, &slot))\n-\t\t\t\tcontinue;\n-\n-\t\t\tif (port->enabled)\n-\t\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n-\t\t}\n-\t}\n-}\n-\n-static void dlb2_ldb_queue_enable_mapped_cqs(struct dlb2_hw *hw,\n-\t\t\t\t\t     struct dlb2_hw_domain *domain,\n-\t\t\t\t\t     struct dlb2_ldb_queue *queue)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_ldb_port *port;\n-\tint slot, i;\n-\tRTE_SET_USED(iter);\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n-\t\t\tenum dlb2_qid_map_state state = DLB2_QUEUE_MAPPED;\n-\n-\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n-\t\t\t\t\t\t       queue, &slot))\n-\t\t\t\tcontinue;\n-\n-\t\t\tif (port->enabled)\n-\t\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n-\t\t}\n-\t}\n-}\n-\n-static void dlb2_ldb_port_clear_queue_if_status(struct dlb2_hw *hw,\n-\t\t\t\t\t\tstruct dlb2_ldb_port *port,\n-\t\t\t\t\t\tint slot)\n-{\n-\tunion dlb2_lsp_ldb_sched_ctrl r0 = { {0} };\n-\n-\tr0.field.cq = port->id.phys_id;\n-\tr0.field.qidix = slot;\n-\tr0.field.value = 0;\n-\tr0.field.inflight_ok_v = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n-static void dlb2_ldb_port_set_queue_if_status(struct dlb2_hw *hw,\n-\t\t\t\t\t      struct dlb2_ldb_port *port,\n-\t\t\t\t\t      int slot)\n-{\n-\tunion dlb2_lsp_ldb_sched_ctrl r0 = { {0} };\n-\n-\tr0.field.cq = port->id.phys_id;\n-\tr0.field.qidix = slot;\n-\tr0.field.value = 1;\n-\tr0.field.inflight_ok_v = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r0.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n-static int dlb2_ldb_port_map_qid_static(struct dlb2_hw *hw,\n-\t\t\t\t\tstruct dlb2_ldb_port *p,\n-\t\t\t\t\tstruct dlb2_ldb_queue *q,\n-\t\t\t\t\tu8 priority)\n-{\n-\tunion dlb2_lsp_cq2priov r0;\n-\tunion dlb2_lsp_cq2qid0 r1;\n-\tunion dlb2_atm_qid2cqidix_00 r2;\n-\tunion dlb2_lsp_qid2cqidix_00 r3;\n-\tunion dlb2_lsp_qid2cqidix2_00 r4;\n-\tenum dlb2_qid_map_state state;\n-\tint i;\n-\n-\t/* Look for a pending or already mapped slot, else an unused slot */\n-\tif (!dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAP_IN_PROG, q, &i) &&\n-\t    !dlb2_port_find_slot_queue(p, DLB2_QUEUE_MAPPED, q, &i) &&\n-\t    !dlb2_port_find_slot(p, DLB2_QUEUE_UNMAPPED, &i)) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: CQ has no available QID mapping slots\\n\",\n-\t\t\t    __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: port slot tracking failed\\n\",\n-\t\t\t    __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\t/* Read-modify-write the priority and valid bit register */\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id));\n-\n-\tr0.field.v |= 1 << i;\n-\tr0.field.prio |= (priority & 0x7) << i * 3;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(p->id.phys_id), r0.val);\n-\n-\t/* Read-modify-write the QID map register */\n-\tif (i < 4)\n-\t\tr1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID0(p->id.phys_id));\n-\telse\n-\t\tr1.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2QID1(p->id.phys_id));\n-\n-\tif (i == 0 || i == 4)\n-\t\tr1.field.qid_p0 = q->id.phys_id;\n-\tif (i == 1 || i == 5)\n-\t\tr1.field.qid_p1 = q->id.phys_id;\n-\tif (i == 2 || i == 6)\n-\t\tr1.field.qid_p2 = q->id.phys_id;\n-\tif (i == 3 || i == 7)\n-\t\tr1.field.qid_p3 = q->id.phys_id;\n-\n-\tif (i < 4)\n-\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2QID0(p->id.phys_id), r1.val);\n-\telse\n-\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2QID1(p->id.phys_id), r1.val);\n-\n-\tr2.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_ATM_QID2CQIDIX(q->id.phys_id,\n-\t\t\t\t\t\t p->id.phys_id / 4));\n-\n-\tr3.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID2CQIDIX(q->id.phys_id,\n-\t\t\t\t\t\t p->id.phys_id / 4));\n-\n-\tr4.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID2CQIDIX2(q->id.phys_id,\n-\t\t\t\t\t\t  p->id.phys_id / 4));\n-\n-\tswitch (p->id.phys_id % 4) {\n-\tcase 0:\n-\t\tr2.field.cq_p0 |= 1 << i;\n-\t\tr3.field.cq_p0 |= 1 << i;\n-\t\tr4.field.cq_p0 |= 1 << i;\n-\t\tbreak;\n-\n-\tcase 1:\n-\t\tr2.field.cq_p1 |= 1 << i;\n-\t\tr3.field.cq_p1 |= 1 << i;\n-\t\tr4.field.cq_p1 |= 1 << i;\n-\t\tbreak;\n-\n-\tcase 2:\n-\t\tr2.field.cq_p2 |= 1 << i;\n-\t\tr3.field.cq_p2 |= 1 << i;\n-\t\tr4.field.cq_p2 |= 1 << i;\n-\t\tbreak;\n-\n-\tcase 3:\n-\t\tr2.field.cq_p3 |= 1 << i;\n-\t\tr3.field.cq_p3 |= 1 << i;\n-\t\tr4.field.cq_p3 |= 1 << i;\n-\t\tbreak;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_ATM_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),\n-\t\t    r2.val);\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_LSP_QID2CQIDIX(q->id.phys_id, p->id.phys_id / 4),\n-\t\t    r3.val);\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_LSP_QID2CQIDIX2(q->id.phys_id, p->id.phys_id / 4),\n-\t\t    r4.val);\n-\n-\tdlb2_flush_csr(hw);\n-\n-\tp->qid_map[i].qid = q->id.phys_id;\n-\tp->qid_map[i].priority = priority;\n-\n-\tstate = DLB2_QUEUE_MAPPED;\n-\n-\treturn dlb2_port_slot_state_transition(hw, p, q, i, state);\n-}\n-\n-static int dlb2_ldb_port_set_has_work_bits(struct dlb2_hw *hw,\n-\t\t\t\t\t   struct dlb2_ldb_port *port,\n-\t\t\t\t\t   struct dlb2_ldb_queue *queue,\n-\t\t\t\t\t   int slot)\n-{\n-\tunion dlb2_lsp_qid_aqed_active_cnt r0;\n-\tunion dlb2_lsp_qid_ldb_enqueue_cnt r1;\n-\tunion dlb2_lsp_ldb_sched_ctrl r2 = { {0} };\n-\n-\t/* Set the atomic scheduling haswork bit */\n-\tr0.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID_AQED_ACTIVE_CNT(queue->id.phys_id));\n-\n-\tr2.field.cq = port->id.phys_id;\n-\tr2.field.qidix = slot;\n-\tr2.field.value = 1;\n-\tr2.field.rlist_haswork_v = r0.field.count > 0;\n-\n-\t/* Set the non-atomic scheduling haswork bit */\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n-\n-\tr1.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID_LDB_ENQUEUE_CNT(queue->id.phys_id));\n-\n-\tmemset(&r2, 0, sizeof(r2));\n-\n-\tr2.field.cq = port->id.phys_id;\n-\tr2.field.qidix = slot;\n-\tr2.field.value = 1;\n-\tr2.field.nalb_haswork_v = (r1.field.count > 0);\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n-\n-\tdlb2_flush_csr(hw);\n-\n-\treturn 0;\n-}\n-\n-static void dlb2_ldb_port_clear_has_work_bits(struct dlb2_hw *hw,\n-\t\t\t\t\t      struct dlb2_ldb_port *port,\n-\t\t\t\t\t      u8 slot)\n-{\n-\tunion dlb2_lsp_ldb_sched_ctrl r2 = { {0} };\n-\n-\tr2.field.cq = port->id.phys_id;\n-\tr2.field.qidix = slot;\n-\tr2.field.value = 0;\n-\tr2.field.rlist_haswork_v = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n-\n-\tmemset(&r2, 0, sizeof(r2));\n-\n-\tr2.field.cq = port->id.phys_id;\n-\tr2.field.qidix = slot;\n-\tr2.field.value = 0;\n-\tr2.field.nalb_haswork_v = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_LDB_SCHED_CTRL, r2.val);\n-\n-\tdlb2_flush_csr(hw);\n-}\n-\n-static void dlb2_ldb_queue_set_inflight_limit(struct dlb2_hw *hw,\n-\t\t\t\t\t      struct dlb2_ldb_queue *queue)\n-{\n-\tunion dlb2_lsp_qid_ldb_infl_lim r0 = { {0} };\n-\n-\tr0.field.limit = queue->num_qid_inflights;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), r0.val);\n-}\n-\n-static void dlb2_ldb_queue_clear_inflight_limit(struct dlb2_hw *hw,\n-\t\t\t\t\t\tstruct dlb2_ldb_queue *queue)\n-{\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id),\n-\t\t    DLB2_LSP_QID_LDB_INFL_LIM_RST);\n-}\n-\n-static int dlb2_ldb_port_finish_map_qid_dynamic(struct dlb2_hw *hw,\n-\t\t\t\t\t\tstruct dlb2_hw_domain *domain,\n-\t\t\t\t\t\tstruct dlb2_ldb_port *port,\n-\t\t\t\t\t\tstruct dlb2_ldb_queue *queue)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tunion dlb2_lsp_qid_ldb_infl_cnt r0;\n-\tenum dlb2_qid_map_state state;\n-\tint slot, ret, i;\n-\tu8 prio;\n-\tRTE_SET_USED(iter);\n-\n-\tr0.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n-\n-\tif (r0.field.count) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s()] Internal error: non-zero QID inflight count\\n\",\n-\t\t\t    __func__);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/*\n-\t * Static map the port and set its corresponding has_work bits.\n-\t */\n-\tstate = DLB2_QUEUE_MAP_IN_PROG;\n-\tif (!dlb2_port_find_slot_queue(port, state, queue, &slot))\n-\t\treturn -EINVAL;\n-\n-\tif (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: port slot tracking failed\\n\",\n-\t\t\t    __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tprio = port->qid_map[slot].priority;\n-\n-\t/*\n-\t * Update the CQ2QID, CQ2PRIOV, and QID2CQIDX registers, and\n-\t * the port's qid_map state.\n-\t */\n-\tret = dlb2_ldb_port_map_qid_static(hw, port, queue, prio);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = dlb2_ldb_port_set_has_work_bits(hw, port, queue, slot);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/*\n-\t * Ensure IF_status(cq,qid) is 0 before enabling the port to\n-\t * prevent spurious schedules to cause the queue's inflight\n-\t * count to increase.\n-\t */\n-\tdlb2_ldb_port_clear_queue_if_status(hw, port, slot);\n-\n-\t/* Reset the queue's inflight status */\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n-\t\t\tstate = DLB2_QUEUE_MAPPED;\n-\t\t\tif (!dlb2_port_find_slot_queue(port, state,\n-\t\t\t\t\t\t       queue, &slot))\n-\t\t\t\tcontinue;\n-\n-\t\t\tdlb2_ldb_port_set_queue_if_status(hw, port, slot);\n-\t\t}\n-\t}\n-\n-\tdlb2_ldb_queue_set_inflight_limit(hw, queue);\n-\n-\t/* Re-enable CQs mapped to this queue */\n-\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n-\n-\t/* If this queue has other mappings pending, clear its inflight limit */\n-\tif (queue->num_pending_additions > 0)\n-\t\tdlb2_ldb_queue_clear_inflight_limit(hw, queue);\n-\n-\treturn 0;\n-}\n-\n-/**\n- * dlb2_ldb_port_map_qid_dynamic() - perform a \"dynamic\" QID->CQ mapping\n- * @hw: dlb2_hw handle for a particular device.\n- * @port: load-balanced port\n- * @queue: load-balanced queue\n- * @priority: queue servicing priority\n- *\n- * Returns 0 if the queue was mapped, 1 if the mapping is scheduled to occur\n- * at a later point, and <0 if an error occurred.\n- */\n-static int dlb2_ldb_port_map_qid_dynamic(struct dlb2_hw *hw,\n-\t\t\t\t\t struct dlb2_ldb_port *port,\n-\t\t\t\t\t struct dlb2_ldb_queue *queue,\n-\t\t\t\t\t u8 priority)\n-{\n-\tunion dlb2_lsp_qid_ldb_infl_cnt r0 = { {0} };\n-\tenum dlb2_qid_map_state state;\n-\tstruct dlb2_hw_domain *domain;\n-\tint domain_id, slot, ret;\n-\n-\tdomain_id = port->domain_id.phys_id;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, false, 0);\n-\tif (domain == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s()] Internal error: unable to find domain %d\\n\",\n-\t\t\t    __func__, port->domain_id.phys_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/*\n-\t * Set the QID inflight limit to 0 to prevent further scheduling of the\n-\t * queue.\n-\t */\n-\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), 0);\n-\n-\tif (!dlb2_port_find_slot(port, DLB2_QUEUE_UNMAPPED, &slot)) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"Internal error: No available unmapped slots\\n\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (slot >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: port slot tracking failed\\n\",\n-\t\t\t    __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tport->qid_map[slot].qid = queue->id.phys_id;\n-\tport->qid_map[slot].priority = priority;\n-\n-\tstate = DLB2_QUEUE_MAP_IN_PROG;\n-\tret = dlb2_port_slot_state_transition(hw, port, queue, slot, state);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tr0.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n-\n-\tif (r0.field.count) {\n-\t\t/*\n-\t\t * The queue is owed completions so it's not safe to map it\n-\t\t * yet. Schedule a kernel thread to complete the mapping later,\n-\t\t * once software has completed all the queue's inflight events.\n-\t\t */\n-\t\tif (!os_worker_active(hw))\n-\t\t\tos_schedule_work(hw);\n-\n-\t\treturn 1;\n-\t}\n-\n-\t/*\n-\t * Disable the affected CQ, and the CQs already mapped to the QID,\n-\t * before reading the QID's inflight count a second time. There is an\n-\t * unlikely race in which the QID may schedule one more QE after we\n-\t * read an inflight count of 0, and disabling the CQs guarantees that\n-\t * the race will not occur after a re-read of the inflight count\n-\t * register.\n-\t */\n-\tif (port->enabled)\n-\t\tdlb2_ldb_port_cq_disable(hw, port);\n-\n-\tdlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);\n-\n-\tr0.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID_LDB_INFL_CNT(queue->id.phys_id));\n-\n-\tif (r0.field.count) {\n-\t\tif (port->enabled)\n-\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n-\n-\t\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n-\n-\t\t/*\n-\t\t * The queue is owed completions so it's not safe to map it\n-\t\t * yet. Schedule a kernel thread to complete the mapping later,\n-\t\t * once software has completed all the queue's inflight events.\n-\t\t */\n-\t\tif (!os_worker_active(hw))\n-\t\t\tos_schedule_work(hw);\n-\n-\t\treturn 1;\n-\t}\n-\n-\treturn dlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);\n-}\n-\n-static void dlb2_domain_finish_map_port(struct dlb2_hw *hw,\n-\t\t\t\t\tstruct dlb2_hw_domain *domain,\n-\t\t\t\t\tstruct dlb2_ldb_port *port)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n-\t\tunion dlb2_lsp_qid_ldb_infl_cnt r0;\n-\t\tstruct dlb2_ldb_queue *queue;\n-\t\tint qid;\n-\n-\t\tif (port->qid_map[i].state != DLB2_QUEUE_MAP_IN_PROG)\n-\t\t\tcontinue;\n-\n-\t\tqid = port->qid_map[i].qid;\n-\n-\t\tqueue = dlb2_get_ldb_queue_from_id(hw, qid, false, 0);\n-\n-\t\tif (queue == NULL) {\n-\t\t\tDLB2_HW_ERR(hw,\n-\t\t\t\t    \"[%s()] Internal error: unable to find queue %d\\n\",\n-\t\t\t\t    __func__, qid);\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));\n-\n-\t\tif (r0.field.count)\n-\t\t\tcontinue;\n-\n-\t\t/*\n-\t\t * Disable the affected CQ, and the CQs already mapped to the\n-\t\t * QID, before reading the QID's inflight count a second time.\n-\t\t * There is an unlikely race in which the QID may schedule one\n-\t\t * more QE after we read an inflight count of 0, and disabling\n-\t\t * the CQs guarantees that the race will not occur after a\n-\t\t * re-read of the inflight count register.\n-\t\t */\n-\t\tif (port->enabled)\n-\t\t\tdlb2_ldb_port_cq_disable(hw, port);\n-\n-\t\tdlb2_ldb_queue_disable_mapped_cqs(hw, domain, queue);\n-\n-\t\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_QID_LDB_INFL_CNT(qid));\n-\n-\t\tif (r0.field.count) {\n-\t\t\tif (port->enabled)\n-\t\t\t\tdlb2_ldb_port_cq_enable(hw, port);\n-\n-\t\t\tdlb2_ldb_queue_enable_mapped_cqs(hw, domain, queue);\n-\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tdlb2_ldb_port_finish_map_qid_dynamic(hw, domain, port, queue);\n-\t}\n-}\n-\n-static unsigned int\n-dlb2_domain_finish_map_qid_procedures(struct dlb2_hw *hw,\n-\t\t\t\t      struct dlb2_hw_domain *domain)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_ldb_port *port;\n-\tint i;\n-\tRTE_SET_USED(iter);\n-\n-\tif (!domain->configured || domain->num_pending_additions == 0)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n-\t\t\tdlb2_domain_finish_map_port(hw, domain, port);\n-\t}\n-\n-\treturn domain->num_pending_additions;\n-}\n-\n-static int dlb2_ldb_port_unmap_qid(struct dlb2_hw *hw,\n-\t\t\t\t   struct dlb2_ldb_port *port,\n-\t\t\t\t   struct dlb2_ldb_queue *queue)\n-{\n-\tenum dlb2_qid_map_state mapped, in_progress, pending_map, unmapped;\n-\tunion dlb2_lsp_cq2priov r0;\n-\tunion dlb2_atm_qid2cqidix_00 r1;\n-\tunion dlb2_lsp_qid2cqidix_00 r2;\n-\tunion dlb2_lsp_qid2cqidix2_00 r3;\n-\tu32 queue_id;\n-\tu32 port_id;\n-\tint i;\n-\n-\t/* Find the queue's slot */\n-\tmapped = DLB2_QUEUE_MAPPED;\n-\tin_progress = DLB2_QUEUE_UNMAP_IN_PROG;\n-\tpending_map = DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP;\n-\n-\tif (!dlb2_port_find_slot_queue(port, mapped, queue, &i) &&\n-\t    !dlb2_port_find_slot_queue(port, in_progress, queue, &i) &&\n-\t    !dlb2_port_find_slot_queue(port, pending_map, queue, &i)) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: QID %d isn't mapped\\n\",\n-\t\t\t    __func__, __LINE__, queue->id.phys_id);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tif (i >= DLB2_MAX_NUM_QIDS_PER_LDB_CQ) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t    \"[%s():%d] Internal error: port slot tracking failed\\n\",\n-\t\t\t    __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tport_id = port->id.phys_id;\n-\tqueue_id = queue->id.phys_id;\n-\n-\t/* Read-modify-write the priority and valid bit register */\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ2PRIOV(port_id));\n-\n-\tr0.field.v &= ~(1 << i);\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port_id), r0.val);\n-\n-\tr1.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4));\n-\n-\tr2.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4));\n-\n-\tr3.val = DLB2_CSR_RD(hw,\n-\t\t\t     DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4));\n-\n-\tswitch (port_id % 4) {\n-\tcase 0:\n-\t\tr1.field.cq_p0 &= ~(1 << i);\n-\t\tr2.field.cq_p0 &= ~(1 << i);\n-\t\tr3.field.cq_p0 &= ~(1 << i);\n-\t\tbreak;\n-\n-\tcase 1:\n-\t\tr1.field.cq_p1 &= ~(1 << i);\n-\t\tr2.field.cq_p1 &= ~(1 << i);\n-\t\tr3.field.cq_p1 &= ~(1 << i);\n-\t\tbreak;\n-\n-\tcase 2:\n-\t\tr1.field.cq_p2 &= ~(1 << i);\n-\t\tr2.field.cq_p2 &= ~(1 << i);\n-\t\tr3.field.cq_p2 &= ~(1 << i);\n-\t\tbreak;\n-\n-\tcase 3:\n-\t\tr1.field.cq_p3 &= ~(1 << i);\n-\t\tr2.field.cq_p3 &= ~(1 << i);\n-\t\tr3.field.cq_p3 &= ~(1 << i);\n-\t\tbreak;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_ATM_QID2CQIDIX(queue_id, port_id / 4),\n-\t\t    r1.val);\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_LSP_QID2CQIDIX(queue_id, port_id / 4),\n-\t\t    r2.val);\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t    DLB2_LSP_QID2CQIDIX2(queue_id, port_id / 4),\n-\t\t    r3.val);\n-\n-\tdlb2_flush_csr(hw);\n-\n-\tunmapped = DLB2_QUEUE_UNMAPPED;\n-\n-\treturn dlb2_port_slot_state_transition(hw, port, queue, i, unmapped);\n-}\n-\n-static int dlb2_ldb_port_map_qid(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_ldb_port *port,\n-\t\t\t\t struct dlb2_ldb_queue *queue,\n-\t\t\t\t u8 prio)\n-{\n-\tif (domain->started)\n-\t\treturn dlb2_ldb_port_map_qid_dynamic(hw, port, queue, prio);\n-\telse\n-\t\treturn dlb2_ldb_port_map_qid_static(hw, port, queue, prio);\n-}\n-\n-static void\n-dlb2_domain_finish_unmap_port_slot(struct dlb2_hw *hw,\n-\t\t\t\t   struct dlb2_hw_domain *domain,\n-\t\t\t\t   struct dlb2_ldb_port *port,\n-\t\t\t\t   int slot)\n-{\n-\tenum dlb2_qid_map_state state;\n-\tstruct dlb2_ldb_queue *queue;\n-\n-\tqueue = &hw->rsrcs.ldb_queues[port->qid_map[slot].qid];\n-\n-\tstate = port->qid_map[slot].state;\n-\n-\t/* Update the QID2CQIDX and CQ2QID vectors */\n-\tdlb2_ldb_port_unmap_qid(hw, port, queue);\n-\n-\t/*\n-\t * Ensure the QID will not be serviced by this {CQ, slot} by clearing\n-\t * the has_work bits\n-\t */\n-\tdlb2_ldb_port_clear_has_work_bits(hw, port, slot);\n-\n-\t/* Reset the {CQ, slot} to its default state */\n-\tdlb2_ldb_port_set_queue_if_status(hw, port, slot);\n-\n-\t/* Re-enable the CQ if it wasn't manually disabled by the user */\n-\tif (port->enabled)\n-\t\tdlb2_ldb_port_cq_enable(hw, port);\n-\n-\t/*\n-\t * If there is a mapping that is pending this slot's removal, perform\n-\t * the mapping now.\n-\t */\n-\tif (state == DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP) {\n-\t\tstruct dlb2_ldb_port_qid_map *map;\n-\t\tstruct dlb2_ldb_queue *map_queue;\n-\t\tu8 prio;\n-\n-\t\tmap = &port->qid_map[slot];\n-\n-\t\tmap->qid = map->pending_qid;\n-\t\tmap->priority = map->pending_priority;\n-\n-\t\tmap_queue = &hw->rsrcs.ldb_queues[map->qid];\n-\t\tprio = map->priority;\n-\n-\t\tdlb2_ldb_port_map_qid(hw, domain, port, map_queue, prio);\n-\t}\n-}\n-\n-static bool dlb2_domain_finish_unmap_port(struct dlb2_hw *hw,\n-\t\t\t\t\t  struct dlb2_hw_domain *domain,\n-\t\t\t\t\t  struct dlb2_ldb_port *port)\n-{\n-\tunion dlb2_lsp_cq_ldb_infl_cnt r0;\n-\tint i;\n-\n-\tif (port->num_pending_removals == 0)\n-\t\treturn false;\n-\n-\t/*\n-\t * The unmap requires all the CQ's outstanding inflights to be\n-\t * completed.\n-\t */\n-\tr0.val = DLB2_CSR_RD(hw, DLB2_LSP_CQ_LDB_INFL_CNT(port->id.phys_id));\n-\tif (r0.field.count > 0)\n-\t\treturn false;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {\n-\t\tstruct dlb2_ldb_port_qid_map *map;\n-\n-\t\tmap = &port->qid_map[i];\n-\n-\t\tif (map->state != DLB2_QUEUE_UNMAP_IN_PROG &&\n-\t\t    map->state != DLB2_QUEUE_UNMAP_IN_PROG_PENDING_MAP)\n-\t\t\tcontinue;\n-\n-\t\tdlb2_domain_finish_unmap_port_slot(hw, domain, port, i);\n-\t}\n-\n-\treturn true;\n-}\n-\n-static unsigned int\n-dlb2_domain_finish_unmap_qid_procedures(struct dlb2_hw *hw,\n-\t\t\t\t\tstruct dlb2_hw_domain *domain)\n-{\n-\tstruct dlb2_list_entry *iter;\n-\tstruct dlb2_ldb_port *port;\n-\tint i;\n-\tRTE_SET_USED(iter);\n-\n-\tif (!domain->configured || domain->num_pending_removals == 0)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter)\n-\t\t\tdlb2_domain_finish_unmap_port(hw, domain, port);\n-\t}\n-\n-\treturn domain->num_pending_removals;\n-}\n-\n-unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw)\n-{\n-\tint i, num = 0;\n-\n-\t/* Finish queue unmap jobs for any domain that needs it */\n-\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n-\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n-\n-\t\tnum += dlb2_domain_finish_unmap_qid_procedures(hw, domain);\n-\t}\n-\n-\treturn num;\n-}\n-\n-unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n-{\n-\tint i, num = 0;\n-\n-\t/* Finish queue map jobs for any domain that needs it */\n-\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n-\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n-\n-\t\tnum += dlb2_domain_finish_map_qid_procedures(hw, domain);\n-\t}\n-\n-\treturn num;\n-}\n-\n int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)\n {\n \tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 6a5af0c1e..8cd1762cf 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -6039,3 +6039,53 @@ int dlb2_hw_get_ldb_queue_depth(struct dlb2_hw *hw,\n \n \treturn 0;\n }\n+\n+/**\n+ * dlb2_finish_unmap_qid_procedures() - finish any pending unmap procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding unmap procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_unmap_qid_procedures(struct dlb2_hw *hw)\n+{\n+\tint i, num = 0;\n+\n+\t/* Finish queue unmap jobs for any domain that needs it */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n+\n+\t\tnum += dlb2_domain_finish_unmap_qid_procedures(hw, domain);\n+\t}\n+\n+\treturn num;\n+}\n+\n+/**\n+ * dlb2_finish_map_qid_procedures() - finish any pending map procedures\n+ * @hw: dlb2_hw handle for a particular device.\n+ *\n+ * This function attempts to finish any outstanding map procedures.\n+ * This function should be called by the kernel thread responsible for\n+ * finishing map/unmap procedures.\n+ *\n+ * Return:\n+ * Returns the number of procedures that weren't completed.\n+ */\n+unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n+{\n+\tint i, num = 0;\n+\n+\t/* Finish queue map jobs for any domain that needs it */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tstruct dlb2_hw_domain *domain = &hw->domains[i];\n+\n+\t\tnum += dlb2_domain_finish_map_qid_procedures(hw, domain);\n+\t}\n+\n+\treturn num;\n+}\n",
    "prefixes": [
        "v3",
        "16/26"
    ]
}