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GET /api/patches/91305/?format=api
{ "id": 91305, "url": "https://patches.dpdk.org/api/patches/91305/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-8-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1618344896-2090-8-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1618344896-2090-8-git-send-email-timothy.mcdaniel@intel.com", "date": "2021-04-13T20:14:37", "name": "[v3,07/26] event/dlb2: add V2.5 create ldb queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "170fec54a30ec3cb11cf53d1b8c5d27306f8271e", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1618344896-2090-8-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 16345, "url": "https://patches.dpdk.org/api/series/16345/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16345", "date": "2021-04-13T20:14:31", "name": "Add DLB V2.5", "version": 3, "mbox": "https://patches.dpdk.org/series/16345/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/91305/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/91305/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3C48AA0524;\n\tTue, 13 Apr 2021 22:17:03 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 790CA1612F0;\n\tTue, 13 Apr 2021 22:16:24 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id 339391612C2\n for <dev@dpdk.org>; Tue, 13 Apr 2021 22:16:15 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Apr 2021 13:16:13 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga008.jf.intel.com with ESMTP; 13 Apr 2021 13:16:12 -0700" ], "IronPort-SDR": [ "\n Ys10oNw4DhYm/+izfcKFi3uHuxeHClpbCCZqvcfHcIYFB9cxgqPvv4Cu46jVzSICy74p9l57ci\n mebAaSl72uVg==", "\n WzMZMe0yajDNPAA28i931qufqVM1UniE2DMi8tfUCmdkQ7+zcAWU783XOFm6CpnnPd3/a6Rhbp\n bBZKFbcltChQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,9953\"; a=\"194519699\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"194519699\"", "E=Sophos;i=\"5.82,220,1613462400\"; d=\"scan'208\";a=\"424406493\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Tue, 13 Apr 2021 15:14:37 -0500", "Message-Id": "<1618344896-2090-8-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20210316221857.2254-2-timothy.mcdaniel@intel.com>\n <1618344896-2090-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 07/26] event/dlb2: add V2.5 create ldb queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Updated low level hardware functions to add DLB 2.5 support\nfor creating load balanced queues.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/pf/base/dlb2_resource.c | 397 ------------------\n .../event/dlb2/pf/base/dlb2_resource_new.c | 391 +++++++++++++++++\n 2 files changed, 391 insertions(+), 397 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 041aeaeee..f8b85bc57 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -1149,403 +1149,6 @@ unsigned int dlb2_finish_map_qid_procedures(struct dlb2_hw *hw)\n \treturn num;\n }\n \n-\n-static void dlb2_configure_ldb_queue(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_hw_domain *domain,\n-\t\t\t\t struct dlb2_ldb_queue *queue,\n-\t\t\t\t struct dlb2_create_ldb_queue_args *args,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tunion dlb2_sys_vf_ldb_vqid_v r0 = { {0} };\n-\tunion dlb2_sys_vf_ldb_vqid2qid r1 = { {0} };\n-\tunion dlb2_sys_ldb_qid2vqid r2 = { {0} };\n-\tunion dlb2_sys_ldb_vasqid_v r3 = { {0} };\n-\tunion dlb2_lsp_qid_ldb_infl_lim r4 = { {0} };\n-\tunion dlb2_lsp_qid_aqed_active_lim r5 = { {0} };\n-\tunion dlb2_aqed_pipe_qid_hid_width r6 = { {0} };\n-\tunion dlb2_sys_ldb_qid_its r7 = { {0} };\n-\tunion dlb2_lsp_qid_atm_depth_thrsh r8 = { {0} };\n-\tunion dlb2_lsp_qid_naldb_depth_thrsh r9 = { {0} };\n-\tunion dlb2_aqed_pipe_qid_fid_lim r10 = { {0} };\n-\tunion dlb2_chp_ord_qid_sn_map r11 = { {0} };\n-\tunion dlb2_sys_ldb_qid_cfg_v r12 = { {0} };\n-\tunion dlb2_sys_ldb_qid_v r13 = { {0} };\n-\n-\tstruct dlb2_sn_group *sn_group;\n-\tunsigned int offs;\n-\n-\t/* QID write permissions are turned on when the domain is started */\n-\tr3.field.vasqid_v = 0;\n-\n-\toffs = domain->id.phys_id * DLB2_MAX_NUM_LDB_QUEUES +\n-\t\tqueue->id.phys_id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_VASQID_V(offs), r3.val);\n-\n-\t/*\n-\t * Unordered QIDs get 4K inflights, ordered get as many as the number\n-\t * of sequence numbers.\n-\t */\n-\tr4.field.limit = args->num_qid_inflights;\n-\n-\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(queue->id.phys_id), r4.val);\n-\n-\tr5.field.limit = queue->aqed_limit;\n-\n-\tif (r5.field.limit > DLB2_MAX_NUM_AQED_ENTRIES)\n-\t\tr5.field.limit = DLB2_MAX_NUM_AQED_ENTRIES;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_LSP_QID_AQED_ACTIVE_LIM(queue->id.phys_id),\n-\t\t r5.val);\n-\n-\tswitch (args->lock_id_comp_level) {\n-\tcase 64:\n-\t\tr6.field.compress_code = 1;\n-\t\tbreak;\n-\tcase 128:\n-\t\tr6.field.compress_code = 2;\n-\t\tbreak;\n-\tcase 256:\n-\t\tr6.field.compress_code = 3;\n-\t\tbreak;\n-\tcase 512:\n-\t\tr6.field.compress_code = 4;\n-\t\tbreak;\n-\tcase 1024:\n-\t\tr6.field.compress_code = 5;\n-\t\tbreak;\n-\tcase 2048:\n-\t\tr6.field.compress_code = 6;\n-\t\tbreak;\n-\tcase 4096:\n-\t\tr6.field.compress_code = 7;\n-\t\tbreak;\n-\tcase 0:\n-\tcase 65536:\n-\t\tr6.field.compress_code = 0;\n-\t}\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_AQED_PIPE_QID_HID_WIDTH(queue->id.phys_id),\n-\t\t r6.val);\n-\n-\t/* Don't timestamp QEs that pass through this queue */\n-\tr7.field.qid_its = 0;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_SYS_LDB_QID_ITS(queue->id.phys_id),\n-\t\t r7.val);\n-\n-\tr8.field.thresh = args->depth_threshold;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_LSP_QID_ATM_DEPTH_THRSH(queue->id.phys_id),\n-\t\t r8.val);\n-\n-\tr9.field.thresh = args->depth_threshold;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_LSP_QID_NALDB_DEPTH_THRSH(queue->id.phys_id),\n-\t\t r9.val);\n-\n-\t/*\n-\t * This register limits the number of inflight flows a queue can have\n-\t * at one time. It has an upper bound of 2048, but can be\n-\t * over-subscribed. 512 is chosen so that a single queue doesn't use\n-\t * the entire atomic storage, but can use a substantial portion if\n-\t * needed.\n-\t */\n-\tr10.field.qid_fid_limit = 512;\n-\n-\tDLB2_CSR_WR(hw,\n-\t\t DLB2_AQED_PIPE_QID_FID_LIM(queue->id.phys_id),\n-\t\t r10.val);\n-\n-\t/* Configure SNs */\n-\tsn_group = &hw->rsrcs.sn_groups[queue->sn_group];\n-\tr11.field.mode = sn_group->mode;\n-\tr11.field.slot = queue->sn_slot;\n-\tr11.field.grp = sn_group->id;\n-\n-\tDLB2_CSR_WR(hw, DLB2_CHP_ORD_QID_SN_MAP(queue->id.phys_id), r11.val);\n-\n-\tr12.field.sn_cfg_v = (args->num_sequence_numbers != 0);\n-\tr12.field.fid_cfg_v = (args->num_atomic_inflights != 0);\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_CFG_V(queue->id.phys_id), r12.val);\n-\n-\tif (vdev_req) {\n-\t\toffs = vdev_id * DLB2_MAX_NUM_LDB_QUEUES + queue->id.virt_id;\n-\n-\t\tr0.field.vqid_v = 1;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID_V(offs), r0.val);\n-\n-\t\tr1.field.qid = queue->id.phys_id;\n-\n-\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID2QID(offs), r1.val);\n-\n-\t\tr2.field.vqid = queue->id.virt_id;\n-\n-\t\tDLB2_CSR_WR(hw,\n-\t\t\t DLB2_SYS_LDB_QID2VQID(queue->id.phys_id),\n-\t\t\t r2.val);\n-\t}\n-\n-\tr13.field.qid_v = 1;\n-\n-\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_V(queue->id.phys_id), r13.val);\n-}\n-\n-static int\n-dlb2_ldb_queue_attach_to_sn_group(struct dlb2_hw *hw,\n-\t\t\t\t struct dlb2_ldb_queue *queue,\n-\t\t\t\t struct dlb2_create_ldb_queue_args *args)\n-{\n-\tint slot = -1;\n-\tint i;\n-\n-\tqueue->sn_cfg_valid = false;\n-\n-\tif (args->num_sequence_numbers == 0)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n-\t\tstruct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];\n-\n-\t\tif (group->sequence_numbers_per_queue ==\n-\t\t args->num_sequence_numbers &&\n-\t\t !dlb2_sn_group_full(group)) {\n-\t\t\tslot = dlb2_sn_group_alloc_slot(group);\n-\t\t\tif (slot >= 0)\n-\t\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tif (slot == -1) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: no sequence number slots available\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tqueue->sn_cfg_valid = true;\n-\tqueue->sn_group = i;\n-\tqueue->sn_slot = slot;\n-\treturn 0;\n-}\n-\n-static int\n-dlb2_ldb_queue_attach_resources(struct dlb2_hw *hw,\n-\t\t\t\tstruct dlb2_hw_domain *domain,\n-\t\t\t\tstruct dlb2_ldb_queue *queue,\n-\t\t\t\tstruct dlb2_create_ldb_queue_args *args)\n-{\n-\tint ret;\n-\n-\tret = dlb2_ldb_queue_attach_to_sn_group(hw, queue, args);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Attach QID inflights */\n-\tqueue->num_qid_inflights = args->num_qid_inflights;\n-\n-\t/* Attach atomic inflights */\n-\tqueue->aqed_limit = args->num_atomic_inflights;\n-\n-\tdomain->num_avail_aqed_entries -= args->num_atomic_inflights;\n-\tdomain->num_used_aqed_entries += args->num_atomic_inflights;\n-\n-\treturn 0;\n-}\n-\n-static int\n-dlb2_verify_create_ldb_queue_args(struct dlb2_hw *hw,\n-\t\t\t\t u32 domain_id,\n-\t\t\t\t struct dlb2_create_ldb_queue_args *args,\n-\t\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t\t bool vdev_req,\n-\t\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\tint i;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\n-\tif (domain == NULL) {\n-\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!domain->configured) {\n-\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (domain->started) {\n-\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (dlb2_list_empty(&domain->avail_ldb_queues)) {\n-\t\tresp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->num_sequence_numbers) {\n-\t\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n-\t\t\tstruct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];\n-\n-\t\t\tif (group->sequence_numbers_per_queue ==\n-\t\t\t args->num_sequence_numbers &&\n-\t\t\t !dlb2_sn_group_full(group))\n-\t\t\t\tbreak;\n-\t\t}\n-\n-\t\tif (i == DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS) {\n-\t\t\tresp->status = DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tif (args->num_qid_inflights > 4096) {\n-\t\tresp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Inflights must be <= number of sequence numbers if ordered */\n-\tif (args->num_sequence_numbers != 0 &&\n-\t args->num_qid_inflights > args->num_sequence_numbers) {\n-\t\tresp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (domain->num_avail_aqed_entries < args->num_atomic_inflights) {\n-\t\tresp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (args->num_atomic_inflights &&\n-\t args->lock_id_comp_level != 0 &&\n-\t args->lock_id_comp_level != 64 &&\n-\t args->lock_id_comp_level != 128 &&\n-\t args->lock_id_comp_level != 256 &&\n-\t args->lock_id_comp_level != 512 &&\n-\t args->lock_id_comp_level != 1024 &&\n-\t args->lock_id_comp_level != 2048 &&\n-\t args->lock_id_comp_level != 4096 &&\n-\t args->lock_id_comp_level != 65536) {\n-\t\tresp->status = DLB2_ST_INVALID_LOCK_ID_COMP_LEVEL;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void\n-dlb2_log_create_ldb_queue_args(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t struct dlb2_create_ldb_queue_args *args,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tDLB2_HW_DBG(hw, \"DLB2 create load-balanced queue arguments:\\n\");\n-\tif (vdev_req)\n-\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n-\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n-\t\t domain_id);\n-\tDLB2_HW_DBG(hw, \"\\tNumber of sequence numbers: %d\\n\",\n-\t\t args->num_sequence_numbers);\n-\tDLB2_HW_DBG(hw, \"\\tNumber of QID inflights: %d\\n\",\n-\t\t args->num_qid_inflights);\n-\tDLB2_HW_DBG(hw, \"\\tNumber of ATM inflights: %d\\n\",\n-\t\t args->num_atomic_inflights);\n-}\n-\n-/**\n- * dlb2_hw_create_ldb_queue() - Allocate and initialize a DLB LDB queue.\n- * @hw:\tContains the current state of the DLB2 hardware.\n- * @domain_id: Domain ID\n- * @args: User-provided arguments.\n- * @resp: Response to user.\n- * @vdev_req: Request came from a virtual device.\n- * @vdev_id: If vdev_req is true, this contains the virtual device's ID.\n- *\n- * Return: returns < 0 on error, 0 otherwise. If the driver is unable to\n- * satisfy a request, resp->status will be set accordingly.\n- */\n-int dlb2_hw_create_ldb_queue(struct dlb2_hw *hw,\n-\t\t\t u32 domain_id,\n-\t\t\t struct dlb2_create_ldb_queue_args *args,\n-\t\t\t struct dlb2_cmd_response *resp,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n-{\n-\tstruct dlb2_hw_domain *domain;\n-\tstruct dlb2_ldb_queue *queue;\n-\tint ret;\n-\n-\tdlb2_log_create_ldb_queue_args(hw, domain_id, args, vdev_req, vdev_id);\n-\n-\t/*\n-\t * Verify that hardware resources are available before attempting to\n-\t * satisfy the request. This simplifies the error unwinding code.\n-\t */\n-\tret = dlb2_verify_create_ldb_queue_args(hw,\n-\t\t\t\t\t\tdomain_id,\n-\t\t\t\t\t\targs,\n-\t\t\t\t\t\tresp,\n-\t\t\t\t\t\tvdev_req,\n-\t\t\t\t\t\tvdev_id);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n-\tif (domain == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: domain not found\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tqueue = DLB2_DOM_LIST_HEAD(domain->avail_ldb_queues, typeof(*queue));\n-\tif (queue == NULL) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: no available ldb queues\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tret = dlb2_ldb_queue_attach_resources(hw, domain, queue, args);\n-\tif (ret < 0) {\n-\t\tDLB2_HW_ERR(hw,\n-\t\t\t \"[%s():%d] Internal error: failed to attach the ldb queue resources\\n\",\n-\t\t\t __func__, __LINE__);\n-\t\treturn ret;\n-\t}\n-\n-\tdlb2_configure_ldb_queue(hw, domain, queue, args, vdev_req, vdev_id);\n-\n-\tqueue->num_mappings = 0;\n-\n-\tqueue->configured = true;\n-\n-\t/*\n-\t * Configuration succeeded, so move the resource from the 'avail' to\n-\t * the 'used' list.\n-\t */\n-\tdlb2_list_del(&domain->avail_ldb_queues, &queue->domain_list);\n-\n-\tdlb2_list_add(&domain->used_ldb_queues, &queue->domain_list);\n-\n-\tresp->status = 0;\n-\tresp->id = (vdev_req) ? queue->id.virt_id : queue->id.phys_id;\n-\n-\treturn 0;\n-}\n-\n int dlb2_get_group_sequence_numbers(struct dlb2_hw *hw, unsigned int group_id)\n {\n \tif (group_id >= DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS)\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource_new.c b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\nindex 641812412..b52d2becd 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource_new.c\n@@ -3581,3 +3581,394 @@ int dlb2_reset_domain(struct dlb2_hw *hw,\n \t/* Hardware reset complete. Reset the domain's software state */\n \treturn dlb2_domain_reset_software_state(hw, domain);\n }\n+\n+static void\n+dlb2_log_create_ldb_queue_args(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_create_ldb_queue_args *args,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 create load-balanced queue arguments:\\n\");\n+\tif (vdev_req)\n+\t\tDLB2_HW_DBG(hw, \"(Request from vdev %d)\\n\", vdev_id);\n+\tDLB2_HW_DBG(hw, \"\\tDomain ID: %d\\n\",\n+\t\t domain_id);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of sequence numbers: %d\\n\",\n+\t\t args->num_sequence_numbers);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of QID inflights: %d\\n\",\n+\t\t args->num_qid_inflights);\n+\tDLB2_HW_DBG(hw, \"\\tNumber of ATM inflights: %d\\n\",\n+\t\t args->num_atomic_inflights);\n+}\n+\n+static int\n+dlb2_ldb_queue_attach_to_sn_group(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t struct dlb2_create_ldb_queue_args *args)\n+{\n+\tint slot = -1;\n+\tint i;\n+\n+\tqueue->sn_cfg_valid = false;\n+\n+\tif (args->num_sequence_numbers == 0)\n+\t\treturn 0;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\tstruct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];\n+\n+\t\tif (group->sequence_numbers_per_queue ==\n+\t\t args->num_sequence_numbers &&\n+\t\t !dlb2_sn_group_full(group)) {\n+\t\t\tslot = dlb2_sn_group_alloc_slot(group);\n+\t\t\tif (slot >= 0)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (slot == -1) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: no sequence number slots available\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tqueue->sn_cfg_valid = true;\n+\tqueue->sn_group = i;\n+\tqueue->sn_slot = slot;\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_verify_create_ldb_queue_args(struct dlb2_hw *hw,\n+\t\t\t\t u32 domain_id,\n+\t\t\t\t struct dlb2_create_ldb_queue_args *args,\n+\t\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id,\n+\t\t\t\t struct dlb2_hw_domain **out_domain,\n+\t\t\t\t struct dlb2_ldb_queue **out_queue)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_queue *queue;\n+\tint i;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n+\n+\tif (!domain) {\n+\t\tresp->status = DLB2_ST_INVALID_DOMAIN_ID;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!domain->configured) {\n+\t\tresp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (domain->started) {\n+\t\tresp->status = DLB2_ST_DOMAIN_STARTED;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqueue = DLB2_DOM_LIST_HEAD(domain->avail_ldb_queues, typeof(*queue));\n+\tif (!queue) {\n+\t\tresp->status = DLB2_ST_LDB_QUEUES_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->num_sequence_numbers) {\n+\t\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\t\tstruct dlb2_sn_group *group = &hw->rsrcs.sn_groups[i];\n+\n+\t\t\tif (group->sequence_numbers_per_queue ==\n+\t\t\t args->num_sequence_numbers &&\n+\t\t\t !dlb2_sn_group_full(group))\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (i == DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS) {\n+\t\t\tresp->status = DLB2_ST_SEQUENCE_NUMBERS_UNAVAILABLE;\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (args->num_qid_inflights > 4096) {\n+\t\tresp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Inflights must be <= number of sequence numbers if ordered */\n+\tif (args->num_sequence_numbers != 0 &&\n+\t args->num_qid_inflights > args->num_sequence_numbers) {\n+\t\tresp->status = DLB2_ST_INVALID_QID_INFLIGHT_ALLOCATION;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (domain->num_avail_aqed_entries < args->num_atomic_inflights) {\n+\t\tresp->status = DLB2_ST_ATOMIC_INFLIGHTS_UNAVAILABLE;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (args->num_atomic_inflights &&\n+\t args->lock_id_comp_level != 0 &&\n+\t args->lock_id_comp_level != 64 &&\n+\t args->lock_id_comp_level != 128 &&\n+\t args->lock_id_comp_level != 256 &&\n+\t args->lock_id_comp_level != 512 &&\n+\t args->lock_id_comp_level != 1024 &&\n+\t args->lock_id_comp_level != 2048 &&\n+\t args->lock_id_comp_level != 4096 &&\n+\t args->lock_id_comp_level != 65536) {\n+\t\tresp->status = DLB2_ST_INVALID_LOCK_ID_COMP_LEVEL;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t*out_domain = domain;\n+\t*out_queue = queue;\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_ldb_queue_attach_resources(struct dlb2_hw *hw,\n+\t\t\t\tstruct dlb2_hw_domain *domain,\n+\t\t\t\tstruct dlb2_ldb_queue *queue,\n+\t\t\t\tstruct dlb2_create_ldb_queue_args *args)\n+{\n+\tint ret;\n+\tret = dlb2_ldb_queue_attach_to_sn_group(hw, queue, args);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Attach QID inflights */\n+\tqueue->num_qid_inflights = args->num_qid_inflights;\n+\n+\t/* Attach atomic inflights */\n+\tqueue->aqed_limit = args->num_atomic_inflights;\n+\n+\tdomain->num_avail_aqed_entries -= args->num_atomic_inflights;\n+\tdomain->num_used_aqed_entries += args->num_atomic_inflights;\n+\n+\treturn 0;\n+}\n+\n+static void dlb2_configure_ldb_queue(struct dlb2_hw *hw,\n+\t\t\t\t struct dlb2_hw_domain *domain,\n+\t\t\t\t struct dlb2_ldb_queue *queue,\n+\t\t\t\t struct dlb2_create_ldb_queue_args *args,\n+\t\t\t\t bool vdev_req,\n+\t\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_sn_group *sn_group;\n+\tunsigned int offs;\n+\tu32 reg = 0;\n+\tu32 alimit;\n+\n+\t/* QID write permissions are turned on when the domain is started */\n+\toffs = domain->id.phys_id * DLB2_MAX_NUM_LDB_QUEUES + queue->id.phys_id;\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_VASQID_V(offs), reg);\n+\n+\t/*\n+\t * Unordered QIDs get 4K inflights, ordered get as many as the number\n+\t * of sequence numbers.\n+\t */\n+\tDLB2_BITS_SET(reg, args->num_qid_inflights,\n+\t\t DLB2_LSP_QID_LDB_INFL_LIM_LIMIT);\n+\tDLB2_CSR_WR(hw, DLB2_LSP_QID_LDB_INFL_LIM(hw->ver,\n+\t\t\t\t\t\t queue->id.phys_id), reg);\n+\n+\talimit = queue->aqed_limit;\n+\n+\tif (alimit > DLB2_MAX_NUM_AQED_ENTRIES)\n+\t\talimit = DLB2_MAX_NUM_AQED_ENTRIES;\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, alimit, DLB2_LSP_QID_AQED_ACTIVE_LIM_LIMIT);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID_AQED_ACTIVE_LIM(hw->ver,\n+\t\t\t\t\t\t queue->id.phys_id), reg);\n+\n+\treg = 0;\n+\tswitch (args->lock_id_comp_level) {\n+\tcase 64:\n+\t\tDLB2_BITS_SET(reg, 1, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 128:\n+\t\tDLB2_BITS_SET(reg, 2, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 256:\n+\t\tDLB2_BITS_SET(reg, 3, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 512:\n+\t\tDLB2_BITS_SET(reg, 4, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 1024:\n+\t\tDLB2_BITS_SET(reg, 5, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 2048:\n+\t\tDLB2_BITS_SET(reg, 6, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tcase 4096:\n+\t\tDLB2_BITS_SET(reg, 7, DLB2_AQED_QID_HID_WIDTH_COMPRESS_CODE);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* No compression by default */\n+\t\tbreak;\n+\t}\n+\n+\tDLB2_CSR_WR(hw, DLB2_AQED_QID_HID_WIDTH(queue->id.phys_id), reg);\n+\n+\treg = 0;\n+\t/* Don't timestamp QEs that pass through this queue */\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_ITS(queue->id.phys_id), reg);\n+\n+\tDLB2_BITS_SET(reg, args->depth_threshold,\n+\t\t DLB2_LSP_QID_ATM_DEPTH_THRSH_THRESH);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID_ATM_DEPTH_THRSH(hw->ver,\n+\t\t\t\t\t\t queue->id.phys_id), reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, args->depth_threshold,\n+\t\t DLB2_LSP_QID_NALDB_DEPTH_THRSH_THRESH);\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_LSP_QID_NALDB_DEPTH_THRSH(hw->ver, queue->id.phys_id),\n+\t\t reg);\n+\n+\t/*\n+\t * This register limits the number of inflight flows a queue can have\n+\t * at one time. It has an upper bound of 2048, but can be\n+\t * over-subscribed. 512 is chosen so that a single queue does not use\n+\t * the entire atomic storage, but can use a substantial portion if\n+\t * needed.\n+\t */\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, 512, DLB2_AQED_QID_FID_LIM_QID_FID_LIMIT);\n+\tDLB2_CSR_WR(hw, DLB2_AQED_QID_FID_LIM(queue->id.phys_id), reg);\n+\n+\t/* Configure SNs */\n+\treg = 0;\n+\tsn_group = &hw->rsrcs.sn_groups[queue->sn_group];\n+\tDLB2_BITS_SET(reg, sn_group->mode, DLB2_CHP_ORD_QID_SN_MAP_MODE);\n+\tDLB2_BITS_SET(reg, queue->sn_slot, DLB2_CHP_ORD_QID_SN_MAP_SLOT);\n+\tDLB2_BITS_SET(reg, sn_group->id, DLB2_CHP_ORD_QID_SN_MAP_GRP);\n+\n+\tDLB2_CSR_WR(hw,\n+\t\t DLB2_CHP_ORD_QID_SN_MAP(hw->ver, queue->id.phys_id), reg);\n+\n+\treg = 0;\n+\tDLB2_BITS_SET(reg, (args->num_sequence_numbers != 0),\n+\t\t DLB2_SYS_LDB_QID_CFG_V_SN_CFG_V);\n+\tDLB2_BITS_SET(reg, (args->num_atomic_inflights != 0),\n+\t\t DLB2_SYS_LDB_QID_CFG_V_FID_CFG_V);\n+\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_CFG_V(queue->id.phys_id), reg);\n+\n+\tif (vdev_req) {\n+\t\toffs = vdev_id * DLB2_MAX_NUM_LDB_QUEUES + queue->id.virt_id;\n+\n+\t\treg = 0;\n+\t\tDLB2_BIT_SET(reg, DLB2_SYS_VF_LDB_VQID_V_VQID_V);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID_V(offs), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, queue->id.phys_id,\n+\t\t\t DLB2_SYS_VF_LDB_VQID2QID_QID);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VQID2QID(offs), reg);\n+\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, queue->id.virt_id,\n+\t\t\t DLB2_SYS_LDB_QID2VQID_VQID);\n+\t\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID2VQID(queue->id.phys_id), reg);\n+\t}\n+\n+\treg = 0;\n+\tDLB2_BIT_SET(reg, DLB2_SYS_LDB_QID_V_QID_V);\n+\tDLB2_CSR_WR(hw, DLB2_SYS_LDB_QID_V(queue->id.phys_id), reg);\n+}\n+\n+/**\n+ * dlb2_hw_create_ldb_queue() - create a load-balanced queue\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @domain_id: domain ID.\n+ * @args: queue creation arguments.\n+ * @resp: response structure.\n+ * @vdev_req: indicates whether this request came from a vdev.\n+ * @vdev_id: If vdev_req is true, this contains the vdev's ID.\n+ *\n+ * This function creates a load-balanced queue.\n+ *\n+ * A vdev can be either an SR-IOV virtual function or a Scalable IOV virtual\n+ * device.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * resp->id contains a virtual ID if vdev_req is true.\n+ *\n+ * Errors:\n+ * EINVAL - A requested resource is unavailable, the domain is not configured,\n+ *\t the domain has already been started, or the requested queue name is\n+ *\t already in use.\n+ * EFAULT - Internal error (resp->status not set).\n+ */\n+int dlb2_hw_create_ldb_queue(struct dlb2_hw *hw,\n+\t\t\t u32 domain_id,\n+\t\t\t struct dlb2_create_ldb_queue_args *args,\n+\t\t\t struct dlb2_cmd_response *resp,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_queue *queue;\n+\tint ret;\n+\n+\tdlb2_log_create_ldb_queue_args(hw, domain_id, args, vdev_req, vdev_id);\n+\n+\t/*\n+\t * Verify that hardware resources are available before attempting to\n+\t * satisfy the request. This simplifies the error unwinding code.\n+\t */\n+\tret = dlb2_verify_create_ldb_queue_args(hw,\n+\t\t\t\t\t\tdomain_id,\n+\t\t\t\t\t\targs,\n+\t\t\t\t\t\tresp,\n+\t\t\t\t\t\tvdev_req,\n+\t\t\t\t\t\tvdev_id,\n+\t\t\t\t\t\t&domain,\n+\t\t\t\t\t\t&queue);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = dlb2_ldb_queue_attach_resources(hw, domain, queue, args);\n+\n+\tif (ret) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: failed to attach the ldb queue resources\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn ret;\n+\t}\n+\n+\tdlb2_configure_ldb_queue(hw, domain, queue, args, vdev_req, vdev_id);\n+\n+\tqueue->num_mappings = 0;\n+\n+\tqueue->configured = true;\n+\n+\t/*\n+\t * Configuration succeeded, so move the resource from the 'avail' to\n+\t * the 'used' list.\n+\t */\n+\tdlb2_list_del(&domain->avail_ldb_queues, &queue->domain_list);\n+\n+\tdlb2_list_add(&domain->used_ldb_queues, &queue->domain_list);\n+\n+\tresp->status = 0;\n+\tresp->id = (vdev_req) ? queue->id.virt_id : queue->id.phys_id;\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v3", "07/26" ] }