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GET /api/patches/90404/?format=api
{ "id": 90404, "url": "https://patches.dpdk.org/api/patches/90404/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-32-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-32-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-32-ndabilpuram@marvell.com", "date": "2021-04-01T12:37:56", "name": "[v3,31/52] common/cnxk: add nix LSO support and misc utils", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "e02d6934fc64a3e148cdfa254d58870f3b0e2e57", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-32-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "https://patches.dpdk.org/api/series/16059/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16059/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90404/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90404/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6D4D0A0548;\n\tThu, 1 Apr 2021 14:43:21 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 248BB14126A;\n\tThu, 1 Apr 2021 14:40:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 8F6D2141260\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:40:12 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CRJvS021887 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:40:12 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje3r-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:40:11 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:40:09 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:40:09 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id F330B3F7070;\n Thu, 1 Apr 2021 05:40:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=g9c2isbLt1D7Bbh6j8XYICS+NvWz4SwfpiCfD54GmKk=;\n b=eLSnjOHCcIo9LIecWwg1ELMqpyLwutLtWziE/NYJstq9U4qNH8aGvg14E9109Ljq3U3j\n 39JsUVvqZM3J6uMksIQNb/3C887zqHAPhSlAnerLeyJUA+f9minotdJYLT12PrRdVnCU\n JLJvarkzx608xUEPlclanDEwUAJ2N4iBbvF/sZMJ8Mnf/a+U3p7b5p3f9TXTErpe6pxZ\n k0BiLMYuxnPZPJb5Rzw0ewB4ezo5hVVv18bPDYJO4ifFbiF2ALJKVwYqLDYhbZ6WVowE\n EgMxXn4+OA6glQsWXtcTBwtrrZnNLXzfO2/5uale0A9ejIeZBoMhcWRGDQPBVMVtW9Vo LQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 18:07:56 +0530", "Message-ID": "<20210401123817.14348-32-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Ps16kWqXhXmR_44es-BAMi0Eb6uRgmBv", "X-Proofpoint-ORIG-GUID": "Ps16kWqXhXmR_44es-BAMi0Eb6uRgmBv", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 31/52] common/cnxk: add nix LSO support and\n misc utils", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nAdd support to create LSO formats for TCP segmentation offload\nfor IPv4/IPv6, tunnel and non-tunnel protocols. Tunnel protocol\nsupport is for GRE and UDP based tunnel protocols.\n\nThis patch also adds other helper API to retrieve eeprom info\nand configure Rx for different switch headers.\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 28 +++\n drivers/common/cnxk/roc_nix_debug.c | 16 ++\n drivers/common/cnxk/roc_nix_ops.c | 438 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_priv.h | 2 +\n drivers/common/cnxk/version.map | 5 +\n 6 files changed, 490 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_ops.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 33eeb8c..d8514b3 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -22,6 +22,7 @@ sources = files('roc_dev.c',\n \t\t'roc_nix_mac.c',\n \t\t'roc_nix_mcast.c',\n \t\t'roc_nix_npc.c',\n+\t\t'roc_nix_ops.c',\n \t\t'roc_nix_ptp.c',\n \t\t'roc_nix_queue.c',\n \t\t'roc_nix_rss.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 2158f8c..ce8c252 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -59,6 +59,12 @@ struct roc_nix_fc_cfg {\n \t};\n };\n \n+struct roc_nix_eeprom_info {\n+#define ROC_NIX_EEPROM_SIZE 256\n+\tuint16_t sff_id;\n+\tuint8_t buf[ROC_NIX_EEPROM_SIZE];\n+};\n+\n /* Range to adjust PTP frequency. Valid range is\n * (-ROC_NIX_PTP_FREQ_ADJUST, ROC_NIX_PTP_FREQ_ADJUST)\n */\n@@ -246,6 +252,14 @@ struct roc_nix {\n \tuint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;\n } __plt_cache_aligned;\n \n+enum roc_nix_lso_tun_type {\n+\tROC_NIX_LSO_TUN_V4V4,\n+\tROC_NIX_LSO_TUN_V4V6,\n+\tROC_NIX_LSO_TUN_V6V4,\n+\tROC_NIX_LSO_TUN_V6V6,\n+\tROC_NIX_LSO_TUN_MAX,\n+};\n+\n /* Dev */\n int __roc_api roc_nix_dev_init(struct roc_nix *roc_nix);\n int __roc_api roc_nix_dev_fini(struct roc_nix *roc_nix);\n@@ -315,6 +329,20 @@ int __roc_api roc_nix_mac_link_cb_register(struct roc_nix *roc_nix,\n \t\t\t\t\t link_status_t link_update);\n void __roc_api roc_nix_mac_link_cb_unregister(struct roc_nix *roc_nix);\n \n+/* Ops */\n+int __roc_api roc_nix_switch_hdr_set(struct roc_nix *roc_nix,\n+\t\t\t\t uint64_t switch_header_type);\n+int __roc_api roc_nix_lso_fmt_setup(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_lso_fmt_get(struct roc_nix *roc_nix,\n+\t\t\t\t uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],\n+\t\t\t\t uint8_t tun[ROC_NIX_LSO_TUN_MAX]);\n+int __roc_api roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,\n+\t\t\t\t\t struct nix_lso_format *fields,\n+\t\t\t\t\t uint16_t nb_fields);\n+\n+int __roc_api roc_nix_eeprom_info_get(struct roc_nix *roc_nix,\n+\t\t\t\t struct roc_nix_eeprom_info *info);\n+\n /* Flow control */\n int __roc_api roc_nix_fc_config_set(struct roc_nix *roc_nix,\n \t\t\t\t struct roc_nix_fc_cfg *fc_cfg);\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 00712d5..a0cf98e 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -786,6 +786,22 @@ roc_nix_dump(struct roc_nix *roc_nix)\n \tnix_dump(\" \\tnb_tx_queues = %d\", nix->nb_tx_queues);\n \tnix_dump(\" \\tlso_tsov6_idx = %d\", nix->lso_tsov6_idx);\n \tnix_dump(\" \\tlso_tsov4_idx = %d\", nix->lso_tsov4_idx);\n+\tnix_dump(\" \\tlso_udp_tun_v4v4 = %d\",\n+\t\t nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]);\n+\tnix_dump(\" \\tlso_udp_tun_v4v6 = %d\",\n+\t\t nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]);\n+\tnix_dump(\" \\tlso_udp_tun_v6v4 = %d\",\n+\t\t nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]);\n+\tnix_dump(\" \\tlso_udp_tun_v6v6 = %d\",\n+\t\t nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]);\n+\tnix_dump(\" \\tlso_tun_v4v4 = %d\",\n+\t\t nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]);\n+\tnix_dump(\" \\tlso_tun_v4v6 = %d\",\n+\t\t nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]);\n+\tnix_dump(\" \\tlso_tun_v6v4 = %d\",\n+\t\t nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]);\n+\tnix_dump(\" \\tlso_tun_v6v6 = %d\",\n+\t\t nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]);\n \tnix_dump(\" \\tlf_rx_stats = %d\", nix->lf_rx_stats);\n \tnix_dump(\" \\tlf_tx_stats = %d\", nix->lf_tx_stats);\n \tnix_dump(\" \\trx_chan_cnt = %d\", nix->rx_chan_cnt);\ndiff --git a/drivers/common/cnxk/roc_nix_ops.c b/drivers/common/cnxk/roc_nix_ops.c\nnew file mode 100644\nindex 0000000..eeb85a5\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_ops.c\n@@ -0,0 +1,438 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static inline struct mbox *\n+get_mbox(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev->mbox;\n+}\n+\n+static void\n+nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)\n+{\n+\t__io struct nix_lso_format *field;\n+\n+\t/* Format works only with TCP packet marked by OL3/OL4 */\n+\tfield = (__io struct nix_lso_format *)&req->fields[0];\n+\treq->field_mask = NIX_LSO_FIELD_MASK;\n+\t/* Outer IPv4/IPv6 */\n+\tfield->layer = NIX_TXLAYER_OL3;\n+\tfield->offset = v4 ? 2 : 4;\n+\tfield->sizem1 = 1; /* 2B */\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\tif (v4) {\n+\t\t/* IPID field */\n+\t\tfield->layer = NIX_TXLAYER_OL3;\n+\t\tfield->offset = 4;\n+\t\tfield->sizem1 = 1;\n+\t\t/* Incremented linearly per segment */\n+\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n+\t\tfield++;\n+\t}\n+\n+\t/* TCP sequence number update */\n+\tfield->layer = NIX_TXLAYER_OL4;\n+\tfield->offset = 4;\n+\tfield->sizem1 = 3; /* 4 bytes */\n+\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n+\tfield++;\n+\t/* TCP flags field */\n+\tfield->layer = NIX_TXLAYER_OL4;\n+\tfield->offset = 12;\n+\tfield->sizem1 = 1;\n+\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n+\tfield++;\n+}\n+\n+static void\n+nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req, bool outer_v4,\n+\t\t bool inner_v4)\n+{\n+\t__io struct nix_lso_format *field;\n+\n+\tfield = (__io struct nix_lso_format *)&req->fields[0];\n+\treq->field_mask = NIX_LSO_FIELD_MASK;\n+\t/* Outer IPv4/IPv6 len */\n+\tfield->layer = NIX_TXLAYER_OL3;\n+\tfield->offset = outer_v4 ? 2 : 4;\n+\tfield->sizem1 = 1; /* 2B */\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\tif (outer_v4) {\n+\t\t/* IPID */\n+\t\tfield->layer = NIX_TXLAYER_OL3;\n+\t\tfield->offset = 4;\n+\t\tfield->sizem1 = 1;\n+\t\t/* Incremented linearly per segment */\n+\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n+\t\tfield++;\n+\t}\n+\n+\t/* Outer UDP length */\n+\tfield->layer = NIX_TXLAYER_OL4;\n+\tfield->offset = 4;\n+\tfield->sizem1 = 1;\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\n+\t/* Inner IPv4/IPv6 */\n+\tfield->layer = NIX_TXLAYER_IL3;\n+\tfield->offset = inner_v4 ? 2 : 4;\n+\tfield->sizem1 = 1; /* 2B */\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\tif (inner_v4) {\n+\t\t/* IPID field */\n+\t\tfield->layer = NIX_TXLAYER_IL3;\n+\t\tfield->offset = 4;\n+\t\tfield->sizem1 = 1;\n+\t\t/* Incremented linearly per segment */\n+\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n+\t\tfield++;\n+\t}\n+\n+\t/* TCP sequence number update */\n+\tfield->layer = NIX_TXLAYER_IL4;\n+\tfield->offset = 4;\n+\tfield->sizem1 = 3; /* 4 bytes */\n+\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n+\tfield++;\n+\n+\t/* TCP flags field */\n+\tfield->layer = NIX_TXLAYER_IL4;\n+\tfield->offset = 12;\n+\tfield->sizem1 = 1;\n+\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n+\tfield++;\n+}\n+\n+static void\n+nix_lso_tun_tcp(struct nix_lso_format_cfg *req, bool outer_v4, bool inner_v4)\n+{\n+\t__io struct nix_lso_format *field;\n+\n+\tfield = (__io struct nix_lso_format *)&req->fields[0];\n+\treq->field_mask = NIX_LSO_FIELD_MASK;\n+\t/* Outer IPv4/IPv6 len */\n+\tfield->layer = NIX_TXLAYER_OL3;\n+\tfield->offset = outer_v4 ? 2 : 4;\n+\tfield->sizem1 = 1; /* 2B */\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\tif (outer_v4) {\n+\t\t/* IPID */\n+\t\tfield->layer = NIX_TXLAYER_OL3;\n+\t\tfield->offset = 4;\n+\t\tfield->sizem1 = 1;\n+\t\t/* Incremented linearly per segment */\n+\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n+\t\tfield++;\n+\t}\n+\n+\t/* Inner IPv4/IPv6 */\n+\tfield->layer = NIX_TXLAYER_IL3;\n+\tfield->offset = inner_v4 ? 2 : 4;\n+\tfield->sizem1 = 1; /* 2B */\n+\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n+\tfield++;\n+\tif (inner_v4) {\n+\t\t/* IPID field */\n+\t\tfield->layer = NIX_TXLAYER_IL3;\n+\t\tfield->offset = 4;\n+\t\tfield->sizem1 = 1;\n+\t\t/* Incremented linearly per segment */\n+\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n+\t\tfield++;\n+\t}\n+\n+\t/* TCP sequence number update */\n+\tfield->layer = NIX_TXLAYER_IL4;\n+\tfield->offset = 4;\n+\tfield->sizem1 = 3; /* 4 bytes */\n+\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n+\tfield++;\n+\n+\t/* TCP flags field */\n+\tfield->layer = NIX_TXLAYER_IL4;\n+\tfield->offset = 12;\n+\tfield->sizem1 = 1;\n+\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n+\tfield++;\n+}\n+\n+int\n+roc_nix_lso_custom_fmt_setup(struct roc_nix *roc_nix,\n+\t\t\t struct nix_lso_format *fields, uint16_t nb_fields)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_lso_format_cfg_rsp *rsp;\n+\tstruct nix_lso_format_cfg *req;\n+\tint rc = -ENOSPC;\n+\n+\tif (nb_fields > NIX_LSO_FIELD_MAX)\n+\t\treturn -EINVAL;\n+\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\n+\treq->field_mask = NIX_LSO_FIELD_MASK;\n+\tmbox_memcpy(req->fields, fields,\n+\t\t sizeof(struct nix_lso_format) * nb_fields);\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tplt_nix_dbg(\"Setup custom format %u\", rsp->lso_format_idx);\n+\treturn rsp->lso_format_idx;\n+}\n+\n+int\n+roc_nix_lso_fmt_setup(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct nix_lso_format_cfg_rsp *rsp;\n+\tstruct nix_lso_format_cfg *req;\n+\tint rc = -ENOSPC;\n+\n+\t/*\n+\t * IPv4/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\tnix_lso_tcp(req, true);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV4)\n+\t\treturn NIX_ERR_INTERNAL;\n+\n+\tplt_nix_dbg(\"tcpv4 lso fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv6/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_tcp(req, false);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV6)\n+\t\treturn NIX_ERR_INTERNAL;\n+\n+\tplt_nix_dbg(\"tcpv6 lso fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv4/UDP/TUN HDR/IPv4/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_udp_tun_tcp(req, true, true);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"udp tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv4/UDP/TUN HDR/IPv6/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_udp_tun_tcp(req, true, false);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"udp tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv6/UDP/TUN HDR/IPv4/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_udp_tun_tcp(req, false, true);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"udp tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv6/UDP/TUN HDR/IPv6/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_udp_tun_tcp(req, false, false);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"udp tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv4/TUN HDR/IPv4/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_tun_tcp(req, true, true);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv4/TUN HDR/IPv6/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_tun_tcp(req, true, false);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv6/TUN HDR/IPv4/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_tun_tcp(req, false, true);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n+\n+\t/*\n+\t * IPv6/TUN HDR/IPv6/TCP LSO\n+\t */\n+\treq = mbox_alloc_msg_nix_lso_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\tnix_lso_tun_tcp(req, false, false);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tnix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n+\tplt_nix_dbg(\"tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_lso_fmt_get(struct roc_nix *roc_nix,\n+\t\t uint8_t udp_tun[ROC_NIX_LSO_TUN_MAX],\n+\t\t uint8_t tun[ROC_NIX_LSO_TUN_MAX])\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tmemcpy(udp_tun, nix->lso_udp_tun_idx, ROC_NIX_LSO_TUN_MAX);\n+\tmemcpy(tun, nix->lso_tun_idx, ROC_NIX_LSO_TUN_MAX);\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_switch_hdr_set(struct roc_nix *roc_nix, uint64_t switch_header_type)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct npc_set_pkind *req;\n+\tstruct msg_resp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\tif (switch_header_type == 0)\n+\t\tswitch_header_type = ROC_PRIV_FLAGS_DEFAULT;\n+\n+\tif (switch_header_type != ROC_PRIV_FLAGS_DEFAULT &&\n+\t switch_header_type != ROC_PRIV_FLAGS_EDSA &&\n+\t switch_header_type != ROC_PRIV_FLAGS_HIGIG &&\n+\t switch_header_type != ROC_PRIV_FLAGS_LEN_90B &&\n+\t switch_header_type != ROC_PRIV_FLAGS_CUSTOM) {\n+\t\tplt_err(\"switch header type is not supported\");\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\tif (switch_header_type == ROC_PRIV_FLAGS_LEN_90B &&\n+\t !roc_nix_is_sdp(roc_nix)) {\n+\t\tplt_err(\"chlen90b is not supported on non-SDP device\");\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\tif (switch_header_type == ROC_PRIV_FLAGS_HIGIG &&\n+\t roc_nix_is_vf_or_sdp(roc_nix)) {\n+\t\tplt_err(\"higig2 is supported on PF devices only\");\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\treq = mbox_alloc_msg_npc_set_pkind(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->mode = switch_header_type;\n+\treq->dir = PKIND_RX;\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treq = mbox_alloc_msg_npc_set_pkind(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\treq->mode = switch_header_type;\n+\treq->dir = PKIND_TX;\n+\treturn mbox_process_msg(mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_nix_eeprom_info_get(struct roc_nix *roc_nix,\n+\t\t\tstruct roc_nix_eeprom_info *info)\n+{\n+\tstruct mbox *mbox = get_mbox(roc_nix);\n+\tstruct cgx_fw_data *rsp = NULL;\n+\tint rc;\n+\n+\tif (!info) {\n+\t\tplt_err(\"Input buffer is NULL\");\n+\t\treturn NIX_ERR_PARAM;\n+\t}\n+\n+\tmbox_alloc_msg_cgx_get_aux_link_info(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get fw data: %d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tinfo->sff_id = rsp->fwdata.sfp_eeprom.sff_id;\n+\tmbox_memcpy(info->buf, rsp->fwdata.sfp_eeprom.buf, SFP_EEPROM_SIZE);\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 1457696..202bc76 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -45,6 +45,8 @@ struct nix {\n \tuint16_t nb_tx_queues;\n \tuint8_t lso_tsov6_idx;\n \tuint8_t lso_tsov4_idx;\n+\tuint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];\n+\tuint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];\n \tuint8_t lf_rx_stats;\n \tuint8_t lf_tx_stats;\n \tuint8_t rx_chan_cnt;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 713fc0b..0f43354 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -39,6 +39,9 @@ INTERNAL {\n \troc_nix_lf_free;\n \troc_nix_lf_get_reg_count;\n \troc_nix_lf_reg_dump;\n+\troc_nix_lso_custom_fmt_setup;\n+\troc_nix_lso_fmt_get;\n+\troc_nix_lso_fmt_setup;\n \troc_nix_mac_addr_add;\n \troc_nix_mac_addr_del;\n \troc_nix_mac_addr_set;\n@@ -98,6 +101,8 @@ INTERNAL {\n \troc_nix_num_xstats_get;\n \troc_nix_xstats_get;\n \troc_nix_xstats_names_get;\n+\troc_nix_switch_hdr_set;\n+\troc_nix_eeprom_info_get;\n \troc_nix_unregister_cq_irqs;\n \troc_nix_unregister_queue_irqs;\n \troc_nix_vlan_insert_ena_dis;\n", "prefixes": [ "v3", "31/52" ] }