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GET /api/patches/90401/?format=api
{ "id": 90401, "url": "https://patches.dpdk.org/api/patches/90401/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-29-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401123817.14348-29-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401123817.14348-29-ndabilpuram@marvell.com", "date": "2021-04-01T12:37:53", "name": "[v3,28/52] common/cnxk: add nix debug dump support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "0adbdfb161e4faaa223567247e14d06f6c9b5224", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401123817.14348-29-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16059, "url": "https://patches.dpdk.org/api/series/16059/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16059", "date": "2021-04-01T12:37:25", "name": "Add Marvell CNXK common driver", "version": 3, "mbox": "https://patches.dpdk.org/series/16059/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90401/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90401/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E62F7A0548;\n\tThu, 1 Apr 2021 14:42:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2643A14125A;\n\tThu, 1 Apr 2021 14:40:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id A6A8E141258\n for <dev@dpdk.org>; Thu, 1 Apr 2021 14:40:01 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 131CPLcY019084 for <dev@dpdk.org>; Thu, 1 Apr 2021 05:40:01 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje38-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 05:40:00 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 05:39:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 05:39:58 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 373223F703F;\n Thu, 1 Apr 2021 05:39:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=gY70+y6dy/52eXCif+LEljdpQxmIaqGvfnFQV6lSzwU=;\n b=fcy+OvKGy++NPSj/rx4OTUORYiq6o2osyTXihWwCFOqT6uz6b/jJmuvJKLHXbiUlV5/e\n /03wZQB+Y9rRec59cXbdafulwiKTwDek6K3o1/G7VCy3bHQsT3S3wk6SyQ9lYA3233i0\n wo16C25+Hz8A5LRSDBYPmjdkRcbf1wncQj/LsqIBsEzN2M5c2n4l4qmA216WwoY7iX3b\n bi64YeU0JS5wYZRLONidTfsqpuX/q47j4E+I7hm5D7fHTpVpt5LEhAsxj0qwmHbSWKoJ\n RUSmP3mXItkGg4UNwzrwEtCMmPcwSNEmF3X4j0HIwUR37VTXRJyWmK3f0DK9LT8gT5ck 3w==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 18:07:53 +0530", "Message-ID": "<20210401123817.14348-29-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401123817.14348-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401123817.14348-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Spg0zMRiOnNMyyCqcErLvW0dXZgd7eGE", "X-Proofpoint-ORIG-GUID": "Spg0zMRiOnNMyyCqcErLvW0dXZgd7eGE", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_05:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 28/52] common/cnxk: add nix debug dump support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd support to dump NIX RQ, SQ and CQ contexts apart\nfrom NIX LF registers.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_nix.h | 10 +\n drivers/common/cnxk/roc_nix_debug.c | 805 ++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_irq.c | 11 +\n drivers/common/cnxk/version.map | 8 +\n 5 files changed, 835 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_debug.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 4c48f55..57253e4 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -16,6 +16,7 @@ sources = files('roc_dev.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n \t\t'roc_nix.c',\n+\t\t'roc_nix_debug.c',\n \t\t'roc_nix_irq.c',\n \t\t'roc_nix_mac.c',\n \t\t'roc_nix_mcast.c',\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 137889a..048a536 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -227,6 +227,16 @@ int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix);\n int __roc_api roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix,\n \t\t\t\t struct roc_nix_ipsec_cfg *cfg, bool enb);\n \n+/* Debug */\n+int __roc_api roc_nix_lf_get_reg_count(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data);\n+int __roc_api roc_nix_queues_ctx_dump(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n+void __roc_api roc_nix_rq_dump(struct roc_nix_rq *rq);\n+void __roc_api roc_nix_cq_dump(struct roc_nix_cq *cq);\n+void __roc_api roc_nix_sq_dump(struct roc_nix_sq *sq);\n+void __roc_api roc_nix_dump(struct roc_nix *roc_nix);\n+\n /* IRQ */\n void __roc_api roc_nix_rx_queue_intr_enable(struct roc_nix *roc_nix,\n \t\t\t\t\t uint16_t rxq_id);\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nnew file mode 100644\nindex 0000000..00712d5\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -0,0 +1,805 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+#define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n+#define NIX_REG_INFO(reg) \\\n+\t{ \\\n+\t\treg, #reg \\\n+\t}\n+#define NIX_REG_NAME_SZ 48\n+\n+#define nix_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)\n+\n+struct nix_lf_reg_info {\n+\tuint32_t offset;\n+\tconst char *name;\n+};\n+\n+static const struct nix_lf_reg_info nix_lf_reg[] = {\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(0)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(1)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(2)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(3)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(4)),\n+\tNIX_REG_INFO(NIX_LF_RX_SECRETX(5)),\n+\tNIX_REG_INFO(NIX_LF_CFG),\n+\tNIX_REG_INFO(NIX_LF_GINT),\n+\tNIX_REG_INFO(NIX_LF_GINT_W1S),\n+\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_W1S),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_RAS),\n+\tNIX_REG_INFO(NIX_LF_RAS_W1S),\n+\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1C),\n+\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1S),\n+\tNIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),\n+\tNIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),\n+\tNIX_REG_INFO(NIX_LF_SEND_ERR_DBG),\n+};\n+\n+int\n+roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint reg_count;\n+\n+\tif (roc_nix == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\treg_count = PLT_DIM(nix_lf_reg);\n+\t/* NIX_LF_TX_STATX */\n+\treg_count += nix->lf_tx_stats;\n+\t/* NIX_LF_RX_STATX */\n+\treg_count += nix->lf_rx_stats;\n+\t/* NIX_LF_QINTX_CNT*/\n+\treg_count += nix->qints;\n+\t/* NIX_LF_QINTX_INT */\n+\treg_count += nix->qints;\n+\t/* NIX_LF_QINTX_ENA_W1S */\n+\treg_count += nix->qints;\n+\t/* NIX_LF_QINTX_ENA_W1C */\n+\treg_count += nix->qints;\n+\t/* NIX_LF_CINTX_CNT */\n+\treg_count += nix->cints;\n+\t/* NIX_LF_CINTX_WAIT */\n+\treg_count += nix->cints;\n+\t/* NIX_LF_CINTX_INT */\n+\treg_count += nix->cints;\n+\t/* NIX_LF_CINTX_INT_W1S */\n+\treg_count += nix->cints;\n+\t/* NIX_LF_CINTX_ENA_W1S */\n+\treg_count += nix->cints;\n+\t/* NIX_LF_CINTX_ENA_W1C */\n+\treg_count += nix->cints;\n+\n+\treturn reg_count;\n+}\n+\n+int\n+roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuintptr_t nix_lf_base = nix->base;\n+\tbool dump_stdout;\n+\tuint64_t reg;\n+\tuint32_t i;\n+\n+\tif (roc_nix == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tdump_stdout = data ? 0 : 1;\n+\n+\tfor (i = 0; i < PLT_DIM(nix_lf_reg); i++) {\n+\t\treg = plt_read64(nix_lf_base + nix_lf_reg[i].offset);\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s = 0x%\" PRIx64, nix_lf_reg[i].name, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_TX_STATX */\n+\tfor (i = 0; i < nix->lf_tx_stats; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_TX_STATX\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_RX_STATX */\n+\tfor (i = 0; i < nix->lf_rx_stats; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_RX_STATX\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_CNT*/\n+\tfor (i = 0; i < nix->qints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_CNT\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_INT */\n+\tfor (i = 0; i < nix->qints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_INT\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_ENA_W1S */\n+\tfor (i = 0; i < nix->qints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_ENA_W1S\",\n+\t\t\t\t i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_QINTX_ENA_W1C */\n+\tfor (i = 0; i < nix->qints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_QINTX_ENA_W1C\",\n+\t\t\t\t i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_CNT */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_CNT\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_WAIT */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_WAIT\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_INT */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_INT\", i,\n+\t\t\t\t reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_INT_W1S */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_INT_W1S\",\n+\t\t\t\t i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_ENA_W1S */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_ENA_W1S\",\n+\t\t\t\t i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\n+\t/* NIX_LF_CINTX_ENA_W1C */\n+\tfor (i = 0; i < nix->cints; i++) {\n+\t\treg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));\n+\t\tif (dump_stdout && reg)\n+\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64, \"NIX_LF_CINTX_ENA_W1C\",\n+\t\t\t\t i, reg);\n+\t\tif (data)\n+\t\t\t*data++ = reg;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nix_q_ctx_get(struct mbox *mbox, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n+{\n+\tint rc;\n+\n+\tif (roc_model_is_cn9k()) {\n+\t\tstruct nix_aq_enq_rsp *rsp;\n+\t\tstruct nix_aq_enq_req *aq;\n+\t\tint rc;\n+\n+\t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = ctype;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\tif (ctype == NIX_AQ_CTYPE_RQ)\n+\t\t\t*ctx_p = &rsp->rq;\n+\t\telse if (ctype == NIX_AQ_CTYPE_SQ)\n+\t\t\t*ctx_p = &rsp->sq;\n+\t\telse\n+\t\t\t*ctx_p = &rsp->cq;\n+\t} else {\n+\t\tstruct nix_cn10k_aq_enq_rsp *rsp;\n+\t\tstruct nix_cn10k_aq_enq_req *aq;\n+\n+\t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\taq->qidx = qid;\n+\t\taq->ctype = ctype;\n+\t\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\t\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\n+\t\tif (ctype == NIX_AQ_CTYPE_RQ)\n+\t\t\t*ctx_p = &rsp->rq;\n+\t\telse if (ctype == NIX_AQ_CTYPE_SQ)\n+\t\t\t*ctx_p = &rsp->sq;\n+\t\telse\n+\t\t\t*ctx_p = &rsp->cq;\n+\t}\n+\treturn 0;\n+}\n+\n+static inline void\n+nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p)\n+{\n+\tnix_dump(\"W0: sqe_way_mask \\t\\t%d\\nW0: cq \\t\\t\\t\\t%d\",\n+\t\t ctx->sqe_way_mask, ctx->cq);\n+\tnix_dump(\"W0: sdp_mcast \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n+\t\t ctx->sdp_mcast, ctx->substream);\n+\tnix_dump(\"W0: qint_idx \\t\\t\\t%d\\nW0: ena \\t\\t\\t%d\\n\", ctx->qint_idx,\n+\t\t ctx->ena);\n+\n+\tnix_dump(\"W1: sqb_count \\t\\t\\t%d\\nW1: default_chan \\t\\t%d\",\n+\t\t ctx->sqb_count, ctx->default_chan);\n+\tnix_dump(\"W1: smq_rr_quantum \\t\\t%d\\nW1: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->smq_rr_quantum, ctx->sso_ena);\n+\tnix_dump(\"W1: xoff \\t\\t\\t%d\\nW1: cq_ena \\t\\t\\t%d\\nW1: smq\\t\\t\\t\\t%d\\n\",\n+\t\t ctx->xoff, ctx->cq_ena, ctx->smq);\n+\n+\tnix_dump(\"W2: sqe_stype \\t\\t\\t%d\\nW2: sq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->sqe_stype, ctx->sq_int_ena);\n+\tnix_dump(\"W2: sq_int \\t\\t\\t%d\\nW2: sqb_aura \\t\\t\\t%d\", ctx->sq_int,\n+\t\t ctx->sqb_aura);\n+\tnix_dump(\"W2: smq_rr_count \\t\\t%d\\n\", ctx->smq_rr_count);\n+\n+\tnix_dump(\"W3: smq_next_sq_vld\\t\\t%d\\nW3: smq_pend\\t\\t\\t%d\",\n+\t\t ctx->smq_next_sq_vld, ctx->smq_pend);\n+\tnix_dump(\"W3: smenq_next_sqb_vld \\t%d\\nW3: head_offset\\t\\t\\t%d\",\n+\t\t ctx->smenq_next_sqb_vld, ctx->head_offset);\n+\tnix_dump(\"W3: smenq_offset\\t\\t%d\\nW3: tail_offset \\t\\t%d\",\n+\t\t ctx->smenq_offset, ctx->tail_offset);\n+\tnix_dump(\"W3: smq_lso_segnum \\t\\t%d\\nW3: smq_next_sq \\t\\t%d\",\n+\t\t ctx->smq_lso_segnum, ctx->smq_next_sq);\n+\tnix_dump(\"W3: mnq_dis \\t\\t\\t%d\\nW3: lmt_dis \\t\\t\\t%d\", ctx->mnq_dis,\n+\t\t ctx->lmt_dis);\n+\tnix_dump(\"W3: cq_limit\\t\\t\\t%d\\nW3: max_sqe_size\\t\\t%d\\n\",\n+\t\t ctx->cq_limit, ctx->max_sqe_size);\n+\n+\tnix_dump(\"W4: next_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->next_sqb);\n+\tnix_dump(\"W5: tail_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->tail_sqb);\n+\tnix_dump(\"W6: smenq_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->smenq_sqb);\n+\tnix_dump(\"W7: smenq_next_sqb \\t\\t0x%\" PRIx64 \"\", ctx->smenq_next_sqb);\n+\tnix_dump(\"W8: head_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->head_sqb);\n+\n+\tnix_dump(\"W9: vfi_lso_vld \\t\\t%d\\nW9: vfi_lso_vlan1_ins_ena\\t%d\",\n+\t\t ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);\n+\tnix_dump(\"W9: vfi_lso_vlan0_ins_ena\\t%d\\nW9: vfi_lso_mps\\t\\t\\t%d\",\n+\t\t ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);\n+\tnix_dump(\"W9: vfi_lso_sb \\t\\t\\t%d\\nW9: vfi_lso_sizem1\\t\\t%d\",\n+\t\t ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);\n+\tnix_dump(\"W9: vfi_lso_total\\t\\t%d\", ctx->vfi_lso_total);\n+\n+\tnix_dump(\"W10: scm_lso_rem \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->scm_lso_rem);\n+\tnix_dump(\"W11: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W12: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W14: dropped_octs \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W15: dropped_pkts \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_pkts);\n+\n+\t*sqb_aura_p = ctx->sqb_aura;\n+}\n+\n+static inline void\n+nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p)\n+{\n+\tnix_dump(\"W0: sqe_way_mask \\t\\t%d\\nW0: cq \\t\\t\\t\\t%d\",\n+\t\t ctx->sqe_way_mask, ctx->cq);\n+\tnix_dump(\"W0: sdp_mcast \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n+\t\t ctx->sdp_mcast, ctx->substream);\n+\tnix_dump(\"W0: qint_idx \\t\\t\\t%d\\nW0: ena \\t\\t\\t%d\\n\", ctx->qint_idx,\n+\t\t ctx->ena);\n+\n+\tnix_dump(\"W1: sqb_count \\t\\t\\t%d\\nW1: default_chan \\t\\t%d\",\n+\t\t ctx->sqb_count, ctx->default_chan);\n+\tnix_dump(\"W1: smq_rr_weight \\t\\t%d\\nW1: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->smq_rr_weight, ctx->sso_ena);\n+\tnix_dump(\"W1: xoff \\t\\t\\t%d\\nW1: cq_ena \\t\\t\\t%d\\nW1: smq\\t\\t\\t\\t%d\\n\",\n+\t\t ctx->xoff, ctx->cq_ena, ctx->smq);\n+\n+\tnix_dump(\"W2: sqe_stype \\t\\t\\t%d\\nW2: sq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->sqe_stype, ctx->sq_int_ena);\n+\tnix_dump(\"W2: sq_int \\t\\t\\t%d\\nW2: sqb_aura \\t\\t\\t%d\", ctx->sq_int,\n+\t\t ctx->sqb_aura);\n+\tnix_dump(\"W2: smq_rr_count[ub:lb] \\t\\t%x:%x\\n\", ctx->smq_rr_count_ub,\n+\t\t ctx->smq_rr_count_lb);\n+\n+\tnix_dump(\"W3: smq_next_sq_vld\\t\\t%d\\nW3: smq_pend\\t\\t\\t%d\",\n+\t\t ctx->smq_next_sq_vld, ctx->smq_pend);\n+\tnix_dump(\"W3: smenq_next_sqb_vld \\t%d\\nW3: head_offset\\t\\t\\t%d\",\n+\t\t ctx->smenq_next_sqb_vld, ctx->head_offset);\n+\tnix_dump(\"W3: smenq_offset\\t\\t%d\\nW3: tail_offset \\t\\t%d\",\n+\t\t ctx->smenq_offset, ctx->tail_offset);\n+\tnix_dump(\"W3: smq_lso_segnum \\t\\t%d\\nW3: smq_next_sq \\t\\t%d\",\n+\t\t ctx->smq_lso_segnum, ctx->smq_next_sq);\n+\tnix_dump(\"W3: mnq_dis \\t\\t\\t%d\\nW3: lmt_dis \\t\\t\\t%d\", ctx->mnq_dis,\n+\t\t ctx->lmt_dis);\n+\tnix_dump(\"W3: cq_limit\\t\\t\\t%d\\nW3: max_sqe_size\\t\\t%d\\n\",\n+\t\t ctx->cq_limit, ctx->max_sqe_size);\n+\n+\tnix_dump(\"W4: next_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->next_sqb);\n+\tnix_dump(\"W5: tail_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->tail_sqb);\n+\tnix_dump(\"W6: smenq_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->smenq_sqb);\n+\tnix_dump(\"W7: smenq_next_sqb \\t\\t0x%\" PRIx64 \"\", ctx->smenq_next_sqb);\n+\tnix_dump(\"W8: head_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->head_sqb);\n+\n+\tnix_dump(\"W9: vfi_lso_vld \\t\\t%d\\nW9: vfi_lso_vlan1_ins_ena\\t%d\",\n+\t\t ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);\n+\tnix_dump(\"W9: vfi_lso_vlan0_ins_ena\\t%d\\nW9: vfi_lso_mps\\t\\t\\t%d\",\n+\t\t ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);\n+\tnix_dump(\"W9: vfi_lso_sb \\t\\t\\t%d\\nW9: vfi_lso_sizem1\\t\\t%d\",\n+\t\t ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);\n+\tnix_dump(\"W9: vfi_lso_total\\t\\t%d\", ctx->vfi_lso_total);\n+\n+\tnix_dump(\"W10: scm_lso_rem \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->scm_lso_rem);\n+\tnix_dump(\"W11: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W12: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W14: dropped_octs \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W15: dropped_pkts \\t\\t0x%\" PRIx64 \"\",\n+\t\t (uint64_t)ctx->drop_pkts);\n+\n+\t*sqb_aura_p = ctx->sqb_aura;\n+}\n+\n+static inline void\n+nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n+\t\t ctx->wqe_aura, ctx->substream);\n+\tnix_dump(\"W0: cq \\t\\t\\t\\t%d\\nW0: ena_wqwd \\t\\t\\t%d\", ctx->cq,\n+\t\t ctx->ena_wqwd);\n+\tnix_dump(\"W0: ipsech_ena \\t\\t\\t%d\\nW0: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->ipsech_ena, ctx->sso_ena);\n+\tnix_dump(\"W0: ena \\t\\t\\t%d\\n\", ctx->ena);\n+\n+\tnix_dump(\"W1: lpb_drop_ena \\t\\t%d\\nW1: spb_drop_ena \\t\\t%d\",\n+\t\t ctx->lpb_drop_ena, ctx->spb_drop_ena);\n+\tnix_dump(\"W1: xqe_drop_ena \\t\\t%d\\nW1: wqe_caching \\t\\t%d\",\n+\t\t ctx->xqe_drop_ena, ctx->wqe_caching);\n+\tnix_dump(\"W1: pb_caching \\t\\t\\t%d\\nW1: sso_tt \\t\\t\\t%d\",\n+\t\t ctx->pb_caching, ctx->sso_tt);\n+\tnix_dump(\"W1: sso_grp \\t\\t\\t%d\\nW1: lpb_aura \\t\\t\\t%d\", ctx->sso_grp,\n+\t\t ctx->lpb_aura);\n+\tnix_dump(\"W1: spb_aura \\t\\t\\t%d\\n\", ctx->spb_aura);\n+\n+\tnix_dump(\"W2: xqe_hdr_split \\t\\t%d\\nW2: xqe_imm_copy \\t\\t%d\",\n+\t\t ctx->xqe_hdr_split, ctx->xqe_imm_copy);\n+\tnix_dump(\"W2: xqe_imm_size \\t\\t%d\\nW2: later_skip \\t\\t\\t%d\",\n+\t\t ctx->xqe_imm_size, ctx->later_skip);\n+\tnix_dump(\"W2: first_skip \\t\\t\\t%d\\nW2: lpb_sizem1 \\t\\t\\t%d\",\n+\t\t ctx->first_skip, ctx->lpb_sizem1);\n+\tnix_dump(\"W2: spb_ena \\t\\t\\t%d\\nW2: wqe_skip \\t\\t\\t%d\", ctx->spb_ena,\n+\t\t ctx->wqe_skip);\n+\tnix_dump(\"W2: spb_sizem1 \\t\\t\\t%d\\n\", ctx->spb_sizem1);\n+\n+\tnix_dump(\"W3: spb_pool_pass \\t\\t%d\\nW3: spb_pool_drop \\t\\t%d\",\n+\t\t ctx->spb_pool_pass, ctx->spb_pool_drop);\n+\tnix_dump(\"W3: spb_aura_pass \\t\\t%d\\nW3: spb_aura_drop \\t\\t%d\",\n+\t\t ctx->spb_aura_pass, ctx->spb_aura_drop);\n+\tnix_dump(\"W3: wqe_pool_pass \\t\\t%d\\nW3: wqe_pool_drop \\t\\t%d\",\n+\t\t ctx->wqe_pool_pass, ctx->wqe_pool_drop);\n+\tnix_dump(\"W3: xqe_pass \\t\\t\\t%d\\nW3: xqe_drop \\t\\t\\t%d\\n\",\n+\t\t ctx->xqe_pass, ctx->xqe_drop);\n+\n+\tnix_dump(\"W4: qint_idx \\t\\t\\t%d\\nW4: rq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->qint_idx, ctx->rq_int_ena);\n+\tnix_dump(\"W4: rq_int \\t\\t\\t%d\\nW4: lpb_pool_pass \\t\\t%d\", ctx->rq_int,\n+\t\t ctx->lpb_pool_pass);\n+\tnix_dump(\"W4: lpb_pool_drop \\t\\t%d\\nW4: lpb_aura_pass \\t\\t%d\",\n+\t\t ctx->lpb_pool_drop, ctx->lpb_aura_pass);\n+\tnix_dump(\"W4: lpb_aura_drop \\t\\t%d\\n\", ctx->lpb_aura_drop);\n+\n+\tnix_dump(\"W5: flow_tagw \\t\\t\\t%d\\nW5: bad_utag \\t\\t\\t%d\",\n+\t\t ctx->flow_tagw, ctx->bad_utag);\n+\tnix_dump(\"W5: good_utag \\t\\t\\t%d\\nW5: ltag \\t\\t\\t%d\\n\", ctx->good_utag,\n+\t\t ctx->ltag);\n+\n+\tnix_dump(\"W6: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W7: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W8: drop_octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W9: drop_pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_pkts);\n+\tnix_dump(\"W10: re_pkts \\t\\t\\t0x%\" PRIx64 \"\\n\", (uint64_t)ctx->re_pkts);\n+}\n+\n+static inline void\n+nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: len_ol3_dis \\t\\t\\t%d\",\n+\t\t ctx->wqe_aura, ctx->len_ol3_dis);\n+\tnix_dump(\"W0: len_ol4_dis \\t\\t\\t%d\\nW0: len_il3_dis \\t\\t\\t%d\",\n+\t\t ctx->len_ol4_dis, ctx->len_il3_dis);\n+\tnix_dump(\"W0: len_il4_dis \\t\\t\\t%d\\nW0: csum_ol4_dis \\t\\t\\t%d\",\n+\t\t ctx->len_il4_dis, ctx->csum_ol4_dis);\n+\tnix_dump(\"W0: csum_ol3_dis \\t\\t\\t%d\\nW0: lenerr_dis \\t\\t\\t%d\",\n+\t\t ctx->csum_ol4_dis, ctx->lenerr_dis);\n+\tnix_dump(\"W0: cq \\t\\t\\t\\t%d\\nW0: ena_wqwd \\t\\t\\t%d\", ctx->cq,\n+\t\t ctx->ena_wqwd);\n+\tnix_dump(\"W0: ipsech_ena \\t\\t\\t%d\\nW0: sso_ena \\t\\t\\t%d\",\n+\t\t ctx->ipsech_ena, ctx->sso_ena);\n+\tnix_dump(\"W0: ena \\t\\t\\t%d\\n\", ctx->ena);\n+\n+\tnix_dump(\"W1: chi_ena \\t\\t%d\\nW1: ipsecd_drop_en \\t\\t%d\", ctx->chi_ena,\n+\t\t ctx->ipsecd_drop_en);\n+\tnix_dump(\"W1: pb_stashing \\t\\t\\t%d\", ctx->pb_stashing);\n+\tnix_dump(\"W1: lpb_drop_ena \\t\\t%d\\nW1: spb_drop_ena \\t\\t%d\",\n+\t\t ctx->lpb_drop_ena, ctx->spb_drop_ena);\n+\tnix_dump(\"W1: xqe_drop_ena \\t\\t%d\\nW1: wqe_caching \\t\\t%d\",\n+\t\t ctx->xqe_drop_ena, ctx->wqe_caching);\n+\tnix_dump(\"W1: pb_caching \\t\\t\\t%d\\nW1: sso_tt \\t\\t\\t%d\",\n+\t\t ctx->pb_caching, ctx->sso_tt);\n+\tnix_dump(\"W1: sso_grp \\t\\t\\t%d\\nW1: lpb_aura \\t\\t\\t%d\", ctx->sso_grp,\n+\t\t ctx->lpb_aura);\n+\tnix_dump(\"W1: spb_aura \\t\\t\\t%d\\n\", ctx->spb_aura);\n+\n+\tnix_dump(\"W2: xqe_hdr_split \\t\\t%d\\nW2: xqe_imm_copy \\t\\t%d\",\n+\t\t ctx->xqe_hdr_split, ctx->xqe_imm_copy);\n+\tnix_dump(\"W2: xqe_imm_size \\t\\t%d\\nW2: later_skip \\t\\t\\t%d\",\n+\t\t ctx->xqe_imm_size, ctx->later_skip);\n+\tnix_dump(\"W2: first_skip \\t\\t\\t%d\\nW2: lpb_sizem1 \\t\\t\\t%d\",\n+\t\t ctx->first_skip, ctx->lpb_sizem1);\n+\tnix_dump(\"W2: spb_ena \\t\\t\\t%d\\nW2: wqe_skip \\t\\t\\t%d\", ctx->spb_ena,\n+\t\t ctx->wqe_skip);\n+\tnix_dump(\"W2: spb_sizem1 \\t\\t\\t%d\\nW2: policer_ena \\t\\t\\t%d\",\n+\t\t ctx->spb_sizem1, ctx->policer_ena);\n+\tnix_dump(\"W2: band_prof_id \\t\\t\\t%d\", ctx->band_prof_id);\n+\n+\tnix_dump(\"W3: spb_pool_pass \\t\\t%d\\nW3: spb_pool_drop \\t\\t%d\",\n+\t\t ctx->spb_pool_pass, ctx->spb_pool_drop);\n+\tnix_dump(\"W3: spb_aura_pass \\t\\t%d\\nW3: spb_aura_drop \\t\\t%d\",\n+\t\t ctx->spb_aura_pass, ctx->spb_aura_drop);\n+\tnix_dump(\"W3: wqe_pool_pass \\t\\t%d\\nW3: wqe_pool_drop \\t\\t%d\",\n+\t\t ctx->wqe_pool_pass, ctx->wqe_pool_drop);\n+\tnix_dump(\"W3: xqe_pass \\t\\t\\t%d\\nW3: xqe_drop \\t\\t\\t%d\\n\",\n+\t\t ctx->xqe_pass, ctx->xqe_drop);\n+\n+\tnix_dump(\"W4: qint_idx \\t\\t\\t%d\\nW4: rq_int_ena \\t\\t\\t%d\",\n+\t\t ctx->qint_idx, ctx->rq_int_ena);\n+\tnix_dump(\"W4: rq_int \\t\\t\\t%d\\nW4: lpb_pool_pass \\t\\t%d\", ctx->rq_int,\n+\t\t ctx->lpb_pool_pass);\n+\tnix_dump(\"W4: lpb_pool_drop \\t\\t%d\\nW4: lpb_aura_pass \\t\\t%d\",\n+\t\t ctx->lpb_pool_drop, ctx->lpb_aura_pass);\n+\tnix_dump(\"W4: lpb_aura_drop \\t\\t%d\\n\", ctx->lpb_aura_drop);\n+\n+\tnix_dump(\"W5: vwqe_skip \\t\\t\\t%d\\nW5: max_vsize_exp \\t\\t\\t%d\",\n+\t\t ctx->vwqe_skip, ctx->max_vsize_exp);\n+\tnix_dump(\"W5: vtime_wait \\t\\t\\t%d\\nW5: vwqe_ena \\t\\t\\t%d\",\n+\t\t ctx->vtime_wait, ctx->max_vsize_exp);\n+\tnix_dump(\"W5: ipsec_vwqe \\t\\t\\t%d\", ctx->ipsec_vwqe);\n+\tnix_dump(\"W5: flow_tagw \\t\\t\\t%d\\nW5: bad_utag \\t\\t\\t%d\",\n+\t\t ctx->flow_tagw, ctx->bad_utag);\n+\tnix_dump(\"W5: good_utag \\t\\t\\t%d\\nW5: ltag \\t\\t\\t%d\\n\", ctx->good_utag,\n+\t\t ctx->ltag);\n+\n+\tnix_dump(\"W6: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n+\tnix_dump(\"W7: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n+\tnix_dump(\"W8: drop_octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_octs);\n+\tnix_dump(\"W9: drop_pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_pkts);\n+\tnix_dump(\"W10: re_pkts \\t\\t\\t0x%\" PRIx64 \"\\n\", (uint64_t)ctx->re_pkts);\n+}\n+\n+static inline void\n+nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx)\n+{\n+\tnix_dump(\"W0: base \\t\\t\\t0x%\" PRIx64 \"\\n\", ctx->base);\n+\n+\tnix_dump(\"W1: wrptr \\t\\t\\t%\" PRIx64 \"\", (uint64_t)ctx->wrptr);\n+\tnix_dump(\"W1: avg_con \\t\\t\\t%d\\nW1: cint_idx \\t\\t\\t%d\", ctx->avg_con,\n+\t\t ctx->cint_idx);\n+\tnix_dump(\"W1: cq_err \\t\\t\\t%d\\nW1: qint_idx \\t\\t\\t%d\", ctx->cq_err,\n+\t\t ctx->qint_idx);\n+\tnix_dump(\"W1: bpid \\t\\t\\t%d\\nW1: bp_ena \\t\\t\\t%d\\n\", ctx->bpid,\n+\t\t ctx->bp_ena);\n+\n+\tnix_dump(\"W2: update_time \\t\\t%d\\nW2: avg_level \\t\\t\\t%d\",\n+\t\t ctx->update_time, ctx->avg_level);\n+\tnix_dump(\"W2: head \\t\\t\\t%d\\nW2: tail \\t\\t\\t%d\\n\", ctx->head,\n+\t\t ctx->tail);\n+\n+\tnix_dump(\"W3: cq_err_int_ena \\t\\t%d\\nW3: cq_err_int \\t\\t\\t%d\",\n+\t\t ctx->cq_err_int_ena, ctx->cq_err_int);\n+\tnix_dump(\"W3: qsize \\t\\t\\t%d\\nW3: caching \\t\\t\\t%d\", ctx->qsize,\n+\t\t ctx->caching);\n+\tnix_dump(\"W3: substream \\t\\t\\t0x%03x\\nW3: ena \\t\\t\\t%d\", ctx->substream,\n+\t\t ctx->ena);\n+\tnix_dump(\"W3: drop_ena \\t\\t\\t%d\\nW3: drop \\t\\t\\t%d\", ctx->drop_ena,\n+\t\t ctx->drop);\n+\tnix_dump(\"W3: bp \\t\\t\\t\\t%d\\n\", ctx->bp);\n+}\n+\n+int\n+roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc = -1, q, rq = nix->nb_rx_queues;\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct npa_aq_enq_rsp *npa_rsp;\n+\tstruct npa_aq_enq_req *npa_aq;\n+\tvolatile void *ctx;\n+\tint sq = nix->nb_tx_queues;\n+\tstruct npa_lf *npa_lf;\n+\tuint32_t sqb_aura;\n+\n+\tnpa_lf = idev_npa_obj_get();\n+\tif (npa_lf == NULL)\n+\t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n+\n+\tfor (q = 0; q < rq; q++) {\n+\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_CQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get cq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d cq=%d ===============\",\n+\t\t\t roc_nix->port_id, q);\n+\t\tnix_lf_cq_dump(ctx);\n+\t}\n+\n+\tfor (q = 0; q < rq; q++) {\n+\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_RQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d rq=%d ===============\",\n+\t\t\t roc_nix->port_id, q);\n+\t\tif (roc_model_is_cn9k())\n+\t\t\tnix_cn9k_lf_rq_dump(ctx);\n+\t\telse\n+\t\t\tnix_lf_rq_dump(ctx);\n+\t}\n+\n+\tfor (q = 0; q < sq; q++) {\n+\t\trc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_SQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get sq context\");\n+\t\t\tgoto fail;\n+\t\t}\n+\t\tnix_dump(\"============== port=%d sq=%d ===============\",\n+\t\t\t roc_nix->port_id, q);\n+\t\tif (roc_model_is_cn9k())\n+\t\t\tnix_cn9k_lf_sq_dump(ctx, &sqb_aura);\n+\t\telse\n+\t\t\tnix_lf_sq_dump(ctx, &sqb_aura);\n+\n+\t\tif (!npa_lf) {\n+\t\t\tplt_err(\"NPA LF does not exist\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Dump SQB Aura minimal info */\n+\t\tnpa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n+\t\tif (npa_aq == NULL)\n+\t\t\treturn -ENOSPC;\n+\t\tnpa_aq->aura_id = sqb_aura;\n+\t\tnpa_aq->ctype = NPA_AQ_CTYPE_AURA;\n+\t\tnpa_aq->op = NPA_AQ_INSTOP_READ;\n+\n+\t\trc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get sq's sqb_aura context\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tnix_dump(\"\\nSQB Aura W0: Pool addr\\t\\t0x%\" PRIx64 \"\",\n+\t\t\t npa_rsp->aura.pool_addr);\n+\t\tnix_dump(\"SQB Aura W1: ena\\t\\t\\t%d\", npa_rsp->aura.ena);\n+\t\tnix_dump(\"SQB Aura W2: count\\t\\t%\" PRIx64 \"\",\n+\t\t\t (uint64_t)npa_rsp->aura.count);\n+\t\tnix_dump(\"SQB Aura W3: limit\\t\\t%\" PRIx64 \"\",\n+\t\t\t (uint64_t)npa_rsp->aura.limit);\n+\t\tnix_dump(\"SQB Aura W3: fc_ena\\t\\t%d\", npa_rsp->aura.fc_ena);\n+\t\tnix_dump(\"SQB Aura W4: fc_addr\\t\\t0x%\" PRIx64 \"\\n\",\n+\t\t\t npa_rsp->aura.fc_addr);\n+\t}\n+\n+fail:\n+\treturn rc;\n+}\n+\n+/* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */\n+void\n+roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n+{\n+\tconst union nix_rx_parse_u *rx =\n+\t\t(const union nix_rx_parse_u *)((const uint64_t *)cq + 1);\n+\n+\tnix_dump(\"tag \\t\\t0x%x\\tq \\t\\t%d\\t\\tnode \\t\\t%d\\tcqe_type \\t%d\",\n+\t\t cq->tag, cq->q, cq->node, cq->cqe_type);\n+\n+\tnix_dump(\"W0: chan \\t%d\\t\\tdesc_sizem1 \\t%d\", rx->chan,\n+\t\t rx->desc_sizem1);\n+\tnix_dump(\"W0: imm_copy \\t%d\\t\\texpress \\t%d\", rx->imm_copy,\n+\t\t rx->express);\n+\tnix_dump(\"W0: wqwd \\t%d\\t\\terrlev \\t\\t%d\\t\\terrcode \\t%d\", rx->wqwd,\n+\t\t rx->errlev, rx->errcode);\n+\tnix_dump(\"W0: latype \\t%d\\t\\tlbtype \\t\\t%d\\t\\tlctype \\t\\t%d\",\n+\t\t rx->latype, rx->lbtype, rx->lctype);\n+\tnix_dump(\"W0: ldtype \\t%d\\t\\tletype \\t\\t%d\\t\\tlftype \\t\\t%d\",\n+\t\t rx->ldtype, rx->letype, rx->lftype);\n+\tnix_dump(\"W0: lgtype \\t%d \\t\\tlhtype \\t\\t%d\", rx->lgtype, rx->lhtype);\n+\n+\tnix_dump(\"W1: pkt_lenm1 \\t%d\", rx->pkt_lenm1);\n+\tnix_dump(\"W1: l2m \\t%d\\t\\tl2b \\t\\t%d\\t\\tl3m \\t\\t%d\\tl3b \\t\\t%d\",\n+\t\t rx->l2m, rx->l2b, rx->l3m, rx->l3b);\n+\tnix_dump(\"W1: vtag0_valid %d\\t\\tvtag0_gone \\t%d\", rx->vtag0_valid,\n+\t\t rx->vtag0_gone);\n+\tnix_dump(\"W1: vtag1_valid %d\\t\\tvtag1_gone \\t%d\", rx->vtag1_valid,\n+\t\t rx->vtag1_gone);\n+\tnix_dump(\"W1: pkind \\t%d\", rx->pkind);\n+\tnix_dump(\"W1: vtag0_tci \\t%d\\t\\tvtag1_tci \\t%d\", rx->vtag0_tci,\n+\t\t rx->vtag1_tci);\n+\n+\tnix_dump(\"W2: laflags \\t%d\\t\\tlbflags\\t\\t%d\\t\\tlcflags \\t%d\",\n+\t\t rx->laflags, rx->lbflags, rx->lcflags);\n+\tnix_dump(\"W2: ldflags \\t%d\\t\\tleflags\\t\\t%d\\t\\tlfflags \\t%d\",\n+\t\t rx->ldflags, rx->leflags, rx->lfflags);\n+\tnix_dump(\"W2: lgflags \\t%d\\t\\tlhflags \\t%d\", rx->lgflags, rx->lhflags);\n+\n+\tnix_dump(\"W3: eoh_ptr \\t%d\\t\\twqe_aura \\t%d\\t\\tpb_aura \\t%d\",\n+\t\t rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);\n+\tnix_dump(\"W3: match_id \\t%d\", rx->match_id);\n+\n+\tnix_dump(\"W4: laptr \\t%d\\t\\tlbptr \\t\\t%d\\t\\tlcptr \\t\\t%d\", rx->laptr,\n+\t\t rx->lbptr, rx->lcptr);\n+\tnix_dump(\"W4: ldptr \\t%d\\t\\tleptr \\t\\t%d\\t\\tlfptr \\t\\t%d\", rx->ldptr,\n+\t\t rx->leptr, rx->lfptr);\n+\tnix_dump(\"W4: lgptr \\t%d\\t\\tlhptr \\t\\t%d\", rx->lgptr, rx->lhptr);\n+\n+\tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n+\t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n+}\n+\n+void\n+roc_nix_rq_dump(struct roc_nix_rq *rq)\n+{\n+\tnix_dump(\"nix_rq@%p\", rq);\n+\tnix_dump(\" qid = %d\", rq->qid);\n+\tnix_dump(\" aura_handle = 0x%\" PRIx64 \"\", rq->aura_handle);\n+\tnix_dump(\" ipsec_ena = %d\", rq->ipsech_ena);\n+\tnix_dump(\" first_skip = %d\", rq->first_skip);\n+\tnix_dump(\" later_skip = %d\", rq->later_skip);\n+\tnix_dump(\" lpb_size = %d\", rq->lpb_size);\n+\tnix_dump(\" sso_ena = %d\", rq->sso_ena);\n+\tnix_dump(\" tag_mask = %d\", rq->tag_mask);\n+\tnix_dump(\" flow_tag_width = %d\", rq->flow_tag_width);\n+\tnix_dump(\" tt = %d\", rq->tt);\n+\tnix_dump(\" hwgrp = %d\", rq->hwgrp);\n+\tnix_dump(\" vwqe_ena = %d\", rq->vwqe_ena);\n+\tnix_dump(\" vwqe_first_skip = %d\", rq->vwqe_first_skip);\n+\tnix_dump(\" vwqe_max_sz_exp = %d\", rq->vwqe_max_sz_exp);\n+\tnix_dump(\" vwqe_wait_tmo = %ld\", rq->vwqe_wait_tmo);\n+\tnix_dump(\" vwqe_aura_handle = %ld\", rq->vwqe_aura_handle);\n+\tnix_dump(\" roc_nix = %p\", rq->roc_nix);\n+}\n+\n+void\n+roc_nix_cq_dump(struct roc_nix_cq *cq)\n+{\n+\tnix_dump(\"nix_cq@%p\", cq);\n+\tnix_dump(\" qid = %d\", cq->qid);\n+\tnix_dump(\" qnb_desc = %d\", cq->nb_desc);\n+\tnix_dump(\" roc_nix = %p\", cq->roc_nix);\n+\tnix_dump(\" door = 0x%\" PRIx64 \"\", cq->door);\n+\tnix_dump(\" status = %p\", cq->status);\n+\tnix_dump(\" wdata = 0x%\" PRIx64 \"\", cq->wdata);\n+\tnix_dump(\" desc_base = %p\", cq->desc_base);\n+\tnix_dump(\" qmask = 0x%\" PRIx32 \"\", cq->qmask);\n+}\n+\n+void\n+roc_nix_sq_dump(struct roc_nix_sq *sq)\n+{\n+\tnix_dump(\"nix_sq@%p\", sq);\n+\tnix_dump(\" qid = %d\", sq->qid);\n+\tnix_dump(\" max_sqe_sz = %d\", sq->max_sqe_sz);\n+\tnix_dump(\" nb_desc = %d\", sq->nb_desc);\n+\tnix_dump(\" sqes_per_sqb_log2 = %d\", sq->sqes_per_sqb_log2);\n+\tnix_dump(\" roc_nix= %p\", sq->roc_nix);\n+\tnix_dump(\" aura_handle = 0x%\" PRIx64 \"\", sq->aura_handle);\n+\tnix_dump(\" nb_sqb_bufs_adj = %d\", sq->nb_sqb_bufs_adj);\n+\tnix_dump(\" nb_sqb_bufs = %d\", sq->nb_sqb_bufs);\n+\tnix_dump(\" io_addr = 0x%\" PRIx64 \"\", sq->io_addr);\n+\tnix_dump(\" lmt_addr = %p\", sq->lmt_addr);\n+\tnix_dump(\" sqe_mem = %p\", sq->sqe_mem);\n+\tnix_dump(\" fc = %p\", sq->fc);\n+};\n+\n+void\n+roc_nix_dump(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\tnix_dump(\"nix@%p\", nix);\n+\tnix_dump(\" pf = %d\", dev_get_pf(dev->pf_func));\n+\tnix_dump(\" vf = %d\", dev_get_vf(dev->pf_func));\n+\tnix_dump(\" bar2 = 0x%\" PRIx64, dev->bar2);\n+\tnix_dump(\" bar4 = 0x%\" PRIx64, dev->bar4);\n+\tnix_dump(\" port_id = %d\", roc_nix->port_id);\n+\tnix_dump(\" rss_tag_as_xor = %d\", roc_nix->rss_tag_as_xor);\n+\tnix_dump(\" rss_tag_as_xor = %d\", roc_nix->max_sqb_count);\n+\n+\tnix_dump(\" \\tpci_dev = %p\", nix->pci_dev);\n+\tnix_dump(\" \\tbase = 0x%\" PRIxPTR \"\", nix->base);\n+\tnix_dump(\" \\tlmt_base = 0x%\" PRIxPTR \"\", nix->lmt_base);\n+\tnix_dump(\" \\treta_size = %d\", nix->reta_sz);\n+\tnix_dump(\" \\ttx_chan_base = %d\", nix->tx_chan_base);\n+\tnix_dump(\" \\trx_chan_base = %d\", nix->rx_chan_base);\n+\tnix_dump(\" \\tnb_rx_queues = %d\", nix->nb_rx_queues);\n+\tnix_dump(\" \\tnb_tx_queues = %d\", nix->nb_tx_queues);\n+\tnix_dump(\" \\tlso_tsov6_idx = %d\", nix->lso_tsov6_idx);\n+\tnix_dump(\" \\tlso_tsov4_idx = %d\", nix->lso_tsov4_idx);\n+\tnix_dump(\" \\tlf_rx_stats = %d\", nix->lf_rx_stats);\n+\tnix_dump(\" \\tlf_tx_stats = %d\", nix->lf_tx_stats);\n+\tnix_dump(\" \\trx_chan_cnt = %d\", nix->rx_chan_cnt);\n+\tnix_dump(\" \\ttx_chan_cnt = %d\", nix->tx_chan_cnt);\n+\tnix_dump(\" \\tcgx_links = %d\", nix->cgx_links);\n+\tnix_dump(\" \\tlbk_links = %d\", nix->lbk_links);\n+\tnix_dump(\" \\tsdp_links = %d\", nix->sdp_links);\n+\tnix_dump(\" \\ttx_link = %d\", nix->tx_link);\n+\tnix_dump(\" \\tsqb_size = %d\", nix->sqb_size);\n+\tnix_dump(\" \\tmsixoff = %d\", nix->msixoff);\n+\tnix_dump(\" \\tcints = %d\", nix->cints);\n+\tnix_dump(\" \\tqints = %d\", nix->qints);\n+\tnix_dump(\" \\tsdp_link = %d\", nix->sdp_link);\n+\tnix_dump(\" \\tptp_en = %d\", nix->ptp_en);\n+\tnix_dump(\" \\trss_alg_idx = %d\", nix->rss_alg_idx);\n+\tnix_dump(\" \\ttx_pause = %d\", nix->tx_pause);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c\nindex 79f25b0..32be64a 100644\n--- a/drivers/common/cnxk/roc_nix_irq.c\n+++ b/drivers/common/cnxk/roc_nix_irq.c\n@@ -74,6 +74,9 @@ nix_lf_err_irq(void *param)\n \n \t/* Clear interrupt */\n \tplt_write64(intr, nix->base + NIX_LF_ERR_INT);\n+\t/* Dump registers to std out */\n+\troc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);\n+\troc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));\n }\n \n static int\n@@ -119,6 +122,10 @@ nix_lf_ras_irq(void *param)\n \tplt_err(\"Ras_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n \t/* Clear interrupt */\n \tplt_write64(intr, nix->base + NIX_LF_RAS);\n+\n+\t/* Dump registers to std out */\n+\troc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);\n+\troc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));\n }\n \n static int\n@@ -279,6 +286,10 @@ nix_lf_q_irq(void *param)\n \n \t/* Clear interrupt */\n \tplt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));\n+\n+\t/* Dump registers to std out */\n+\troc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);\n+\troc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));\n }\n \n int\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 85b8393..05f4314 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -13,10 +13,13 @@ INTERNAL {\n \troc_idev_npa_nix_get;\n \troc_idev_num_lmtlines_get;\n \troc_model;\n+\troc_nix_cq_dump;\n \troc_nix_cq_fini;\n \troc_nix_cq_init;\n+\troc_nix_cqe_dump;\n \troc_nix_dev_fini;\n \troc_nix_dev_init;\n+\troc_nix_dump;\n \troc_nix_err_intr_ena_dis;\n \troc_nix_get_base_chan;\n \troc_nix_get_pf;\n@@ -30,6 +33,8 @@ INTERNAL {\n \troc_nix_lf_alloc;\n \troc_nix_lf_inl_ipsec_cfg;\n \troc_nix_lf_free;\n+\troc_nix_lf_get_reg_count;\n+\troc_nix_lf_reg_dump;\n \troc_nix_mac_addr_add;\n \troc_nix_mac_addr_del;\n \troc_nix_mac_addr_set;\n@@ -61,9 +66,11 @@ INTERNAL {\n \troc_nix_ptp_rx_ena_dis;\n \troc_nix_ptp_sync_time_adjust;\n \troc_nix_ptp_tx_ena_dis;\n+\troc_nix_queues_ctx_dump;\n \troc_nix_ras_intr_ena_dis;\n \troc_nix_register_cq_irqs;\n \troc_nix_register_queue_irqs;\n+\troc_nix_rq_dump;\n \troc_nix_rq_ena_dis;\n \troc_nix_rq_fini;\n \troc_nix_rq_init;\n@@ -77,6 +84,7 @@ INTERNAL {\n \troc_nix_rss_reta_set;\n \troc_nix_rx_queue_intr_disable;\n \troc_nix_rx_queue_intr_enable;\n+\troc_nix_sq_dump;\n \troc_nix_sq_fini;\n \troc_nix_sq_init;\n \troc_nix_stats_get;\n", "prefixes": [ "v3", "28/52" ] }