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GET /api/patches/90321/?format=api
{ "id": 90321, "url": "https://patches.dpdk.org/api/patches/90321/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-33-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401094739.22714-33-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401094739.22714-33-ndabilpuram@marvell.com", "date": "2021-04-01T09:47:19", "name": "[v2,32/52] common/cnxk: add nix traffic management base support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c2e85532bad022a57fc26c9364e8c9a0118102ed", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-33-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16050, "url": "https://patches.dpdk.org/api/series/16050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16050", "date": "2021-04-01T09:46:47", "name": "Add Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/16050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90321/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/90321/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DF3BCA0548;\n\tThu, 1 Apr 2021 11:52:27 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CE4B6140E7E;\n\tThu, 1 Apr 2021 11:49:46 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id B910A140EB5\n for <dev@dpdk.org>; Thu, 1 Apr 2021 11:49:44 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1319fAG5031137 for <dev@dpdk.org>; Thu, 1 Apr 2021 02:49:44 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 37n28jhw9u-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 02:49:44 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 02:49:41 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 02:49:41 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id F1BEA3F7040;\n Thu, 1 Apr 2021 02:49:38 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=yIBrU7qvnih1RMCVafztD3JkUwXjjV+n6ReDBidrWJM=;\n b=PT9S6XUUub70q9tlXV6oXa10pJ4cuJ8lkxl1rooLG7ac0zUHitWPYO52EyltMWkIsshh\n h44+MyLmYxxAzbA0vTuOyjcwau77W0gt1CVyVpvmdtD057AALs5BFzIvNTfnI6Nxlwud\n gGI7Zg4liSg/gUbHvZ5a+tsRBMFZ73SKjoyvSM4+bNE32CcWV4EhxRT+ncw4is0kXwA4\n YO9M9MYZnRDWX0VyhdaxRWfWrZaPAOHH8JYHFlLYS08jMn18mPcD5cX/5H3j9LrY5JK9\n YvSViqSppB7TpI+rasbdf4nm8dYVNiRdr7DJxRab0CVMAsasmKwu7PTRZwLluGi1XrdU /A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>", "Date": "Thu, 1 Apr 2021 15:17:19 +0530", "Message-ID": "<20210401094739.22714-33-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401094739.22714-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401094739.22714-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "K6EiPaPkPxnVaSEp7CTO6sHBusFbKNQV", "X-Proofpoint-ORIG-GUID": "K6EiPaPkPxnVaSEp7CTO6sHBusFbKNQV", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_04:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 32/52] common/cnxk: add nix traffic management\n base support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add nix traffic management base support to init/fini node, shaper profile\nand topology, setup SQ for a given user hierarchy or default internal\nhierarchy.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/meson.build | 3 +\n drivers/common/cnxk/roc_nix.c | 7 +\n drivers/common/cnxk/roc_nix.h | 26 +++\n drivers/common/cnxk/roc_nix_priv.h | 219 ++++++++++++++++++\n drivers/common/cnxk/roc_nix_queue.c | 9 +\n drivers/common/cnxk/roc_nix_tm.c | 397 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_tm_ops.c | 67 ++++++\n drivers/common/cnxk/roc_nix_tm_utils.c | 62 +++++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/version.map | 3 +\n 11 files changed, 796 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix_tm.c\n create mode 100644 drivers/common/cnxk/roc_nix_tm_ops.c\n create mode 100644 drivers/common/cnxk/roc_nix_tm_utils.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 7e742de..f1c2109 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -33,6 +33,9 @@ sources = files('roc_dev.c',\n \t\t'roc_nix_queue.c',\n \t\t'roc_nix_rss.c',\n \t\t'roc_nix_stats.c',\n+\t\t'roc_nix_tm.c',\n+\t\t'roc_nix_tm_ops.c',\n+\t\t'roc_nix_tm_utils.c',\n \t\t'roc_nix_vlan.c',\n \t\t'roc_npa.c',\n \t\t'roc_npa_debug.c',\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nindex 0621976..d6b288f 100644\n--- a/drivers/common/cnxk/roc_nix.c\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -396,11 +396,17 @@ roc_nix_dev_init(struct roc_nix *roc_nix)\n \tif (rc)\n \t\tgoto lf_detach;\n \n+\trc = nix_tm_conf_init(roc_nix);\n+\tif (rc)\n+\t\tgoto unregister_irqs;\n+\n \t/* Get NIX HW info */\n \troc_nix_get_hw_info(roc_nix);\n \tnix->dev.drv_inited = true;\n \n \treturn 0;\n+unregister_irqs:\n+\tnix_unregister_irqs(nix);\n lf_detach:\n \tnix_lf_detach(nix);\n dev_fini:\n@@ -421,6 +427,7 @@ roc_nix_dev_fini(struct roc_nix *roc_nix)\n \tif (!nix->dev.drv_inited)\n \t\tgoto fini;\n \n+\tnix_tm_conf_fini(roc_nix);\n \tnix_unregister_irqs(nix);\n \n \trc = nix_lf_detach(nix);\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex ce8c252..1ad0e72 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -305,6 +305,32 @@ void __roc_api roc_nix_unregister_queue_irqs(struct roc_nix *roc_nix);\n int __roc_api roc_nix_register_cq_irqs(struct roc_nix *roc_nix);\n void __roc_api roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix);\n \n+/* Traffic Management */\n+#define ROC_NIX_TM_MAX_SCHED_WT\t ((uint8_t)~0)\n+\n+enum roc_nix_tm_tree {\n+\tROC_NIX_TM_DEFAULT = 0,\n+\tROC_NIX_TM_RLIMIT,\n+\tROC_NIX_TM_USER,\n+\tROC_NIX_TM_TREE_MAX,\n+};\n+\n+enum roc_tm_node_level {\n+\tROC_TM_LVL_ROOT = 0,\n+\tROC_TM_LVL_SCH1,\n+\tROC_TM_LVL_SCH2,\n+\tROC_TM_LVL_SCH3,\n+\tROC_TM_LVL_SCH4,\n+\tROC_TM_LVL_QUEUE,\n+\tROC_TM_LVL_MAX,\n+};\n+\n+/*\n+ * TM runtime hierarchy init API.\n+ */\n+int __roc_api roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable);\n+int __roc_api roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq);\n+\n /* MAC */\n int __roc_api roc_nix_mac_rxtx_start_stop(struct roc_nix *roc_nix, bool start);\n int __roc_api roc_nix_mac_link_event_start_stop(struct roc_nix *roc_nix,\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 202bc76..edc3ff1 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -28,6 +28,77 @@ struct nix_qint {\n \tuint8_t qintx;\n };\n \n+/* Traffic Manager */\n+#define NIX_TM_MAX_HW_TXSCHQ 512\n+#define NIX_TM_HW_ID_INVALID UINT32_MAX\n+\n+/* TM flags */\n+#define NIX_TM_HIERARCHY_ENA BIT_ULL(0)\n+#define NIX_TM_TL1_NO_SP BIT_ULL(1)\n+#define NIX_TM_TL1_ACCESS BIT_ULL(2)\n+\n+struct nix_tm_tb {\n+\t/** Token bucket rate (bytes per second) */\n+\tuint64_t rate;\n+\n+\t/** Token bucket size (bytes), a.k.a. max burst size */\n+\tuint64_t size;\n+};\n+\n+struct nix_tm_node {\n+\tTAILQ_ENTRY(nix_tm_node) node;\n+\n+\t/* Input params */\n+\tenum roc_nix_tm_tree tree;\n+\tuint32_t id;\n+\tuint32_t priority;\n+\tuint32_t weight;\n+\tuint16_t lvl;\n+\tuint32_t parent_id;\n+\tuint32_t shaper_profile_id;\n+\tvoid (*free_fn)(void *node);\n+\n+\t/* Derived params */\n+\tuint32_t hw_id;\n+\tuint16_t hw_lvl;\n+\tuint32_t rr_prio;\n+\tuint32_t rr_num;\n+\tuint32_t max_prio;\n+\tuint32_t parent_hw_id;\n+\tuint32_t flags : 16;\n+#define NIX_TM_NODE_HWRES BIT_ULL(0)\n+#define NIX_TM_NODE_ENABLED BIT_ULL(1)\n+\t/* Shaper algorithm for RED state @NIX_REDALG_E */\n+\tuint32_t red_algo : 2;\n+\tuint32_t pkt_mode : 1;\n+\tuint32_t pkt_mode_set : 1;\n+\n+\tbool child_realloc;\n+\tstruct nix_tm_node *parent;\n+\n+\t/* Non-leaf node sp count */\n+\tuint32_t n_sp_priorities;\n+\n+\t/* Last stats */\n+\tuint64_t last_pkts;\n+\tuint64_t last_bytes;\n+};\n+\n+struct nix_tm_shaper_profile {\n+\tTAILQ_ENTRY(nix_tm_shaper_profile) shaper;\n+\tstruct nix_tm_tb commit;\n+\tstruct nix_tm_tb peak;\n+\tint32_t pkt_len_adj;\n+\tbool pkt_mode;\n+\tuint32_t id;\n+\tvoid (*free_fn)(void *profile);\n+\n+\tuint32_t ref_cnt;\n+};\n+\n+TAILQ_HEAD(nix_tm_node_list, nix_tm_node);\n+TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);\n+\n struct nix {\n \tuint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];\n \tenum roc_nix_rss_reta_sz reta_sz;\n@@ -73,6 +144,23 @@ struct nix {\n \tbool ptp_en;\n \tbool is_nix1;\n \n+\t/* Traffic manager info */\n+\n+\t/* Contiguous resources per lvl */\n+\tstruct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];\n+\t/* Dis-contiguous resources per lvl */\n+\tstruct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];\n+\tvoid *schq_bmp_mem;\n+\n+\tstruct nix_tm_shaper_profile_list shaper_profile_list;\n+\tstruct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];\n+\tenum roc_nix_tm_tree tm_tree;\n+\tuint64_t tm_rate_min;\n+\tuint16_t tm_root_lvl;\n+\tuint16_t tm_flags;\n+\tuint16_t tm_link_cfg_lvl;\n+\tuint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];\n+\tuint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];\n } __plt_cache_aligned;\n \n enum nix_err_status {\n@@ -84,6 +172,29 @@ enum nix_err_status {\n \tNIX_ERR_QUEUE_INVALID_RANGE,\n \tNIX_ERR_AQ_READ_FAILED,\n \tNIX_ERR_AQ_WRITE_FAILED,\n+\tNIX_ERR_TM_LEAF_NODE_GET,\n+\tNIX_ERR_TM_INVALID_LVL,\n+\tNIX_ERR_TM_INVALID_PRIO,\n+\tNIX_ERR_TM_INVALID_PARENT,\n+\tNIX_ERR_TM_NODE_EXISTS,\n+\tNIX_ERR_TM_INVALID_NODE,\n+\tNIX_ERR_TM_INVALID_SHAPER_PROFILE,\n+\tNIX_ERR_TM_PKT_MODE_MISMATCH,\n+\tNIX_ERR_TM_WEIGHT_EXCEED,\n+\tNIX_ERR_TM_CHILD_EXISTS,\n+\tNIX_ERR_TM_INVALID_PEAK_SZ,\n+\tNIX_ERR_TM_INVALID_PEAK_RATE,\n+\tNIX_ERR_TM_INVALID_COMMIT_SZ,\n+\tNIX_ERR_TM_INVALID_COMMIT_RATE,\n+\tNIX_ERR_TM_SHAPER_PROFILE_IN_USE,\n+\tNIX_ERR_TM_SHAPER_PROFILE_EXISTS,\n+\tNIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,\n+\tNIX_ERR_TM_INVALID_TREE,\n+\tNIX_ERR_TM_PARENT_PRIO_UPDATE,\n+\tNIX_ERR_TM_PRIO_EXCEEDED,\n+\tNIX_ERR_TM_PRIO_ORDER,\n+\tNIX_ERR_TM_MULTIPLE_RR_GROUPS,\n+\tNIX_ERR_TM_SQ_UPDATE_FAIL,\n \tNIX_ERR_NDC_SYNC,\n };\n \n@@ -117,4 +228,112 @@ nix_priv_to_roc_nix(struct nix *nix)\n int nix_register_irqs(struct nix *nix);\n void nix_unregister_irqs(struct nix *nix);\n \n+/* TM */\n+#define NIX_TM_TREE_MASK_ALL \\\n+\t(BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \\\n+\t BIT(ROC_NIX_TM_USER))\n+\n+/* NIX_MAX_HW_FRS ==\n+ * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT\n+ */\n+#define NIX_TM_DFLT_RR_WT 71\n+\n+/* Default TL1 priority and Quantum from AF */\n+#define NIX_TM_TL1_DFLT_RR_QTM\t((1 << 24) - 1)\n+#define NIX_TM_TL1_DFLT_RR_PRIO 1\n+\n+struct nix_tm_shaper_data {\n+\tuint64_t burst_exponent;\n+\tuint64_t burst_mantissa;\n+\tuint64_t div_exp;\n+\tuint64_t exponent;\n+\tuint64_t mantissa;\n+\tuint64_t burst;\n+\tuint64_t rate;\n+};\n+\n+static inline uint64_t\n+nix_tm_weight_to_rr_quantum(uint64_t weight)\n+{\n+\tuint64_t max = (roc_model_is_cn9k() ? NIX_CN9K_TM_RR_QUANTUM_MAX :\n+\t\t\t\t\t\t NIX_TM_RR_QUANTUM_MAX);\n+\n+\tweight &= (uint64_t)ROC_NIX_TM_MAX_SCHED_WT;\n+\treturn (weight * max) / ROC_NIX_TM_MAX_SCHED_WT;\n+}\n+\n+static inline bool\n+nix_tm_have_tl1_access(struct nix *nix)\n+{\n+\treturn !!(nix->tm_flags & NIX_TM_TL1_ACCESS);\n+}\n+\n+static inline bool\n+nix_tm_is_leaf(struct nix *nix, int lvl)\n+{\n+\tif (nix_tm_have_tl1_access(nix))\n+\t\treturn (lvl == ROC_TM_LVL_QUEUE);\n+\treturn (lvl == ROC_TM_LVL_SCH4);\n+}\n+\n+static inline struct nix_tm_node_list *\n+nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)\n+{\n+\treturn &nix->trees[tree];\n+}\n+\n+static inline const char *\n+nix_tm_hwlvl2str(uint32_t hw_lvl)\n+{\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_MDQ:\n+\t\treturn \"SMQ/MDQ\";\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treturn \"TL4\";\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treturn \"TL3\";\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treturn \"TL2\";\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\treturn \"TL1\";\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn \"???\";\n+}\n+\n+static inline const char *\n+nix_tm_tree2str(enum roc_nix_tm_tree tree)\n+{\n+\tif (tree == ROC_NIX_TM_DEFAULT)\n+\t\treturn \"Default Tree\";\n+\telse if (tree == ROC_NIX_TM_RLIMIT)\n+\t\treturn \"Rate Limit Tree\";\n+\telse if (tree == ROC_NIX_TM_USER)\n+\t\treturn \"User Tree\";\n+\treturn \"???\";\n+}\n+\n+/*\n+ * TM priv ops.\n+ */\n+\n+int nix_tm_conf_init(struct roc_nix *roc_nix);\n+void nix_tm_conf_fini(struct roc_nix *roc_nix);\n+int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,\n+\t\t\t uint16_t *smq);\n+int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);\n+int nix_tm_sq_flush_post(struct roc_nix_sq *sq);\n+int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);\n+int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);\n+\n+/*\n+ * TM priv utils.\n+ */\n+struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,\n+\t\t\t\t enum roc_nix_tm_tree tree);\n+uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n+\t\t\t volatile uint64_t *reg, volatile uint64_t *regval);\n+\n #endif /* _ROC_NIX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex c5287a9..fbf7efa 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -788,6 +788,12 @@ roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \tif (rc)\n \t\tgoto nomem;\n \n+\trc = nix_tm_leaf_data_get(nix, sq->qid, &rr_quantum, &smq);\n+\tif (rc) {\n+\t\trc = NIX_ERR_TM_LEAF_NODE_GET;\n+\t\tgoto nomem;\n+\t}\n+\n \t/* Init SQ context */\n \tif (roc_model_is_cn9k())\n \t\tsq_cn9k_init(nix, sq, rr_quantum, smq);\n@@ -831,6 +837,8 @@ roc_nix_sq_fini(struct roc_nix_sq *sq)\n \n \tqid = sq->qid;\n \n+\trc = nix_tm_sq_flush_pre(sq);\n+\n \t/* Release SQ context */\n \tif (roc_model_is_cn9k())\n \t\trc |= sq_cn9k_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);\n@@ -845,6 +853,7 @@ roc_nix_sq_fini(struct roc_nix_sq *sq)\n \tif (mbox_process(mbox))\n \t\trc |= NIX_ERR_NDC_SYNC;\n \n+\trc |= nix_tm_sq_flush_post(sq);\n \trc |= roc_npa_pool_destroy(sq->aura_handle);\n \tplt_free(sq->fc);\n \tplt_free(sq->sqe_mem);\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nnew file mode 100644\nindex 0000000..4cafc0f\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -0,0 +1,397 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+\n+int\n+nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txschq_config *req;\n+\tstruct nix_tm_node *p;\n+\tint rc;\n+\n+\t/* Enable nodes in path for flush to succeed */\n+\tif (!nix_tm_is_leaf(nix, node->lvl))\n+\t\tp = node;\n+\telse\n+\t\tp = node->parent;\n+\twhile (p) {\n+\t\tif (!(p->flags & NIX_TM_NODE_ENABLED) &&\n+\t\t (p->flags & NIX_TM_NODE_HWRES)) {\n+\t\t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\t\treq->lvl = p->hw_lvl;\n+\t\t\treq->num_regs = nix_tm_sw_xoff_prep(p, false, req->reg,\n+\t\t\t\t\t\t\t req->regval);\n+\t\t\trc = mbox_process(mbox);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\n+\t\t\tp->flags |= NIX_TM_NODE_ENABLED;\n+\t\t}\n+\t\tp = p->parent;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_txschq_config *req;\n+\tuint16_t smq;\n+\tint rc;\n+\n+\tsmq = node->hw_id;\n+\tplt_tm_dbg(\"Setting SMQ %u XOFF/FLUSH to %s\", smq,\n+\t\t enable ? \"enable\" : \"disable\");\n+\n+\trc = nix_tm_clear_path_xoff(nix, node);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = NIX_TXSCH_LVL_SMQ;\n+\treq->num_regs = 1;\n+\n+\treq->reg[0] = NIX_AF_SMQX_CFG(smq);\n+\treq->regval[0] = enable ? (BIT_ULL(50) | BIT_ULL(49)) : 0;\n+\treq->regval_mask[0] =\n+\t\tenable ? ~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+int\n+nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,\n+\t\t uint16_t *smq)\n+{\n+\tstruct nix_tm_node *node;\n+\tint rc;\n+\n+\tnode = nix_tm_node_search(nix, sq, nix->tm_tree);\n+\n+\t/* Check if we found a valid leaf node */\n+\tif (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||\n+\t node->parent->hw_id == NIX_TM_HW_ID_INVALID) {\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Get SMQ Id of leaf node's parent */\n+\t*smq = node->parent->hw_id;\n+\t*rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);\n+\n+\trc = nix_tm_smq_xoff(nix, node->parent, false);\n+\tif (rc)\n+\t\treturn rc;\n+\tnode->flags |= NIX_TM_NODE_ENABLED;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(sq->roc_nix);\n+\tuint16_t sqb_cnt, head_off, tail_off;\n+\tuint64_t wdata, val, prev;\n+\tuint16_t qid = sq->qid;\n+\tint64_t *regaddr;\n+\tuint64_t timeout; /* 10's of usec */\n+\n+\t/* Wait for enough time based on shaper min rate */\n+\ttimeout = (sq->nb_desc * roc_nix_max_pkt_len(sq->roc_nix) * 8 * 1E5);\n+\t/* Wait for worst case scenario of this SQ being last priority\n+\t * and so have to wait for all other SQ's drain out by their own.\n+\t */\n+\ttimeout = timeout * nix->nb_tx_queues;\n+\ttimeout = timeout / nix->tm_rate_min;\n+\tif (!timeout)\n+\t\ttimeout = 10000;\n+\n+\twdata = ((uint64_t)qid << 32);\n+\tregaddr = (int64_t *)(nix->base + NIX_LF_SQ_OP_STATUS);\n+\tval = roc_atomic64_add_nosync(wdata, regaddr);\n+\n+\t/* Spin multiple iterations as \"sq->fc_cache_pkts\" can still\n+\t * have space to send pkts even though fc_mem is disabled\n+\t */\n+\n+\twhile (true) {\n+\t\tprev = val;\n+\t\tplt_delay_us(10);\n+\t\tval = roc_atomic64_add_nosync(wdata, regaddr);\n+\t\t/* Continue on error */\n+\t\tif (val & BIT_ULL(63))\n+\t\t\tcontinue;\n+\n+\t\tif (prev != val)\n+\t\t\tcontinue;\n+\n+\t\tsqb_cnt = val & 0xFFFF;\n+\t\thead_off = (val >> 20) & 0x3F;\n+\t\ttail_off = (val >> 28) & 0x3F;\n+\n+\t\t/* SQ reached quiescent state */\n+\t\tif (sqb_cnt <= 1 && head_off == tail_off &&\n+\t\t (*(volatile uint64_t *)sq->fc == sq->nb_sqb_bufs)) {\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Timeout */\n+\t\tif (!timeout)\n+\t\t\tgoto exit;\n+\t\ttimeout--;\n+\t}\n+\n+\treturn 0;\n+exit:\n+\troc_nix_queues_ctx_dump(sq->roc_nix);\n+\treturn -EFAULT;\n+}\n+\n+/* Flush and disable tx queue and its parent SMQ */\n+int\n+nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n+{\n+\tstruct roc_nix *roc_nix = sq->roc_nix;\n+\tstruct nix_tm_node *node, *sibling;\n+\tstruct nix_tm_node_list *list;\n+\tenum roc_nix_tm_tree tree;\n+\tstruct mbox *mbox;\n+\tstruct nix *nix;\n+\tuint16_t qid;\n+\tint rc;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* Need not do anything if tree is in disabled state */\n+\tif (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))\n+\t\treturn 0;\n+\n+\tmbox = (&nix->dev)->mbox;\n+\tqid = sq->qid;\n+\n+\ttree = nix->tm_tree;\n+\tlist = nix_tm_node_list(nix, tree);\n+\n+\t/* Find the node for this SQ */\n+\tnode = nix_tm_node_search(nix, qid, tree);\n+\tif (!node || !(node->flags & NIX_TM_NODE_ENABLED)) {\n+\t\tplt_err(\"Invalid node/state for sq %u\", qid);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* Enable CGX RXTX to drain pkts */\n+\tif (!roc_nix->io_enabled) {\n+\t\t/* Though it enables both RX MCAM Entries and CGX Link\n+\t\t * we assume all the rx queues are stopped way back.\n+\t\t */\n+\t\tmbox_alloc_msg_nix_lf_start_rx(mbox);\n+\t\trc = mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"cgx start failed, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\t/* Disable smq xoff for case it was enabled earlier */\n+\trc = nix_tm_smq_xoff(nix, node->parent, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to enable smq %u, rc=%d\", node->parent->hw_id,\n+\t\t\trc);\n+\t\treturn rc;\n+\t}\n+\n+\t/* As per HRM, to disable an SQ, all other SQ's\n+\t * that feed to same SMQ must be paused before SMQ flush.\n+\t */\n+\tTAILQ_FOREACH(sibling, list, node) {\n+\t\tif (sibling->parent != node->parent)\n+\t\t\tcontinue;\n+\t\tif (!(sibling->flags & NIX_TM_NODE_ENABLED))\n+\t\t\tcontinue;\n+\n+\t\tqid = sibling->id;\n+\t\tsq = nix->sqs[qid];\n+\t\tif (!sq)\n+\t\t\tcontinue;\n+\n+\t\trc = roc_nix_tm_sq_aura_fc(sq, false);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to disable sqb aura fc, rc=%d\", rc);\n+\t\t\tgoto cleanup;\n+\t\t}\n+\n+\t\t/* Wait for sq entries to be flushed */\n+\t\trc = roc_nix_tm_sq_flush_spin(sq);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to drain sq %u, rc=%d\\n\", sq->qid, rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\tnode->flags &= ~NIX_TM_NODE_ENABLED;\n+\n+\t/* Disable and flush */\n+\trc = nix_tm_smq_xoff(nix, node->parent, true);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to disable smq %u, rc=%d\", node->parent->hw_id,\n+\t\t\trc);\n+\t\tgoto cleanup;\n+\t}\n+cleanup:\n+\t/* Restore cgx state */\n+\tif (!roc_nix->io_enabled) {\n+\t\tmbox_alloc_msg_nix_lf_stop_rx(mbox);\n+\t\trc |= mbox_process(mbox);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+nix_tm_sq_flush_post(struct roc_nix_sq *sq)\n+{\n+\tstruct roc_nix *roc_nix = sq->roc_nix;\n+\tstruct nix_tm_node *node, *sibling;\n+\tstruct nix_tm_node_list *list;\n+\tenum roc_nix_tm_tree tree;\n+\tstruct roc_nix_sq *s_sq;\n+\tbool once = false;\n+\tuint16_t qid, s_qid;\n+\tstruct nix *nix;\n+\tint rc;\n+\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\n+\t/* Need not do anything if tree is in disabled state */\n+\tif (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))\n+\t\treturn 0;\n+\n+\tqid = sq->qid;\n+\ttree = nix->tm_tree;\n+\tlist = nix_tm_node_list(nix, tree);\n+\n+\t/* Find the node for this SQ */\n+\tnode = nix_tm_node_search(nix, qid, tree);\n+\tif (!node) {\n+\t\tplt_err(\"Invalid node for sq %u\", qid);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* Enable all the siblings back */\n+\tTAILQ_FOREACH(sibling, list, node) {\n+\t\tif (sibling->parent != node->parent)\n+\t\t\tcontinue;\n+\n+\t\tif (sibling->id == qid)\n+\t\t\tcontinue;\n+\n+\t\tif (!(sibling->flags & NIX_TM_NODE_ENABLED))\n+\t\t\tcontinue;\n+\n+\t\ts_qid = sibling->id;\n+\t\ts_sq = nix->sqs[s_qid];\n+\t\tif (!s_sq)\n+\t\t\tcontinue;\n+\n+\t\tif (!once) {\n+\t\t\t/* Enable back if any SQ is still present */\n+\t\t\trc = nix_tm_smq_xoff(nix, node->parent, false);\n+\t\t\tif (rc) {\n+\t\t\t\tplt_err(\"Failed to enable smq %u, rc=%d\",\n+\t\t\t\t\tnode->parent->hw_id, rc);\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t\tonce = true;\n+\t\t}\n+\n+\t\trc = roc_nix_tm_sq_aura_fc(s_sq, true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to enable sqb aura fc, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+nix_tm_conf_init(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint32_t bmp_sz, hw_lvl;\n+\tvoid *bmp_mem;\n+\tint rc, i;\n+\n+\tnix->tm_flags = 0;\n+\tfor (i = 0; i < ROC_NIX_TM_TREE_MAX; i++)\n+\t\tTAILQ_INIT(&nix->trees[i]);\n+\n+\tTAILQ_INIT(&nix->shaper_profile_list);\n+\tnix->tm_rate_min = 1E9; /* 1Gbps */\n+\n+\trc = -ENOMEM;\n+\tbmp_sz = plt_bitmap_get_memory_footprint(NIX_TM_MAX_HW_TXSCHQ);\n+\tbmp_mem = plt_zmalloc(bmp_sz * NIX_TXSCH_LVL_CNT * 2, 0);\n+\tif (!bmp_mem)\n+\t\treturn rc;\n+\tnix->schq_bmp_mem = bmp_mem;\n+\n+\t/* Init contiguous and discontiguous bitmap per lvl */\n+\trc = -EIO;\n+\tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\t/* Bitmap for discontiguous resource */\n+\t\tnix->schq_bmp[hw_lvl] =\n+\t\t\tplt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);\n+\t\tif (!nix->schq_bmp[hw_lvl])\n+\t\t\tgoto exit;\n+\n+\t\tbmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);\n+\n+\t\t/* Bitmap for contiguous resource */\n+\t\tnix->schq_contig_bmp[hw_lvl] =\n+\t\t\tplt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);\n+\t\tif (!nix->schq_contig_bmp[hw_lvl])\n+\t\t\tgoto exit;\n+\n+\t\tbmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);\n+\t}\n+\n+\t/* Disable TL1 Static Priority when VF's are enabled\n+\t * as otherwise VF's TL2 reallocation will be needed\n+\t * runtime to support a specific topology of PF.\n+\t */\n+\tif (nix->pci_dev->max_vfs)\n+\t\tnix->tm_flags |= NIX_TM_TL1_NO_SP;\n+\n+\t/* TL1 access is only for PF's */\n+\tif (roc_nix_is_pf(roc_nix)) {\n+\t\tnix->tm_flags |= NIX_TM_TL1_ACCESS;\n+\t\tnix->tm_root_lvl = NIX_TXSCH_LVL_TL1;\n+\t} else {\n+\t\tnix->tm_root_lvl = NIX_TXSCH_LVL_TL2;\n+\t}\n+\n+\treturn 0;\n+exit:\n+\tnix_tm_conf_fini(roc_nix);\n+\treturn rc;\n+}\n+\n+void\n+nix_tm_conf_fini(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tuint16_t hw_lvl;\n+\n+\tfor (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tplt_bitmap_free(nix->schq_bmp[hw_lvl]);\n+\t\tplt_bitmap_free(nix->schq_contig_bmp[hw_lvl]);\n+\t}\n+\tplt_free(nix->schq_bmp_mem);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c\nnew file mode 100644\nindex 0000000..e2b6d02\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_tm_ops.c\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+roc_nix_tm_sq_aura_fc(struct roc_nix_sq *sq, bool enable)\n+{\n+\tstruct npa_aq_enq_req *req;\n+\tstruct npa_aq_enq_rsp *rsp;\n+\tuint64_t aura_handle;\n+\tstruct npa_lf *lf;\n+\tstruct mbox *mbox;\n+\tint rc = -ENOSPC;\n+\n+\tplt_tm_dbg(\"Setting SQ %u SQB aura FC to %s\", sq->qid,\n+\t\t enable ? \"enable\" : \"disable\");\n+\n+\tlf = idev_npa_obj_get();\n+\tif (!lf)\n+\t\treturn NPA_ERR_DEVICE_NOT_BOUNDED;\n+\n+\tmbox = lf->mbox;\n+\t/* Set/clear sqb aura fc_ena */\n+\taura_handle = sq->aura_handle;\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\n+\treq->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n+\treq->ctype = NPA_AQ_CTYPE_AURA;\n+\treq->op = NPA_AQ_INSTOP_WRITE;\n+\t/* Below is not needed for aura writes but AF driver needs it */\n+\t/* AF will translate to associated poolctx */\n+\treq->aura.pool_addr = req->aura_id;\n+\n+\treq->aura.fc_ena = enable;\n+\treq->aura_mask.fc_ena = 1;\n+\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Read back npa aura ctx */\n+\treq = mbox_alloc_msg_npa_aq_enq(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->aura_id = roc_npa_aura_handle_to_aura(aura_handle);\n+\treq->ctype = NPA_AQ_CTYPE_AURA;\n+\treq->op = NPA_AQ_INSTOP_READ;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Init when enabled as there might be no triggers */\n+\tif (enable)\n+\t\t*(volatile uint64_t *)sq->fc = rsp->aura.count;\n+\telse\n+\t\t*(volatile uint64_t *)sq->fc = sq->nb_sqb_bufs;\n+\t/* Sync write barrier */\n+\tplt_wmb();\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c\nnew file mode 100644\nindex 0000000..a3f683e\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_tm_utils.c\n@@ -0,0 +1,62 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+struct nix_tm_node *\n+nix_tm_node_search(struct nix *nix, uint32_t node_id, enum roc_nix_tm_tree tree)\n+{\n+\tstruct nix_tm_node_list *list;\n+\tstruct nix_tm_node *node;\n+\n+\tlist = nix_tm_node_list(nix, tree);\n+\tTAILQ_FOREACH(node, list, node) {\n+\t\tif (node->id == node_id)\n+\t\t\treturn node;\n+\t}\n+\treturn NULL;\n+}\n+\n+uint8_t\n+nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,\n+\t\t volatile uint64_t *reg, volatile uint64_t *regval)\n+{\n+\tuint32_t hw_lvl = node->hw_lvl;\n+\tuint32_t schq = node->hw_id;\n+\tuint8_t k = 0;\n+\n+\tplt_tm_dbg(\"sw xoff config node %s(%u) lvl %u id %u, enable %u (%p)\",\n+\t\t nix_tm_hwlvl2str(hw_lvl), schq, node->lvl, node->id, enable,\n+\t\t node);\n+\n+\tregval[k] = enable;\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_MDQ:\n+\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n+\t\tk++;\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n+\t\tk++;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn k;\n+}\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 3ac81ce..4d61344 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -32,3 +32,4 @@ RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_tm, pmd.net.cnxk.tm, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 5e4976b..94bb3c7 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -136,6 +136,7 @@ extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n extern int cnxk_logtype_npa;\n extern int cnxk_logtype_nix;\n+extern int cnxk_logtype_tm;\n \n #define plt_err(fmt, args...) \\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n@@ -155,6 +156,7 @@ extern int cnxk_logtype_nix;\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n #define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n+#define plt_tm_dbg(fmt, ...)\tplt_dbg(tm, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev)\t\t\t\t\\\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 0f43354..5b99467 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -5,6 +5,7 @@ INTERNAL {\n \tcnxk_logtype_mbox;\n \tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n+\tcnxk_logtype_tm;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n@@ -103,6 +104,8 @@ INTERNAL {\n \troc_nix_xstats_names_get;\n \troc_nix_switch_hdr_set;\n \troc_nix_eeprom_info_get;\n+\troc_nix_tm_sq_aura_fc;\n+\troc_nix_tm_sq_flush_spin;\n \troc_nix_unregister_cq_irqs;\n \troc_nix_unregister_queue_irqs;\n \troc_nix_vlan_insert_ena_dis;\n", "prefixes": [ "v2", "32/52" ] }