Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/90306/?format=api
{ "id": 90306, "url": "https://patches.dpdk.org/api/patches/90306/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-18-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210401094739.22714-18-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210401094739.22714-18-ndabilpuram@marvell.com", "date": "2021-04-01T09:47:04", "name": "[v2,17/52] common/cnxk: add base nix support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "410036df5d46b73c535a8f25a22b060bd994efa4", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210401094739.22714-18-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 16050, "url": "https://patches.dpdk.org/api/series/16050/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=16050", "date": "2021-04-01T09:46:47", "name": "Add Marvell CNXK common driver", "version": 2, "mbox": "https://patches.dpdk.org/series/16050/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/90306/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/90306/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 697C8A0548;\n\tThu, 1 Apr 2021 11:50:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E45C140F46;\n\tThu, 1 Apr 2021 11:49:00 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 8E246140F45\n for <dev@dpdk.org>; Thu, 1 Apr 2021 11:48:58 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 1319f5PN014877 for <dev@dpdk.org>; Thu, 1 Apr 2021 02:48:57 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 37n28j1wtn-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 01 Apr 2021 02:48:57 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 1 Apr 2021 02:48:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 1 Apr 2021 02:48:56 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C1C623F703F;\n Thu, 1 Apr 2021 02:48:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=67ZE2Kpua8dn5Hv6Ea+PEZsKx2FrnaRxGvtK0gxnD1k=;\n b=DpqwUwY1Loe28gwLmNjUWRl2dS/F3Zbc3amsSbYIFNYiDbTcd1p6WzerAdkPiTS3gFgV\n keawWymLFTRCkRtobohodPqvgXgrS48/dLWXXlxoqXiIZ2MZyvbxecfaf0oJWtY6MBWn\n YxyIZ3Z2pu0z40eNGFYYZsYDeuELQv3Totwboac388KTsdH+xTjQxdud/oBVHIWYB1OO\n y+V++o8fTrBMBG73tobLIJ861LQkgFAjbsjS1sBhJTaQqpP1xrtAWQQuFEi+YfV2YRSQ\n oJaOU7FsmalFk3/IEGGHId4smerjUyMjBC3RII3nMD34qINIlWRzoUa5jooLdAC03Eez GQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<jerinj@marvell.com>, <skori@marvell.com>, <skoteshwar@marvell.com>,\n <pbhagavatula@marvell.com>, <kirankumark@marvell.com>,\n <psatheesh@marvell.com>, <asekhar@marvell.com>", "Date": "Thu, 1 Apr 2021 15:17:04 +0530", "Message-ID": "<20210401094739.22714-18-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210401094739.22714-1-ndabilpuram@marvell.com>", "References": "<20210305133918.8005-1-ndabilpuram@marvell.com>\n <20210401094739.22714-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "RH2e8RHpBn80Jt0GF2_dxQlvQ0QR4QBb", "X-Proofpoint-GUID": "RH2e8RHpBn80Jt0GF2_dxQlvQ0QR4QBb", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761\n definitions=2021-04-01_04:2021-03-31,\n 2021-04-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 17/52] common/cnxk: add base nix support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd base nix support as ROC(Rest of Chip) API which will\nbe used by generic ETHDEV PMD(net/cnxk).\n\nThis patch adds support to device init, fini, resource\nalloc and free API which sets up a ETHDEV PCI device of either\nCN9K or CN10K Marvell SoC.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_idev.c | 13 ++\n drivers/common/cnxk/roc_idev.h | 2 +\n drivers/common/cnxk/roc_nix.c | 396 +++++++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix.h | 84 ++++++++\n drivers/common/cnxk/roc_nix_priv.h | 100 ++++++++++\n drivers/common/cnxk/roc_platform.c | 1 +\n drivers/common/cnxk/roc_platform.h | 2 +\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/roc_utils.c | 42 ++++\n drivers/common/cnxk/version.map | 16 ++\n 12 files changed, 663 insertions(+)\n create mode 100644 drivers/common/cnxk/roc_nix.c\n create mode 100644 drivers/common/cnxk/roc_nix.h\n create mode 100644 drivers/common/cnxk/roc_nix_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 86ea9e8..bbf8720 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -21,6 +21,7 @@ sources = files('roc_dev.c',\n \t\t'roc_irq.c',\n \t\t'roc_mbox.c',\n \t\t'roc_model.c',\n+\t\t'roc_nix.c',\n \t\t'roc_npa.c',\n \t\t'roc_npa_debug.c',\n \t\t'roc_npa_irq.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 9289c68..718916d 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -82,6 +82,9 @@\n /* NPA */\n #include \"roc_npa.h\"\n \n+/* NIX */\n+#include \"roc_nix.h\"\n+\n /* Utils */\n #include \"roc_utils.h\"\n \ndiff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex bf9cce8..a92ac6a 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -142,3 +142,16 @@ roc_idev_num_lmtlines_get(void)\n \n \treturn num_lmtlines;\n }\n+\n+struct roc_nix *\n+roc_idev_npa_nix_get(void)\n+{\n+\tstruct npa_lf *npa_lf = idev_npa_obj_get();\n+\tstruct dev *dev;\n+\n+\tif (!npa_lf)\n+\t\treturn NULL;\n+\n+\tdev = container_of(npa_lf, struct dev, npa);\n+\treturn dev->roc_nix;\n+}\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex f267865..043e8af 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -12,4 +12,6 @@ void __roc_api roc_idev_npa_maxpools_set(uint32_t max_pools);\n uint64_t __roc_api roc_idev_lmt_base_addr_get(void);\n uint16_t __roc_api roc_idev_num_lmtlines_get(void);\n \n+struct roc_nix *__roc_api roc_idev_npa_nix_get(void);\n+\n #endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c\nnew file mode 100644\nindex 0000000..040f78c\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix.c\n@@ -0,0 +1,396 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+bool\n+roc_nix_is_lbk(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->lbk_link;\n+}\n+\n+int\n+roc_nix_get_base_chan(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->rx_chan_base;\n+}\n+\n+uint16_t\n+roc_nix_get_vwqe_interval(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->vwqe_interval;\n+}\n+\n+bool\n+roc_nix_is_sdp(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn nix->sdp_link;\n+}\n+\n+bool\n+roc_nix_is_pf(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn !dev_is_vf(&nix->dev);\n+}\n+\n+int\n+roc_nix_get_pf(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev_get_pf(dev->pf_func);\n+}\n+\n+int\n+roc_nix_get_vf(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev_get_vf(dev->pf_func);\n+}\n+\n+bool\n+roc_nix_is_vf_or_sdp(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\treturn (dev_is_vf(&nix->dev) != 0) || roc_nix_is_sdp(roc_nix);\n+}\n+\n+uint16_t\n+roc_nix_get_pf_func(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct dev *dev = &nix->dev;\n+\n+\treturn dev->pf_func;\n+}\n+\n+int\n+roc_nix_max_pkt_len(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\n+\tif (roc_model_is_cn9k())\n+\t\treturn NIX_CN9K_MAX_HW_FRS;\n+\n+\tif (nix->lbk_link || roc_nix_is_sdp(roc_nix))\n+\t\treturn NIX_LBK_MAX_HW_FRS;\n+\n+\treturn NIX_RPM_MAX_HW_FRS;\n+}\n+\n+int\n+roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq,\n+\t\t uint64_t rx_cfg)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_lf_alloc_req *req;\n+\tstruct nix_lf_alloc_rsp *rsp;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->rq_cnt = nb_rxq;\n+\treq->sq_cnt = nb_txq;\n+\treq->cq_cnt = nb_rxq;\n+\t/* XQESZ can be W64 or W16 */\n+\treq->xqe_sz = NIX_XQESZ_W16;\n+\treq->rss_sz = nix->reta_sz;\n+\treq->rss_grps = ROC_NIX_RSS_GRPS;\n+\treq->npa_func = idev_npa_pffunc_get();\n+\treq->rx_cfg = rx_cfg;\n+\n+\tif (!roc_nix->rss_tag_as_xor)\n+\t\treq->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;\n+\n+\trc = mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\tgoto fail;\n+\n+\tnix->sqb_size = rsp->sqb_size;\n+\tnix->tx_chan_base = rsp->tx_chan_base;\n+\tnix->rx_chan_base = rsp->rx_chan_base;\n+\tif (roc_nix_is_lbk(roc_nix) && roc_nix->enable_loop)\n+\t\tnix->tx_chan_base = rsp->rx_chan_base;\n+\tnix->rx_chan_cnt = rsp->rx_chan_cnt;\n+\tnix->tx_chan_cnt = rsp->tx_chan_cnt;\n+\tnix->lso_tsov4_idx = rsp->lso_tsov4_idx;\n+\tnix->lso_tsov6_idx = rsp->lso_tsov6_idx;\n+\tnix->lf_tx_stats = rsp->lf_tx_stats;\n+\tnix->lf_rx_stats = rsp->lf_rx_stats;\n+\tnix->cints = rsp->cints;\n+\troc_nix->cints = rsp->cints;\n+\tnix->qints = rsp->qints;\n+\tnix->ptp_en = rsp->hw_rx_tstamp_en;\n+\troc_nix->rx_ptp_ena = rsp->hw_rx_tstamp_en;\n+\tnix->cgx_links = rsp->cgx_links;\n+\tnix->lbk_links = rsp->lbk_links;\n+\tnix->sdp_links = rsp->sdp_links;\n+\tnix->tx_link = rsp->tx_link;\n+\tnix->nb_rx_queues = nb_rxq;\n+\tnix->nb_tx_queues = nb_txq;\n+\tnix->sqs = plt_zmalloc(sizeof(struct roc_nix_sq *) * nb_txq, 0);\n+\tif (!nix->sqs)\n+\t\treturn -ENOMEM;\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_lf_free(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_lf_free_req *req;\n+\tstruct ndc_sync_op *ndc_req;\n+\tint rc = -ENOSPC;\n+\n+\tplt_free(nix->sqs);\n+\tnix->sqs = NULL;\n+\n+\t/* Sync NDC-NIX for LF */\n+\tndc_req = mbox_alloc_msg_ndc_sync_op(mbox);\n+\tif (ndc_req == NULL)\n+\t\treturn rc;\n+\tndc_req->nix_lf_tx_sync = 1;\n+\tndc_req->nix_lf_rx_sync = 1;\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\tplt_err(\"Error on NDC-NIX-[TX, RX] LF sync, rc %d\", rc);\n+\n+\treq = mbox_alloc_msg_nix_lf_free(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\t/* Let AF driver free all this nix lf's\n+\t * NPC entries allocated using NPC MBOX.\n+\t */\n+\treq->flags = 0;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static inline int\n+nix_lf_attach(struct dev *dev)\n+{\n+\tstruct mbox *mbox = dev->mbox;\n+\tstruct rsrc_attach_req *req;\n+\tint rc = -ENOSPC;\n+\n+\t/* Attach NIX(lf) */\n+\treq = mbox_alloc_msg_attach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->modify = true;\n+\treq->nixlf = true;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static inline int\n+nix_lf_get_msix_offset(struct dev *dev, struct nix *nix)\n+{\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tstruct mbox *mbox = dev->mbox;\n+\tint rc;\n+\n+\t/* Get MSIX vector offsets */\n+\tmbox_alloc_msg_msix_offset(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&msix_rsp);\n+\tif (rc == 0)\n+\t\tnix->msixoff = msix_rsp->nix_msixoff;\n+\n+\treturn rc;\n+}\n+\n+static inline int\n+nix_lf_detach(struct nix *nix)\n+{\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct rsrc_detach_req *req;\n+\tint rc = -ENOSPC;\n+\n+\treq = mbox_alloc_msg_detach_resources(mbox);\n+\tif (req == NULL)\n+\t\treturn rc;\n+\treq->partial = true;\n+\treq->nixlf = true;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n+static int\n+roc_nix_get_hw_info(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct nix_hw_info *hw_info;\n+\tint rc;\n+\n+\tmbox_alloc_msg_nix_get_hw_info(mbox);\n+\trc = mbox_process_msg(mbox, (void *)&hw_info);\n+\tif (rc == 0)\n+\t\tnix->vwqe_interval = hw_info->vwqe_delay;\n+\n+\treturn rc;\n+}\n+\n+static void\n+sdp_lbk_id_update(struct plt_pci_device *pci_dev, struct nix *nix)\n+{\n+\tnix->sdp_link = false;\n+\tnix->lbk_link = false;\n+\n+\t/* Update SDP/LBK link based on PCI device id */\n+\tswitch (pci_dev->id.device_id) {\n+\tcase PCI_DEVID_CNXK_RVU_SDP_PF:\n+\tcase PCI_DEVID_CNXK_RVU_SDP_VF:\n+\t\tnix->sdp_link = true;\n+\t\tbreak;\n+\tcase PCI_DEVID_CNXK_RVU_AF_VF:\n+\t\tnix->lbk_link = true;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+static inline uint64_t\n+nix_get_blkaddr(struct dev *dev)\n+{\n+\tuint64_t reg;\n+\n+\t/* Reading the discovery register to know which NIX is the LF\n+\t * attached to.\n+\t */\n+\treg = plt_read64(dev->bar2 +\n+\t\t\t RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));\n+\n+\treturn reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;\n+}\n+\n+int\n+roc_nix_dev_init(struct roc_nix *roc_nix)\n+{\n+\tenum roc_nix_rss_reta_sz reta_sz;\n+\tstruct plt_pci_device *pci_dev;\n+\tuint16_t max_sqb_count;\n+\tuint64_t blkaddr;\n+\tstruct dev *dev;\n+\tstruct nix *nix;\n+\tint rc;\n+\n+\tif (roc_nix == NULL || roc_nix->pci_dev == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\treta_sz = roc_nix->reta_sz;\n+\tif (reta_sz != 0 && reta_sz != 64 && reta_sz != 128 && reta_sz != 256)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (reta_sz == 0)\n+\t\treta_sz = ROC_NIX_RSS_RETA_SZ_64;\n+\n+\tmax_sqb_count = roc_nix->max_sqb_count;\n+\tmax_sqb_count = PLT_MIN(max_sqb_count, NIX_MAX_SQB);\n+\tmax_sqb_count = PLT_MAX(max_sqb_count, NIX_MIN_SQB);\n+\troc_nix->max_sqb_count = max_sqb_count;\n+\n+\tPLT_STATIC_ASSERT(sizeof(struct nix) <= ROC_NIX_MEM_SZ);\n+\tnix = roc_nix_to_nix_priv(roc_nix);\n+\tpci_dev = roc_nix->pci_dev;\n+\tdev = &nix->dev;\n+\n+\tif (nix->dev.drv_inited)\n+\t\treturn 0;\n+\n+\tif (dev->mbox_active)\n+\t\tgoto skip_dev_init;\n+\n+\tmemset(nix, 0, sizeof(*nix));\n+\t/* Initialize device */\n+\trc = dev_init(dev, pci_dev);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to init roc device\");\n+\t\tgoto fail;\n+\t}\n+\n+skip_dev_init:\n+\tdev->roc_nix = roc_nix;\n+\n+\tnix->lmt_base = dev->lmt_base;\n+\t/* Expose base LMT line address for\n+\t * \"Per Core LMT line\" mode.\n+\t */\n+\troc_nix->lmt_base = dev->lmt_base;\n+\n+\t/* Attach NIX LF */\n+\trc = nix_lf_attach(dev);\n+\tif (rc)\n+\t\tgoto dev_fini;\n+\n+\tblkaddr = nix_get_blkaddr(dev);\n+\tnix->is_nix1 = (blkaddr == RVU_BLOCK_ADDR_NIX1);\n+\n+\t/* Calculating base address based on which NIX block LF\n+\t * is attached to.\n+\t */\n+\tnix->base = dev->bar2 + (blkaddr << 20);\n+\n+\t/* Get NIX MSIX offset */\n+\trc = nix_lf_get_msix_offset(dev, nix);\n+\tif (rc)\n+\t\tgoto lf_detach;\n+\n+\t/* Update nix context */\n+\tsdp_lbk_id_update(pci_dev, nix);\n+\tnix->pci_dev = pci_dev;\n+\tnix->reta_sz = reta_sz;\n+\tnix->mtu = ROC_NIX_DEFAULT_HW_FRS;\n+\n+\t/* Get NIX HW info */\n+\troc_nix_get_hw_info(roc_nix);\n+\tnix->dev.drv_inited = true;\n+\n+\treturn 0;\n+lf_detach:\n+\tnix_lf_detach(nix);\n+dev_fini:\n+\trc |= dev_fini(dev, pci_dev);\n+fail:\n+\treturn rc;\n+}\n+\n+int\n+roc_nix_dev_fini(struct roc_nix *roc_nix)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc = 0;\n+\n+\tif (nix == NULL)\n+\t\treturn NIX_ERR_PARAM;\n+\n+\tif (!nix->dev.drv_inited)\n+\t\tgoto fini;\n+\n+\trc = nix_lf_detach(nix);\n+\tnix->dev.drv_inited = false;\n+fini:\n+\trc |= dev_fini(&nix->dev, nix->pci_dev);\n+\treturn rc;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nnew file mode 100644\nindex 0000000..fc078f8\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_NIX_H_\n+#define _ROC_NIX_H_\n+\n+/* Constants */\n+enum roc_nix_rss_reta_sz {\n+\tROC_NIX_RSS_RETA_SZ_64 = 64,\n+\tROC_NIX_RSS_RETA_SZ_128 = 128,\n+\tROC_NIX_RSS_RETA_SZ_256 = 256,\n+};\n+\n+enum roc_nix_sq_max_sqe_sz {\n+\troc_nix_maxsqesz_w16 = NIX_MAXSQESZ_W16,\n+\troc_nix_maxsqesz_w8 = NIX_MAXSQESZ_W8,\n+};\n+\n+/* NIX LF RX offload configuration flags.\n+ * These are input flags to roc_nix_lf_alloc:rx_cfg\n+ */\n+#define ROC_NIX_LF_RX_CFG_DROP_RE BIT_ULL(32)\n+#define ROC_NIX_LF_RX_CFG_L2_LEN_ERR BIT_ULL(33)\n+#define ROC_NIX_LF_RX_CFG_IP6_UDP_OPT BIT_ULL(34)\n+#define ROC_NIX_LF_RX_CFG_DIS_APAD BIT_ULL(35)\n+#define ROC_NIX_LF_RX_CFG_CSUM_IL4 BIT_ULL(36)\n+#define ROC_NIX_LF_RX_CFG_CSUM_OL4 BIT_ULL(37)\n+#define ROC_NIX_LF_RX_CFG_LEN_IL4 BIT_ULL(38)\n+#define ROC_NIX_LF_RX_CFG_LEN_IL3 BIT_ULL(39)\n+#define ROC_NIX_LF_RX_CFG_LEN_OL4 BIT_ULL(40)\n+#define ROC_NIX_LF_RX_CFG_LEN_OL3 BIT_ULL(41)\n+\n+/* Group 0 will be used for RSS, 1 -7 will be used for npc_flow RSS action*/\n+#define ROC_NIX_RSS_GROUP_DEFAULT 0\n+#define ROC_NIX_RSS_GRPS\t 8\n+#define ROC_NIX_RSS_RETA_MAX\t ROC_NIX_RSS_RETA_SZ_256\n+#define ROC_NIX_RSS_KEY_LEN\t 48 /* 352 Bits */\n+\n+#define ROC_NIX_DEFAULT_HW_FRS 1514\n+\n+#define ROC_NIX_VWQE_MAX_SIZE_LOG2 11\n+#define ROC_NIX_VWQE_MIN_SIZE_LOG2 2\n+struct roc_nix {\n+\t/* Input parameters */\n+\tstruct plt_pci_device *pci_dev;\n+\tuint16_t port_id;\n+\tbool rss_tag_as_xor;\n+\tuint16_t max_sqb_count;\n+\tenum roc_nix_rss_reta_sz reta_sz;\n+\tbool enable_loop;\n+\t/* End of input parameters */\n+\t/* LMT line base for \"Per Core Tx LMT line\" mode*/\n+\tuintptr_t lmt_base;\n+\tbool io_enabled;\n+\tbool rx_ptp_ena;\n+\tuint16_t cints;\n+\n+#define ROC_NIX_MEM_SZ (6 * 1024)\n+\tuint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+/* Dev */\n+int __roc_api roc_nix_dev_init(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_dev_fini(struct roc_nix *roc_nix);\n+\n+/* Type */\n+bool __roc_api roc_nix_is_lbk(struct roc_nix *roc_nix);\n+bool __roc_api roc_nix_is_sdp(struct roc_nix *roc_nix);\n+bool __roc_api roc_nix_is_pf(struct roc_nix *roc_nix);\n+bool __roc_api roc_nix_is_vf_or_sdp(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_get_base_chan(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_get_pf(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_get_vf(struct roc_nix *roc_nix);\n+uint16_t __roc_api roc_nix_get_pf_func(struct roc_nix *roc_nix);\n+uint16_t __roc_api roc_nix_get_vwqe_interval(struct roc_nix *roc_nix);\n+int __roc_api roc_nix_max_pkt_len(struct roc_nix *roc_nix);\n+\n+/* LF ops */\n+int __roc_api roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq,\n+\t\t\t uint32_t nb_txq, uint64_t rx_cfg);\n+int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix);\n+\n+#endif /* _ROC_NIX_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nnew file mode 100644\nindex 0000000..92a0d2e\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -0,0 +1,100 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#ifndef _ROC_NIX_PRIV_H_\n+#define _ROC_NIX_PRIV_H_\n+\n+/* Constants */\n+#define NIX_CQ_ENTRY_SZ\t 128\n+#define NIX_CQ_ENTRY64_SZ 512\n+#define NIX_CQ_ALIGN\t (uint16_t)512\n+#define NIX_MAX_SQB\t (uint16_t)512\n+#define NIX_DEF_SQB\t (uint16_t)16\n+#define NIX_MIN_SQB\t (uint16_t)8\n+#define NIX_SQB_LIST_SPACE (uint16_t)2\n+#define NIX_SQB_LOWER_THRESH (uint16_t)70\n+\n+/* Apply BP/DROP when CQ is 95% full */\n+#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)\n+\n+struct nix {\n+\tuint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];\n+\tenum roc_nix_rss_reta_sz reta_sz;\n+\tstruct plt_pci_device *pci_dev;\n+\tuint16_t bpid[NIX_MAX_CHAN];\n+\tstruct roc_nix_sq **sqs;\n+\tuint16_t vwqe_interval;\n+\tuint16_t tx_chan_base;\n+\tuint16_t rx_chan_base;\n+\tuint16_t nb_rx_queues;\n+\tuint16_t nb_tx_queues;\n+\tuint8_t lso_tsov6_idx;\n+\tuint8_t lso_tsov4_idx;\n+\tuint8_t lf_rx_stats;\n+\tuint8_t lf_tx_stats;\n+\tuint8_t rx_chan_cnt;\n+\tuint8_t rss_alg_idx;\n+\tuint8_t tx_chan_cnt;\n+\tuintptr_t lmt_base;\n+\tuint8_t cgx_links;\n+\tuint8_t lbk_links;\n+\tuint8_t sdp_links;\n+\tuint8_t tx_link;\n+\tuint16_t sqb_size;\n+\t/* Without FCS, with L2 overhead */\n+\tuint16_t mtu;\n+\tuint16_t chan_cnt;\n+\tuint16_t msixoff;\n+\tuint8_t rx_pause;\n+\tuint8_t tx_pause;\n+\tstruct dev dev;\n+\tuint16_t cints;\n+\tuint16_t qints;\n+\tuintptr_t base;\n+\tbool sdp_link;\n+\tbool lbk_link;\n+\tbool ptp_en;\n+\tbool is_nix1;\n+\n+} __plt_cache_aligned;\n+\n+enum nix_err_status {\n+\tNIX_ERR_PARAM = -2048,\n+\tNIX_ERR_NO_MEM,\n+\tNIX_ERR_INVALID_RANGE,\n+\tNIX_ERR_INTERNAL,\n+\tNIX_ERR_OP_NOTSUP,\n+\tNIX_ERR_QUEUE_INVALID_RANGE,\n+\tNIX_ERR_AQ_READ_FAILED,\n+\tNIX_ERR_AQ_WRITE_FAILED,\n+\tNIX_ERR_NDC_SYNC,\n+};\n+\n+enum nix_q_size {\n+\tnix_q_size_16, /* 16 entries */\n+\tnix_q_size_64, /* 64 entries */\n+\tnix_q_size_256,\n+\tnix_q_size_1K,\n+\tnix_q_size_4K,\n+\tnix_q_size_16K,\n+\tnix_q_size_64K,\n+\tnix_q_size_256K,\n+\tnix_q_size_1M, /* Million entries */\n+\tnix_q_size_max\n+};\n+\n+static inline struct nix *\n+roc_nix_to_nix_priv(struct roc_nix *roc_nix)\n+{\n+\treturn (struct nix *)&roc_nix->reserved[0];\n+}\n+\n+static inline struct roc_nix *\n+nix_priv_to_roc_nix(struct nix *nix)\n+{\n+\treturn (struct roc_nix *)((char *)nix -\n+\t\t\t\t offsetof(struct roc_nix, reserved));\n+}\n+\n+#endif /* _ROC_NIX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.c b/drivers/common/cnxk/roc_platform.c\nindex 7dce0bd..3ac81ce 100644\n--- a/drivers/common/cnxk/roc_platform.c\n+++ b/drivers/common/cnxk/roc_platform.c\n@@ -31,3 +31,4 @@ roc_plt_init(void)\n RTE_LOG_REGISTER(cnxk_logtype_base, pmd.cnxk.base, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_mbox, pmd.cnxk.mbox, NOTICE);\n RTE_LOG_REGISTER(cnxk_logtype_npa, pmd.mempool.cnxk, NOTICE);\n+RTE_LOG_REGISTER(cnxk_logtype_nix, pmd.net.cnxk, NOTICE);\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 7ffaca6..5e4976b 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -135,6 +135,7 @@\n extern int cnxk_logtype_base;\n extern int cnxk_logtype_mbox;\n extern int cnxk_logtype_npa;\n+extern int cnxk_logtype_nix;\n \n #define plt_err(fmt, args...) \\\n \tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\", __func__, __LINE__, ##args)\n@@ -153,6 +154,7 @@ extern int cnxk_logtype_npa;\n #define plt_base_dbg(fmt, ...)\tplt_dbg(base, fmt, ##__VA_ARGS__)\n #define plt_mbox_dbg(fmt, ...)\tplt_dbg(mbox, fmt, ##__VA_ARGS__)\n #define plt_npa_dbg(fmt, ...)\tplt_dbg(npa, fmt, ##__VA_ARGS__)\n+#define plt_nix_dbg(fmt, ...)\tplt_dbg(nix, fmt, ##__VA_ARGS__)\n \n #ifdef __cplusplus\n #define CNXK_PCI_ID(subsystem_dev, dev)\t\t\t\t\\\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 21599dc..7371785 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -20,4 +20,7 @@\n /* idev */\n #include \"roc_idev_priv.h\"\n \n+/* NIX */\n+#include \"roc_nix_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_utils.c b/drivers/common/cnxk/roc_utils.c\nindex b5d8f0b..2b157a3 100644\n--- a/drivers/common/cnxk/roc_utils.c\n+++ b/drivers/common/cnxk/roc_utils.c\n@@ -11,10 +11,37 @@ roc_error_msg_get(int errorcode)\n \tconst char *err_msg;\n \n \tswitch (errorcode) {\n+\tcase NIX_AF_ERR_PARAM:\n+\tcase NIX_ERR_PARAM:\n \tcase NPA_ERR_PARAM:\n \tcase UTIL_ERR_PARAM:\n \t\terr_msg = \"Invalid parameter\";\n \t\tbreak;\n+\tcase NIX_ERR_NO_MEM:\n+\t\terr_msg = \"Out of memory\";\n+\t\tbreak;\n+\tcase NIX_ERR_INVALID_RANGE:\n+\t\terr_msg = \"Range is not supported\";\n+\t\tbreak;\n+\tcase NIX_ERR_INTERNAL:\n+\t\terr_msg = \"Internal error\";\n+\t\tbreak;\n+\tcase NIX_ERR_OP_NOTSUP:\n+\t\terr_msg = \"Operation not supported\";\n+\t\tbreak;\n+\tcase NIX_ERR_QUEUE_INVALID_RANGE:\n+\t\terr_msg = \"Invalid Queue range\";\n+\t\tbreak;\n+\tcase NIX_ERR_AQ_READ_FAILED:\n+\t\terr_msg = \"AQ read failed\";\n+\t\tbreak;\n+\tcase NIX_ERR_AQ_WRITE_FAILED:\n+\t\terr_msg = \"AQ write failed\";\n+\t\tbreak;\n+\tcase NIX_ERR_NDC_SYNC:\n+\t\terr_msg = \"NDC Sync failed\";\n+\t\tbreak;\n+\t\tbreak;\n \tcase NPA_ERR_ALLOC:\n \t\terr_msg = \"NPA alloc failed\";\n \t\tbreak;\n@@ -36,6 +63,21 @@ roc_error_msg_get(int errorcode)\n \tcase NPA_ERR_DEVICE_NOT_BOUNDED:\n \t\terr_msg = \"NPA device is not bounded\";\n \t\tbreak;\n+\tcase NIX_AF_ERR_AQ_FULL:\n+\t\terr_msg = \"AQ full\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_AQ_ENQUEUE:\n+\t\terr_msg = \"AQ enqueue failed\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_AF_LF_INVALID:\n+\t\terr_msg = \"Invalid NIX LF\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_AF_LF_ALLOC:\n+\t\terr_msg = \"NIX LF alloc failed\";\n+\t\tbreak;\n+\tcase NIX_AF_ERR_LF_RESET:\n+\t\terr_msg = \"NIX LF reset failed\";\n+\t\tbreak;\n \tcase UTIL_ERR_FS:\n \t\terr_msg = \"file operation failed\";\n \t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex c0f282d..62aa2ba 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -3,14 +3,30 @@ INTERNAL {\n \n \tcnxk_logtype_base;\n \tcnxk_logtype_mbox;\n+\tcnxk_logtype_nix;\n \tcnxk_logtype_npa;\n \troc_clk_freq_get;\n \troc_error_msg_get;\n \troc_idev_lmt_base_addr_get;\n \troc_idev_npa_maxpools_get;\n \troc_idev_npa_maxpools_set;\n+\troc_idev_npa_nix_get;\n \troc_idev_num_lmtlines_get;\n \troc_model;\n+\troc_nix_dev_fini;\n+\troc_nix_dev_init;\n+\troc_nix_get_base_chan;\n+\troc_nix_get_pf;\n+\troc_nix_get_pf_func;\n+\troc_nix_get_vf;\n+\troc_nix_get_vwqe_interval;\n+\troc_nix_is_lbk;\n+\troc_nix_is_pf;\n+\troc_nix_is_sdp;\n+\troc_nix_is_vf_or_sdp;\n+\troc_nix_lf_alloc;\n+\troc_nix_lf_free;\n+\troc_nix_max_pkt_len;\n \troc_npa_aura_limit_modify;\n \troc_npa_aura_op_range_set;\n \troc_npa_ctx_dump;\n", "prefixes": [ "v2", "17/52" ] }