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GET /api/patches/89905/?format=api
{ "id": 89905, "url": "https://patches.dpdk.org/api/patches/89905/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1616748961-11239-3-git-send-email-humin29@huawei.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1616748961-11239-3-git-send-email-humin29@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1616748961-11239-3-git-send-email-humin29@huawei.com", "date": "2021-03-26T08:56:01", "name": "[2/2] net/hns3: support IEEE 1588 PTP", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b4226bd76bb9949d5b9c920169209a8077b7c817", "submitter": { "id": 1944, "url": "https://patches.dpdk.org/api/people/1944/?format=api", "name": "humin (Q)", "email": "humin29@huawei.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1616748961-11239-3-git-send-email-humin29@huawei.com/mbox/", "series": [ { "id": 15902, "url": "https://patches.dpdk.org/api/series/15902/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15902", "date": "2021-03-26T08:56:00", "name": "Support PTP for hns3 PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/15902/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/89905/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/89905/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 82497A0A02;\n\tFri, 26 Mar 2021 09:55:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 62DC1140D73;\n\tFri, 26 Mar 2021 09:55:43 +0100 (CET)", "from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190])\n by mails.dpdk.org (Postfix) with ESMTP id 983AA140D4C\n for <dev@dpdk.org>; Fri, 26 Mar 2021 09:55:41 +0100 (CET)", "from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59])\n by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4F6G3P2phZz19JjF\n for <dev@dpdk.org>; Fri, 26 Mar 2021 16:53:37 +0800 (CST)", "from localhost.localdomain (10.69.192.56) by\n DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id\n 14.3.498.0; Fri, 26 Mar 2021 16:55:35 +0800" ], "From": "\"Min Hu (Connor)\" <humin29@huawei.com>", "To": "<dev@dpdk.org>, <ferruh.yigit@intel.com>", "Date": "Fri, 26 Mar 2021 16:56:01 +0800", "Message-ID": "<1616748961-11239-3-git-send-email-humin29@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1616748961-11239-1-git-send-email-humin29@huawei.com>", "References": "<1616748961-11239-1-git-send-email-humin29@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.69.192.56]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 2/2] net/hns3: support IEEE 1588 PTP", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add hns3 support for new ethdev APIs to enable and read IEEE1588/\n802.1AS PTP timestamps.\n\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\n---\n doc/guides/nics/features/hns3.ini | 2 +\n doc/guides/nics/hns3.rst | 1 +\n drivers/net/hns3/hns3_cmd.h | 33 +++++\n drivers/net/hns3/hns3_ethdev.c | 59 +++++++-\n drivers/net/hns3/hns3_ethdev.h | 25 ++++\n drivers/net/hns3/hns3_ptp.c | 294 ++++++++++++++++++++++++++++++++++++++\n drivers/net/hns3/hns3_regs.h | 25 ++++\n drivers/net/hns3/hns3_rxtx.c | 56 +++++++-\n drivers/net/hns3/hns3_rxtx.h | 12 ++\n drivers/net/hns3/hns3_rxtx_vec.c | 19 ++-\n drivers/net/hns3/meson.build | 3 +-\n 11 files changed, 516 insertions(+), 13 deletions(-)\n create mode 100644 drivers/net/hns3/hns3_ptp.c", "diff": "diff --git a/doc/guides/nics/features/hns3.ini b/doc/guides/nics/features/hns3.ini\nindex 3988be4..502bfe7 100644\n--- a/doc/guides/nics/features/hns3.ini\n+++ b/doc/guides/nics/features/hns3.ini\n@@ -43,6 +43,8 @@ Stats per queue = Y\n FW version = Y\n Registers dump = Y\n Module EEPROM dump = Y\n+Timesync = Y\n+Timestamp offload = Y\n Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/doc/guides/nics/hns3.rst b/doc/guides/nics/hns3.rst\nindex ccd2f6f..3366562 100644\n--- a/doc/guides/nics/hns3.rst\n+++ b/doc/guides/nics/hns3.rst\n@@ -37,6 +37,7 @@ Features of the HNS3 PMD are:\n - MTU update\n - NUMA support\n - Generic flow API\n+- IEEE1588/802.1AS timestamping\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h\nindex e704d0c..abc853b 100644\n--- a/drivers/net/hns3/hns3_cmd.h\n+++ b/drivers/net/hns3/hns3_cmd.h\n@@ -123,6 +123,12 @@ enum hns3_opcode_type {\n \tHNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312,\n \tHNS3_OPC_CONFIG_FEC_MODE = 0x031A,\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\t/* PTP command */\n+\tHNS3_OPC_PTP_INT_EN = 0x0501,\n+\tHNS3_OPC_CFG_PTP_MODE = 0x0507,\n+#endif\n+\n \t/* PFC/Pause commands */\n \tHNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701,\n \tHNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702,\n@@ -969,6 +975,33 @@ struct hns3_query_ssu_cmd {\n \tuint32_t oq_drop_cnt;\n \tuint32_t rev1[2];\n };\n+#ifdef RTE_LIBRTE_IEEE1588\n+#define HNS3_PTP_ENABLE_B 0\n+#define HNS3_PTP_TX_ENABLE_B 1\n+#define HNS3_PTP_RX_ENABLE_B 2\n+\n+#define HNS3_PTP_TYPE_S 0\n+#define HNS3_PTP_TYPE_M (0x3 << HNS3_PTP_TYPE_S)\n+\n+#define ALL_PTP_V2_TYPE 0xF\n+#define HNS3_PTP_MESSAGE_TYPE_S 0\n+#define HNS3_PTP_MESSAGE_TYPE_M (0xF << HNS3_PTP_MESSAGE_TYPE_S)\n+\n+#define PTP_TYPE_L2_V2_TYPE 0\n+\n+struct hns3_ptp_mode_cfg_cmd {\n+\tuint8_t enable;\n+\tuint8_t ptp_type;\n+\tuint8_t v2_message_type_1;\n+\tuint8_t v2_message_type_0;\n+\tuint8_t rsv[20];\n+};\n+\n+struct hns3_ptp_int_cmd {\n+\tuint8_t int_en;\n+\tuint8_t rsvd[23];\n+};\n+#endif\n \n #define HNS3_MAX_TQP_NUM_HIP08_PF\t64\n #define HNS3_DEFAULT_TX_BUF\t\t0x4000 /* 16k bytes */\ndiff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c\nindex b985447..11b9065 100644\n--- a/drivers/net/hns3/hns3_ethdev.c\n+++ b/drivers/net/hns3/hns3_ethdev.c\n@@ -58,6 +58,10 @@ enum hns3_evt_cause {\n \tHNS3_VECTOR0_EVENT_RST,\n \tHNS3_VECTOR0_EVENT_MBX,\n \tHNS3_VECTOR0_EVENT_ERR,\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\tHNS3_VECTOR0_EVENT_PTP,\n+#endif\n \tHNS3_VECTOR0_EVENT_OTHER,\n };\n \n@@ -202,6 +206,14 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \t\tgoto out;\n \t}\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\t/* Check for vector0 1588 event source */\n+\tif (BIT(HNS3_VECTOR0_1588_INT_B) & vector0_int_stats) {\n+\t\tval = BIT(HNS3_VECTOR0_1588_INT_B);\n+\t\tret = HNS3_VECTOR0_EVENT_PTP;\n+\t\tgoto out;\n+\t}\n+#endif\n \t/* check for vector0 msix event source */\n \tif (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||\n \t hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {\n@@ -227,10 +239,22 @@ hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)\n \treturn ret;\n }\n \n+static bool\n+hns3_is_1588_event_type(uint32_t event_type)\n+{\n+#ifdef RTE_LIBRTE_IEEE1588\n+\treturn (event_type == HNS3_VECTOR0_EVENT_PTP);\n+#else\n+\tRTE_SET_USED(event_type);\n+\treturn false;\n+#endif\n+}\n+\n static void\n hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)\n {\n-\tif (event_type == HNS3_VECTOR0_EVENT_RST)\n+\tif (event_type == HNS3_VECTOR0_EVENT_RST ||\n+\t hns3_is_1588_event_type(event_type))\n \t\thns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);\n \telse if (event_type == HNS3_VECTOR0_EVENT_MBX)\n \t\thns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);\n@@ -253,6 +277,11 @@ hns3_clear_all_event_cause(struct hns3_hw *hw)\n \t\t\t BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |\n \t\t\t BIT(HNS3_VECTOR0_CORERESET_INT_B));\n \thns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\thns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_PTP,\n+\t\t\t\tBIT(HNS3_VECTOR0_1588_INT_B));\n+#endif\n }\n \n static void\n@@ -2467,6 +2496,11 @@ hns3_dev_configure(struct rte_eth_dev *dev)\n \tif (ret)\n \t\tgoto cfg_err;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tret = hns3_mbuf_dyn_rx_timestamp_register(dev, conf);\n+\tif (ret)\n+\t\tgoto cfg_err;\n+#endif\n \tret = hns3_dev_configure_vlan(dev);\n \tif (ret)\n \t\tgoto cfg_err;\n@@ -2640,6 +2674,9 @@ hns3_dev_infos_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *info)\n \t\tinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\n \n+\tif (hns3_dev_ptp_supported(hw))\n+\t\tinfo->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;\n+\n \tinfo->rx_desc_lim = (struct rte_eth_desc_lim) {\n \t\t.nb_max = HNS3_MAX_RING_DESC,\n \t\t.nb_min = HNS3_MIN_RING_DESC,\n@@ -4933,6 +4970,11 @@ hns3_init_pf(struct rte_eth_dev *eth_dev)\n \t\tgoto err_intr_callback_register;\n \t}\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tret = hns3_ptp_init(hw);\n+\tif (ret)\n+\t\tgoto err_get_config;\n+#endif\n \t/* Enable interrupt */\n \trte_intr_enable(&pci_dev->intr_handle);\n \thns3_pf_enable_irq0(hw);\n@@ -5950,6 +5992,12 @@ hns3_restore_conf(struct hns3_adapter *hns)\n \tif (ret)\n \t\tgoto err_promisc;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tret = hns3_restore_ptp(hns);\n+\tif (ret)\n+\t\tgoto err_promisc;\n+#endif\n+\n \tret = hns3_restore_rx_interrupt(hw);\n \tif (ret)\n \t\tgoto err_promisc;\n@@ -6654,6 +6702,15 @@ static const struct eth_dev_ops hns3_eth_dev_ops = {\n \t.fec_set = hns3_fec_set,\n \t.tm_ops_get = hns3_tm_ops_get,\n \t.tx_done_cleanup = hns3_tx_done_cleanup,\n+#ifdef RTE_LIBRTE_IEEE1588\n+\t.timesync_enable = hns3_timesync_enable,\n+\t.timesync_disable = hns3_timesync_disable,\n+\t.timesync_read_rx_timestamp = hns3_timesync_read_rx_timestamp,\n+\t.timesync_read_tx_timestamp = hns3_timesync_read_tx_timestamp,\n+\t.timesync_adjust_time = hns3_timesync_adjust_time,\n+\t.timesync_read_time = hns3_timesync_read_time,\n+\t.timesync_write_time = hns3_timesync_write_time,\n+#endif\n };\n \n static const struct hns3_reset_ops hns3_reset_ops = {\ndiff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nindex f69e2d8..4ce192c 100644\n--- a/drivers/net/hns3/hns3_ethdev.h\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -731,6 +731,13 @@ struct hns3_pf {\n \tbool support_sfp_query;\n \tuint32_t fec_mode; /* current FEC mode for ethdev */\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tbool ptp_enable;\n+\n+\t/* Stores timestamp of last received packet on dev */\n+\tuint64_t rx_timestamp;\n+#endif\n+\n \tstruct hns3_vtag_cfg vtag_config;\n \tLIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;\n \n@@ -982,6 +989,24 @@ void hns3vf_update_link_status(struct hns3_hw *hw, uint8_t link_status,\n \t\t\t uint32_t link_speed, uint8_t link_duplex);\n void hns3_parse_devargs(struct rte_eth_dev *dev);\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+int hns3_restore_ptp(struct hns3_adapter *hns);\n+int hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_conf *conf);\n+int hns3_ptp_init(struct hns3_hw *hw);\n+int hns3_timesync_enable(struct rte_eth_dev *dev);\n+int hns3_timesync_disable(struct rte_eth_dev *dev);\n+int hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\tstruct timespec *timestamp,\n+\t\t\t\tuint32_t flags __rte_unused);\n+int hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\tstruct timespec *timestamp);\n+int hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts);\n+int hns3_timesync_write_time(struct rte_eth_dev *dev,\n+\t\t\tconst struct timespec *ts);\n+int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);\n+#endif\n+\n static inline bool\n is_reset_pending(struct hns3_adapter *hns)\n {\ndiff --git a/drivers/net/hns3/hns3_ptp.c b/drivers/net/hns3/hns3_ptp.c\nnew file mode 100644\nindex 0000000..d7e18c1\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_ptp.c\n@@ -0,0 +1,294 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021-2021 Hisilicon Limited.\n+ */\n+\n+#include <ethdev_pci.h>\n+#include <rte_io.h>\n+#include <rte_time.h>\n+\n+#include \"hns3_ethdev.h\"\n+#include \"hns3_regs.h\"\n+#include \"hns3_logs.h\"\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+uint64_t hns3_timestamp_rx_dynflag;\n+int hns3_timestamp_dynfield_offset = -1;\n+\n+int\n+hns3_mbuf_dyn_rx_timestamp_register(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_conf *conf)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tint ret;\n+\n+\tif (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_TIMESTAMP))\n+\t\treturn 0;\n+\n+\tret = rte_mbuf_dyn_rx_timestamp_register\n+\t\t\t(&hns3_timestamp_dynfield_offset,\n+\t\t\t &hns3_timestamp_rx_dynflag);\n+\tif (ret) {\n+\t\thns3_err(hw,\n+\t\t\t\"failed to register Rx timestamp field/flag\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_ptp_int_en(struct hns3_hw *hw, bool en)\n+{\n+\tstruct hns3_ptp_int_cmd *req;\n+\tstruct hns3_cmd_desc desc;\n+\tint ret;\n+\n+\treq = (struct hns3_ptp_int_cmd *)desc.data;\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_PTP_INT_EN, false);\n+\treq->int_en = en ? 1 : 0;\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret)\n+\t\thns3_err(hw,\n+\t\t\t\"failed to %s ptp interrupt, ret = %d\\n\",\n+\t\t\ten ? \"enable\" : \"disable\", ret);\n+\n+\treturn ret;\n+}\n+\n+int\n+hns3_ptp_init(struct hns3_hw *hw)\n+{\n+\tint ret;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn 0;\n+\n+\tret = hns3_ptp_int_en(hw, true);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Start PTP timer */\n+\thns3_write_dev(hw, HNS3_CFG_TIME_CYC_EN, 1);\n+\n+\treturn 0;\n+}\n+\n+static int\n+hns3_timesync_configure(struct hns3_adapter *hns, bool en)\n+{\n+\tstruct hns3_ptp_mode_cfg_cmd *req;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tstruct hns3_cmd_desc desc;\n+\tint val;\n+\tint ret;\n+\n+\thns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_PTP_MODE, false);\n+\n+\treq = (struct hns3_ptp_mode_cfg_cmd *)desc.data;\n+\n+\tval = en ? 1 : 0;\n+\thns3_set_bit(req->enable, HNS3_PTP_ENABLE_B, val);\n+\thns3_set_bit(req->enable, HNS3_PTP_TX_ENABLE_B, val);\n+\thns3_set_bit(req->enable, HNS3_PTP_RX_ENABLE_B, val);\n+\n+\tif (en) {\n+\t\thns3_set_field(req->ptp_type, HNS3_PTP_TYPE_M, HNS3_PTP_TYPE_S,\n+\t\t\t PTP_TYPE_L2_V2_TYPE);\n+\t\thns3_set_field(req->v2_message_type_1, HNS3_PTP_MESSAGE_TYPE_M,\n+\t\t\t HNS3_PTP_MESSAGE_TYPE_S, ALL_PTP_V2_TYPE);\n+\t}\n+\n+\tret = hns3_cmd_send(hw, &desc, 1);\n+\tif (ret) {\n+\t\thns3_err(hw, \"configure PTP time failed, en = %d, ret = %d\",\n+\t\t\t en, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tpf->ptp_enable = en;\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_timesync_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tint ret;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\tif (pf->ptp_enable)\n+\t\treturn 0;\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3_timesync_configure(hns, true);\n+\trte_spinlock_unlock(&hw->lock);\n+\treturn ret;\n+}\n+\n+int\n+hns3_timesync_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tint ret;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\tif (!pf->ptp_enable)\n+\t\treturn 0;\n+\n+\trte_spinlock_lock(&hw->lock);\n+\tret = hns3_timesync_configure(hns, false);\n+\trte_spinlock_unlock(&hw->lock);\n+\n+\treturn ret;\n+}\n+\n+int\n+hns3_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\tstruct timespec *timestamp,\n+\t\t\t\tuint32_t flags __rte_unused)\n+{\n+#define TIME_RX_STAMP_NS_MASK 0x3FFFFFFF\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tuint64_t ns, sec;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\tns = pf->rx_timestamp & TIME_RX_STAMP_NS_MASK;\n+\tsec = upper_32_bits(pf->rx_timestamp);\n+\n+\tns += sec * NSEC_PER_SEC;\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\tstruct timespec *timestamp)\n+{\n+#define TIME_TX_STAMP_NS_MASK 0x3FFFFFFF\n+#define TIME_TX_STAMP_VALID 24\n+#define TIME_TX_STAMP_CNT_MASK 0x7\n+\tstruct hns3_adapter *hns = dev->data->dev_private;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tuint64_t sec;\n+\tuint64_t tmp;\n+\tuint64_t ns;\n+\tint ts_cnt;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\tts_cnt = hns3_read_dev(hw, HNS3_TX_1588_BACK_TSP_CNT) &\n+\t\t\tTIME_TX_STAMP_CNT_MASK;\n+\tif (ts_cnt == 0)\n+\t\treturn -EINVAL;\n+\n+\tns = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_0) & TIME_TX_STAMP_NS_MASK;\n+\tsec = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_1);\n+\ttmp = hns3_read_dev(hw, HNS3_TX_1588_TSP_BACK_2) & 0xFFFF;\n+\tsec = (tmp << 32) | sec;\n+\n+\tns += sec * NSEC_PER_SEC;\n+\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\t/* Clear current timestamp hardware stores */\n+\thns3_read_dev(hw, HNS3_TX_1588_SEQID_BACK);\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t ns, sec;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\tsec = hns3_read_dev(hw, HNS3_CURR_TIME_OUT_L);\n+\tsec |= (uint64_t)(hns3_read_dev(hw, HNS3_CURR_TIME_OUT_H) & 0xFFFF)\n+\t\t<< 32;\n+\n+\tns = hns3_read_dev(hw, HNS3_CURR_TIME_OUT_NS);\n+\tns += sec * NSEC_PER_SEC;\n+\t*ts = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n+{\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t sec = ts->tv_sec;\n+\tuint64_t ns = ts->tv_nsec;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\t/* Set the timecounters to a new value. */\n+\thns3_write_dev(hw, HNS3_CFG_TIME_SYNC_H, upper_32_bits(sec));\n+\thns3_write_dev(hw, HNS3_CFG_TIME_SYNC_M, lower_32_bits(sec));\n+\thns3_write_dev(hw, HNS3_CFG_TIME_SYNC_L, lower_32_bits(ns));\n+\thns3_write_dev(hw, HNS3_CFG_TIME_SYNC_RDY, 1);\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n+{\n+#define TIME_SYNC_L_MASK 0x7FFFFFFF\n+#define SYMBOL_BIT_OFFSET 31\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct timespec cur_time;\n+\tuint64_t ns;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+\n+\t(void)hns3_timesync_read_time(dev, &cur_time);\n+\tns = rte_timespec_to_ns((const struct timespec *)&cur_time);\n+\tcur_time = rte_ns_to_timespec(ns + delta);\n+\t(void)hns3_timesync_write_time(dev, (const struct timespec *)&cur_time);\n+\n+\treturn 0;\n+}\n+\n+int\n+hns3_restore_ptp(struct hns3_adapter *hns)\n+{\n+\tstruct hns3_pf *pf = &hns->pf;\n+\tstruct hns3_hw *hw = &hns->hw;\n+\tbool en = pf->ptp_enable;\n+\tint ret;\n+\n+\tif (!hns3_dev_ptp_supported(hw))\n+\t\treturn 0;\n+\n+\tret = hns3_timesync_configure(hns, en);\n+\tif (ret)\n+\t\thns3_err(hw, \"restore PTP enable state(%d) failed, ret = %d\",\n+\t\t\t en, ret);\n+\n+\treturn ret;\n+}\n+#endif\ndiff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h\nindex e141fe1..58a20ca 100644\n--- a/drivers/net/hns3/hns3_regs.h\n+++ b/drivers/net/hns3/hns3_regs.h\n@@ -121,6 +121,31 @@\n #define HNS3_TQP_INTR_RL_DEFAULT\t\t0\n #define HNS3_TQP_INTR_QL_DEFAULT\t\t0\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+/* Register bit for 1588 event */\n+#define HNS3_VECTOR0_1588_INT_B\t 0\n+\n+#define HNS3_PTP_BASE_ADDRESS\t\t\t0x29000\n+\n+#define HNS3_TX_1588_SEQID_BACK\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x0)\n+#define HNS3_TX_1588_TSP_BACK_0\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x4)\n+#define HNS3_TX_1588_TSP_BACK_1\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x8)\n+#define HNS3_TX_1588_TSP_BACK_2\t\t\t(HNS3_PTP_BASE_ADDRESS + 0xc)\n+\n+#define HNS3_TX_1588_BACK_TSP_CNT\t\t(HNS3_PTP_BASE_ADDRESS + 0x30)\n+\n+#define HNS3_CFG_TIME_SYNC_H\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x50)\n+#define HNS3_CFG_TIME_SYNC_M\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x54)\n+#define HNS3_CFG_TIME_SYNC_L\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x58)\n+#define HNS3_CFG_TIME_SYNC_RDY\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x5c)\n+\n+#define HNS3_CFG_TIME_CYC_EN\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x70)\n+\n+#define HNS3_CURR_TIME_OUT_H\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x74)\n+#define HNS3_CURR_TIME_OUT_L\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x78)\n+#define HNS3_CURR_TIME_OUT_NS\t\t\t(HNS3_PTP_BASE_ADDRESS + 0x7c)\n+#endif\n+\n /* gl_usec convert to hardware count, as writing each 1 represents 2us */\n #define HNS3_GL_USEC_TO_REG(gl_usec)\t\t((gl_usec) >> 1)\n /* rl_usec convert to hardware count, as writing each 1 represents 4us */\ndiff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex feeb702..ceed302 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -2275,6 +2275,25 @@ hns3_rx_alloc_buffer(struct hns3_rx_queue *rxq)\n \t\treturn rte_mbuf_raw_alloc(rxq->mb_pool);\n }\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+static inline void\n+hns3_rx_ptp_timestamp_handle(struct hns3_rx_queue *rxq, struct rte_mbuf *mbuf,\n+\t\t volatile struct hns3_desc *rxd)\n+{\n+\tstruct hns3_pf *pf = HNS3_DEV_PRIVATE_TO_PF(rxq->hns);\n+\tuint64_t timestamp = rte_le_to_cpu_64(rxd->timestamp);\n+\n+\tmbuf->ol_flags |= PKT_RX_IEEE1588_PTP | PKT_RX_IEEE1588_TMST;\n+\tif (hns3_timestamp_rx_dynflag > 0) {\n+\t\t*RTE_MBUF_DYNFIELD(mbuf, hns3_timestamp_dynfield_offset,\n+\t\t\trte_mbuf_timestamp_t *) = timestamp;\n+\t\tmbuf->ol_flags |= hns3_timestamp_rx_dynflag;\n+\t}\n+\n+\tpf->rx_timestamp = timestamp;\n+}\n+#endif\n+\n uint16_t\n hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n {\n@@ -2334,8 +2353,13 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t}\n \n \t\trxm = rxe->mbuf;\n+\t\trxm->ol_flags = 0;\n \t\trxe->mbuf = nmb;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\t\tif (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B)))\n+\t\t\thns3_rx_ptp_timestamp_handle(rxq, rxm, rxdp);\n+#endif\n \t\tdma_addr = rte_mbuf_data_iova_default(nmb);\n \t\trxdp->addr = rte_cpu_to_le_64(dma_addr);\n \t\trxdp->rx.bd_base_info = 0;\n@@ -2346,7 +2370,7 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\trxm->data_len = rxm->pkt_len;\n \t\trxm->port = rxq->port_id;\n \t\trxm->hash.rss = rte_le_to_cpu_32(rxd.rx.rss_hash);\n-\t\trxm->ol_flags = PKT_RX_RSS_HASH;\n+\t\trxm->ol_flags |= PKT_RX_RSS_HASH;\n \t\tif (unlikely(bd_base_info & BIT(HNS3_RXD_LUM_B))) {\n \t\t\trxm->hash.fdir.hi =\n \t\t\t\trte_le_to_cpu_16(rxd.rx.fd_id);\n@@ -2365,6 +2389,11 @@ hns3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \n \t\trxm->packet_type = hns3_rx_calc_ptype(rxq, l234_info, ol_info);\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\t\tif (rxm->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC)\n+\t\t\trxm->ol_flags |= PKT_RX_IEEE1588_PTP;\n+#endif\n+\n \t\tif (likely(bd_base_info & BIT(HNS3_RXD_L3L4P_B)))\n \t\t\thns3_rx_set_cksum_flag(rxm, rxm->packet_type,\n \t\t\t\t\t cksum_err);\n@@ -2952,7 +2981,7 @@ hns3_fill_per_desc(struct hns3_desc *desc, struct rte_mbuf *rxm)\n {\n \tdesc->addr = rte_mbuf_data_iova(rxm);\n \tdesc->tx.send_size = rte_cpu_to_le_16(rte_pktmbuf_data_len(rxm));\n-\tdesc->tx.tp_fe_sc_vld_ra_ri = rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));\n+\tdesc->tx.tp_fe_sc_vld_ra_ri |= rte_cpu_to_le_16(BIT(HNS3_TXD_VLD_B));\n }\n \n static void\n@@ -3000,6 +3029,12 @@ hns3_fill_first_desc(struct hns3_tx_queue *txq, struct hns3_desc *desc,\n \t\t\t\t\trte_cpu_to_le_32(BIT(HNS3_TXD_VLAN_B));\n \t\tdesc->tx.vlan_tag = rte_cpu_to_le_16(rxm->vlan_tci);\n \t}\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n+\t\tdesc->tx.tp_fe_sc_vld_ra_ri |=\n+\t\t\t\trte_cpu_to_le_16(BIT(HNS3_TXD_TSYN_B));\n+#endif\n }\n \n static inline int\n@@ -3991,10 +4026,23 @@ hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,\n \treturn 0;\n }\n \n+static bool\n+hns3_tx_check_simple_support(struct rte_eth_dev *dev)\n+{\n+\tuint64_t offloads = dev->data->dev_conf.txmode.offloads;\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tif (hns3_dev_ptp_supported(hw))\n+\t\treturn false;\n+#endif\n+\n+\treturn (offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE));\n+}\n+\n static eth_tx_burst_t\n hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)\n {\n-\tuint64_t offloads = dev->data->dev_conf.txmode.offloads;\n \tstruct hns3_adapter *hns = dev->data->dev_private;\n \tbool vec_allowed, sve_allowed, simple_allowed;\n \n@@ -4002,7 +4050,7 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)\n \t\t hns3_tx_check_vec_support(dev) == 0;\n \tsve_allowed = vec_allowed && hns3_check_sve_support();\n \tsimple_allowed = hns->tx_simple_allowed &&\n-\t\t\t offloads == (offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);\n+\t\t\t hns3_tx_check_simple_support(dev);\n \n \t*prep = NULL;\n \ndiff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex f9b3048..74e5407 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -106,6 +106,8 @@\n #define HNS3_RXD_L3L4P_B\t\t\t11\n #define HNS3_RXD_TSIND_S\t\t\t12\n #define HNS3_RXD_TSIND_M\t\t\t(0x7 << HNS3_RXD_TSIND_S)\n+\n+#define HNS3_RXD_TS_VLD_B\t\t\t14\n #define HNS3_RXD_LKBK_B\t\t\t\t15\n #define HNS3_RXD_GRO_SIZE_S\t\t\t16\n #define HNS3_RXD_GRO_SIZE_M\t\t\t(0x3fff << HNS3_RXD_GRO_SIZE_S)\n@@ -200,6 +202,11 @@ enum hns3_pkt_tun_type {\n struct hns3_desc {\n \tunion {\n \t\tuint64_t addr;\n+\n+#ifdef RTE_LIBRTE_IEEE1588\n+\t\tuint64_t timestamp;\n+#endif\n+\n \t\tstruct {\n \t\t\tuint32_t addr0;\n \t\t\tuint32_t addr1;\n@@ -518,6 +525,11 @@ enum hns3_cksum_status {\n \tHNS3_OUTER_L4_CKSUM_ERR = 8\n };\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+extern uint64_t hns3_timestamp_rx_dynflag;\n+extern int hns3_timestamp_dynfield_offset;\n+#endif\n+\n static inline int\n hns3_handle_bdinfo(struct hns3_rx_queue *rxq, struct rte_mbuf *rxm,\n \t\t uint32_t bd_base_info, uint32_t l234_info,\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec.c b/drivers/net/hns3/hns3_rxtx_vec.c\nindex 2bc4372..4584d8a 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec.c\n@@ -18,6 +18,12 @@ hns3_tx_check_vec_support(struct rte_eth_dev *dev)\n {\n \tstruct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tif (hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+#endif\n+\n \t/* Only support DEV_TX_OFFLOAD_MBUF_FAST_FREE */\n \tif (txmode->offloads != DEV_TX_OFFLOAD_MBUF_FAST_FREE)\n \t\treturn -ENOTSUP;\n@@ -167,7 +173,6 @@ hns3_rxq_vec_setup(struct hns3_rx_queue *rxq)\n \tmemset(rxq->offset_table, 0, sizeof(rxq->offset_table));\n }\n \n-#ifndef RTE_LIBRTE_IEEE1588\n static int\n hns3_rxq_vec_check(struct hns3_rx_queue *rxq, void *arg)\n {\n@@ -183,17 +188,21 @@ hns3_rxq_vec_check(struct hns3_rx_queue *rxq, void *arg)\n \tRTE_SET_USED(arg);\n \treturn 0;\n }\n-#endif\n \n int\n hns3_rx_check_vec_support(struct rte_eth_dev *dev)\n {\n-#ifndef RTE_LIBRTE_IEEE1588\n \tstruct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;\n \tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n \tuint64_t offloads_mask = DEV_RX_OFFLOAD_TCP_LRO |\n \t\t\t\t DEV_RX_OFFLOAD_VLAN;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tstruct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tif (hns3_dev_ptp_supported(hw))\n+\t\treturn -ENOTSUP;\n+#endif\n+\n \tif (dev->data->scattered_rx)\n \t\treturn -ENOTSUP;\n \n@@ -207,8 +216,4 @@ hns3_rx_check_vec_support(struct rte_eth_dev *dev)\n \t\treturn -ENOTSUP;\n \n \treturn 0;\n-#else\n-\tRTE_SET_USED(dev);\n-\treturn -ENOTSUP;\n-#endif\n }\ndiff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build\nindex f6aac69..6d78c33 100644\n--- a/drivers/net/hns3/meson.build\n+++ b/drivers/net/hns3/meson.build\n@@ -26,7 +26,8 @@ sources = files('hns3_cmd.c',\n \t'hns3_rxtx.c',\n \t'hns3_stats.c',\n \t'hns3_mp.c',\n-\t'hns3_tm.c')\n+\t'hns3_tm.c',\n+\t'hns3_ptp.c')\n \n deps += ['hash']\n \n", "prefixes": [ "2/2" ] }