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{
    "id": 89219,
    "url": "https://patches.dpdk.org/api/patches/89219/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210316105149.110904-5-jiawenwu@trustnetic.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210316105149.110904-5-jiawenwu@trustnetic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210316105149.110904-5-jiawenwu@trustnetic.com",
    "date": "2021-03-16T10:51:46",
    "name": "[v2,4/7] net/txgbe: update link setup process of backplane NICs",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "b5de5d516f72ea3e2501e670abc39eedca7b66c8",
    "submitter": {
        "id": 1932,
        "url": "https://patches.dpdk.org/api/people/1932/?format=api",
        "name": "Jiawen Wu",
        "email": "jiawenwu@trustnetic.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210316105149.110904-5-jiawenwu@trustnetic.com/mbox/",
    "series": [
        {
            "id": 15691,
            "url": "https://patches.dpdk.org/api/series/15691/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15691",
            "date": "2021-03-16T10:51:42",
            "name": "txgbe backplane AN training",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/15691/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/89219/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/89219/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D8073A054F;\n\tTue, 16 Mar 2021 11:52:15 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 49C9E24286F;\n\tTue, 16 Mar 2021 11:52:02 +0100 (CET)",
            "from smtpbg511.qq.com (smtpbg511.qq.com [203.205.250.109])\n by mails.dpdk.org (Postfix) with ESMTP id 8B00F242845\n for <dev@dpdk.org>; Tue, 16 Mar 2021 11:51:57 +0100 (CET)",
            "from wxdbg.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Tue, 16 Mar 2021 18:51:52 +0800 (CST)"
        ],
        "X-QQ-mid": "bizesmtp11t1615891912ta0mrhld",
        "X-QQ-SSF": "01400000002000C0E000B00A0000000",
        "X-QQ-FEAT": "VhB2JdYvshfLtgGNsm59q4HTWEh9X/1ENoo7K8GZh47Xn3Am8NVo/X66hKGgK\n oPebYw9EULqyV9JyooMiyrJgGznWgzHbpktvPOGUNxyN6O2i38vD0lK1FBaCRj16/Oqnv4b\n tpwRWZcfmZkcU2Dxd6pDiLw6wojaGN/vv0Nnn1O99aeDPMFoXY2Ae6PEq95qO+SZhBG5zd8\n 6pQgX/uGrhmKWTdSgAdtUIUgXdj93pTUfp4VxOASgaDhv/aGDznHJRhpmtaju7E7sERjv+x\n TZrI1ZPA0adFAEvo00fs8ClgYwW00MDvu0aaB/AFvR8lnYxfo1x0+dAtcC7/eyMVoiP84MA\n GET8XrxrpjYIlQT+LPWSUWdv+On/qAClTeVPZOX",
        "X-QQ-GoodBg": "2",
        "From": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "Date": "Tue, 16 Mar 2021 18:51:46 +0800",
        "Message-Id": "<20210316105149.110904-5-jiawenwu@trustnetic.com>",
        "X-Mailer": "git-send-email 2.27.0",
        "In-Reply-To": "<20210316105149.110904-1-jiawenwu@trustnetic.com>",
        "References": "<20210316105149.110904-1-jiawenwu@trustnetic.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-QQ-SENDSIZE": "520",
        "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7",
        "X-QQ-Bgrelay": "1",
        "Subject": "[dpdk-dev] [PATCH v2 4/7] net/txgbe: update link setup process of\n backplane NICs",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Use some configuration to control the link setup flow, to adapt to\ndifferent NIC's construction. Use firmware version to control the impact\nof firmware update. And fix some left bugs.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_eeprom.h |   3 +\n drivers/net/txgbe/base/txgbe_hw.c     |  85 +---------------\n drivers/net/txgbe/base/txgbe_osdep.h  |   1 +\n drivers/net/txgbe/base/txgbe_phy.c    | 141 +++++++++++++++-----------\n drivers/net/txgbe/base/txgbe_phy.h    |  90 ++++++++++++++--\n drivers/net/txgbe/base/txgbe_type.h   |   3 +-\n drivers/net/txgbe/txgbe_logs.h        |  10 ++\n 7 files changed, 189 insertions(+), 144 deletions(-)",
    "diff": "diff --git a/drivers/net/txgbe/base/txgbe_eeprom.h b/drivers/net/txgbe/base/txgbe_eeprom.h\nindex 78b8af978..3a5d7c621 100644\n--- a/drivers/net/txgbe/base/txgbe_eeprom.h\n+++ b/drivers/net/txgbe/base/txgbe_eeprom.h\n@@ -9,6 +9,9 @@\n #define TXGBE_PBANUM_PTR_GUARD\t\t0xFAFA\n #define TXGBE_EEPROM_SUM\t\t0xBABA\n \n+#define TXGBE_FW_VER_LEN\t32\n+#define TXGBE_FW_N_TXEQ\t\t0x0002000A\n+\n #define TXGBE_FW_PTR\t\t\t0x0F\n #define TXGBE_PBANUM0_PTR\t\t0x05\n #define TXGBE_PBANUM1_PTR\t\t0x06\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex 26562f50d..521cb4650 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -91,7 +91,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)\n \tu16 reg_cu = 0;\n \tu32 value = 0;\n \tu64 reg_bp = 0;\n-\tbool locked = false;\n \n \tDEBUGFUNC(\"txgbe_setup_fc\");\n \n@@ -109,29 +108,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)\n \tif (hw->fc.requested_mode == txgbe_fc_default)\n \t\thw->fc.requested_mode = txgbe_fc_full;\n \n-\t/*\n-\t * Set up the 1G and 10G flow control advertisement registers so the\n-\t * HW will be able to do fc autoneg once the cable is plugged in.  If\n-\t * we link at 10G, the 1G advertisement is harmless and vice versa.\n-\t */\n-\tswitch (hw->phy.media_type) {\n-\tcase txgbe_media_type_backplane:\n-\t\t/* some MAC's need RMW protection on AUTOC */\n-\t\terr = hw->mac.prot_autoc_read(hw, &locked, &reg_bp);\n-\t\tif (err != 0)\n-\t\t\tgoto out;\n-\n-\t\t/* fall through - only backplane uses autoc */\n-\tcase txgbe_media_type_fiber_qsfp:\n-\tcase txgbe_media_type_fiber:\n-\tcase txgbe_media_type_copper:\n-\t\thw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,\n-\t\t\t\t     TXGBE_MD_DEV_AUTO_NEG, &reg_cu);\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n \t/*\n \t * The possible values of fc.requested_mode are:\n \t * 0: Flow control is completely disabled\n@@ -145,13 +121,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)\n \tswitch (hw->fc.requested_mode) {\n \tcase txgbe_fc_none:\n \t\t/* Flow control completely disabled by software override. */\n-\t\treg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |\n-\t\t\tSR_MII_MMD_AN_ADV_PAUSE_ASM);\n-\t\tif (hw->phy.media_type == txgbe_media_type_backplane)\n-\t\t\treg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |\n-\t\t\t\t    TXGBE_AUTOC_ASM_PAUSE);\n-\t\telse if (hw->phy.media_type == txgbe_media_type_copper)\n-\t\t\treg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);\n \t\tbreak;\n \tcase txgbe_fc_tx_pause:\n \t\t/*\n@@ -159,15 +128,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)\n \t\t * disabled by software override.\n \t\t */\n \t\treg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;\n-\t\treg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;\n-\t\tif (hw->phy.media_type == txgbe_media_type_backplane) {\n-\t\t\treg_bp |= TXGBE_AUTOC_ASM_PAUSE;\n-\t\t\treg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;\n-\t\t} else if (hw->phy.media_type == txgbe_media_type_copper) {\n-\t\t\treg_cu |= TXGBE_TAF_ASM_PAUSE;\n-\t\t\treg_cu &= ~TXGBE_TAF_SYM_PAUSE;\n-\t\t}\n-\t\treg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;\n \t\treg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;\n \t\tbreak;\n \tcase txgbe_fc_rx_pause:\n@@ -182,13 +142,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)\n \t\t */\n \tcase txgbe_fc_full:\n \t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n-\t\treg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |\n-\t\t\tSR_MII_MMD_AN_ADV_PAUSE_ASM;\n-\t\tif (hw->phy.media_type == txgbe_media_type_backplane)\n-\t\t\treg_bp |= TXGBE_AUTOC_SYM_PAUSE |\n-\t\t\t\t  TXGBE_AUTOC_ASM_PAUSE;\n-\t\telse if (hw->phy.media_type == txgbe_media_type_copper)\n-\t\t\treg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;\n \t\treg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |\n \t\t\tSR_MII_MMD_AN_ADV_PAUSE_ASM;\n \t\treg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |\n@@ -2575,13 +2528,9 @@ void txgbe_init_mac_link_ops(struct txgbe_hw *hw)\n \t\tmac->setup_link = txgbe_setup_mac_link_multispeed_fiber;\n \t\tmac->setup_mac_link = txgbe_setup_mac_link;\n \t\tmac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;\n-\t} else if ((hw->phy.media_type == txgbe_media_type_backplane) &&\n-\t\t    (hw->phy.smart_speed == txgbe_smart_speed_auto ||\n-\t\t     hw->phy.smart_speed == txgbe_smart_speed_on) &&\n-\t\t     !txgbe_verify_lesm_fw_enabled_raptor(hw)) {\n-\t\tmac->setup_link = txgbe_setup_mac_link_smartspeed;\n \t} else {\n \t\tmac->setup_link = txgbe_setup_mac_link;\n+\t\tmac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;\n \t}\n }\n \n@@ -3309,13 +3258,11 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,\n \tu64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;\n \tu64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;\n \tu64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;\n-\tu64 current_autoc = autoc;\n \tu64 orig_autoc = 0;\n-\tu32 links_reg;\n-\tu32 i;\n \tu32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;\n \n \tDEBUGFUNC(\"txgbe_setup_mac_link\");\n+\tUNREFERENCED_PARAMETER(autoneg_wait_to_complete);\n \n \t/* Check to see if speed passed in is supported. */\n \tstatus = hw->mac.get_link_capabilities(hw,\n@@ -3346,8 +3293,7 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,\n \t\tif (speed & TXGBE_LINK_SPEED_10GB_FULL) {\n \t\t\tif (orig_autoc & TXGBE_AUTOC_KX4_SUPP)\n \t\t\t\tautoc |= TXGBE_AUTOC_KX4_SUPP;\n-\t\t\tif ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&\n-\t\t\t    !hw->phy.smart_speed_active)\n+\t\t\tif (orig_autoc & TXGBE_AUTOC_KR_SUPP)\n \t\t\t\tautoc |= TXGBE_AUTOC_KR_SUPP;\n \t\t}\n \t\tif (speed & TXGBE_LINK_SPEED_1GB_FULL)\n@@ -3374,35 +3320,14 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,\n \t\t}\n \t}\n \n-\tif (autoc == current_autoc)\n-\t\treturn status;\n-\n \tautoc &= ~TXGBE_AUTOC_SPEED_MASK;\n \tautoc |= TXGBE_AUTOC_SPEED(speed);\n+\tautoc &= ~TXGBE_AUTOC_AUTONEG;\n \tautoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);\n \n \t/* Restart link */\n \thw->mac.autoc_write(hw, autoc);\n \n-\t/* Only poll for autoneg to complete if specified to do so */\n-\tif (autoneg_wait_to_complete) {\n-\t\tif (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||\n-\t\t    link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n-\t\t    link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n-\t\t\tlinks_reg = 0; /*Just in case Autoneg time=0*/\n-\t\t\tfor (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {\n-\t\t\t\tlinks_reg = rd32(hw, TXGBE_PORTSTAT);\n-\t\t\t\tif (links_reg & TXGBE_PORTSTAT_UP)\n-\t\t\t\t\tbreak;\n-\t\t\t\tmsec_delay(100);\n-\t\t\t}\n-\t\t\tif (!(links_reg & TXGBE_PORTSTAT_UP)) {\n-\t\t\t\tstatus = TXGBE_ERR_AUTONEG_NOT_COMPLETE;\n-\t\t\t\tDEBUGOUT(\"Autoneg did not complete.\\n\");\n-\t\t\t}\n-\t\t}\n-\t}\n-\n \t/* Add delay to filter out noises during initial link setup */\n \tmsec_delay(50);\n \n@@ -3515,6 +3440,7 @@ txgbe_reset_misc(struct txgbe_hw *hw)\n \t/* enable mac transmitter */\n \twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);\n \n+\thw->mac.autoc = hw->mac.orig_autoc;\n \tfor (i = 0; i < 4; i++)\n \t\twr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);\n }\n@@ -3608,7 +3534,6 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)\n \t */\n \tif (!hw->mac.orig_link_settings_stored) {\n \t\thw->mac.orig_autoc = hw->mac.autoc_read(hw);\n-\t\thw->mac.autoc_write(hw, hw->mac.orig_autoc);\n \t\thw->mac.orig_link_settings_stored = true;\n \t} else {\n \t\thw->mac.orig_autoc = autoc;\ndiff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h\nindex e18e400af..074d7a306 100644\n--- a/drivers/net/txgbe/base/txgbe_osdep.h\n+++ b/drivers/net/txgbe/base/txgbe_osdep.h\n@@ -36,6 +36,7 @@\n #define msec_delay(x) rte_delay_ms(x)\n #define usleep(x)     rte_delay_us(x)\n #define msleep(x)     rte_delay_ms(x)\n+#define usec_stamp()    (rte_get_timer_cycles() * 1000000 / rte_get_timer_hz())\n \n #define FALSE               0\n #define TRUE                1\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c\nindex 1ca6e35a4..33d3839ed 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.c\n+++ b/drivers/net/txgbe/base/txgbe_phy.c\n@@ -9,6 +9,7 @@\n \n static void txgbe_i2c_start(struct txgbe_hw *hw);\n static void txgbe_i2c_stop(struct txgbe_hw *hw);\n+static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);\n \n /**\n  * txgbe_identify_extphy - Identify a single address for a PHY\n@@ -1416,6 +1417,7 @@ static s32\n txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)\n {\n \tu32 i;\n+\tu16 value;\n \ts32 err = 0;\n \n \t/* 1. Wait xpcs power-up good */\n@@ -1430,18 +1432,33 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)\n \t\terr = TXGBE_ERR_XPCS_POWER_UP_FAILED;\n \t\tgoto out;\n \t}\n+\tBP_LOG(\"It is set to kr.\\n\");\n+\n+\twr32_epcs(hw, VR_AN_INTR_MSK, 0x7);\n+\twr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);\n+\twr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);\n \n \tif (!autoneg) {\n \t\t/* 2. Disable xpcs AN-73 */\n-\t\twr32_epcs(hw, SR_AN_CTRL, 0x0);\n-\t\t/* Disable PHY MPLLA for eth mode change(after ECO) */\n-\t\twr32_ephy(hw, 0x4, 0x243A);\n-\t\ttxgbe_flush(hw);\n-\t\tmsec_delay(1);\n-\t\t/* Set the eth change_mode bit first in mis_rst register\n-\t\t * for corresponding LAN port\n-\t\t */\n-\t\twr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));\n+\t\twr32_epcs(hw, SR_AN_CTRL,\n+\t\t\tSR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP);\n+\n+\t\twr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET);\n+\n+\t\tif (!(hw->devarg.auto_neg == 1)) {\n+\t\t\twr32_epcs(hw, SR_AN_CTRL, 0);\n+\t\t\twr32_epcs(hw, VR_AN_KR_MODE_CL, 0);\n+\t\t}\n+\t\tif (hw->devarg.present  == 1) {\n+\t\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\t\tvalue |= TXGBE_PHY_TX_EQ_CTL1_DEF;\n+\t\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t\t}\n+\t\tif (hw->devarg.poll == 1) {\n+\t\t\twr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0,\n+\t\t\t\tVR_PMA_KRTR_TIMER_MAX_WAIT);\n+\t\t\twr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697);\n+\t\t}\n \n \t\t/* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register\n \t\t * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)\n@@ -1501,6 +1518,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)\n \tif (hw->link_status == TXGBE_LINK_STATUS_KX4)\n \t\tgoto out;\n \n+\tBP_LOG(\"It is set to kx4.\\n\");\n+\twr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0);\n+\twr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0);\n+\n \t/* 1. Wait xpcs power-up good */\n \tfor (i = 0; i < 100; i++) {\n \t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n@@ -1545,16 +1566,13 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)\n \twr32_epcs(hw, SR_PMA_CTRL1,\n \t\t\tSR_PMA_CTRL1_SS13_KX4);\n \n-\tvalue = (0xf5f0 & ~0x7F0) |  (0x5 << 8) | (0x7 << 5) | 0x10;\n+\tvalue = (0xf5f0 & ~0x7F0) |  (0x5 << 8) | (0x7 << 5) | 0xF0;\n \twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n \n-\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n-\n-\tvalue = (0x1804 & ~0x3F3F);\n-\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n-\n-\tvalue = (0x50 & ~0x7F) | 40 | (1 << 6);\n-\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\tif ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI)\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n+\telse\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n \n \tfor (i = 0; i < 4; i++) {\n \t\tif (i == 0)\n@@ -1682,6 +1700,13 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)\n \t\tgoto out;\n \t}\n \n+\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\t\tvalue = (0x1804 & ~0x3F3F);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = (0x50 & ~0x7F) | 40 | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t}\n out:\n \treturn err;\n }\n@@ -1700,6 +1725,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,\n \tif (hw->link_status == TXGBE_LINK_STATUS_KX)\n \t\tgoto out;\n \n+\tBP_LOG(\"It is set to kx. speed =0x%x\\n\", speed);\n+\twr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);\n+\twr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);\n+\n \t/* 1. Wait xpcs power-up good */\n \tfor (i = 0; i < 100; i++) {\n \t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n@@ -1756,16 +1785,13 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,\n \twr32_epcs(hw, SR_MII_MMD_CTL,\n \t\t\twdata);\n \n-\tvalue = (0xf5f0 & ~0x710) |  (0x5 << 8);\n+\tvalue = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10;\n \twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n \n-\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n-\n-\tvalue = (0x1804 & ~0x3F3F) | (24 << 8) | 4;\n-\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n-\n-\tvalue = (0x50 & ~0x7F) | 16 | (1 << 6);\n-\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\tif (hw->devarg.sgmii == 1)\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n+\telse\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n \n \tfor (i = 0; i < 4; i++) {\n \t\tif (i) {\n@@ -1881,6 +1907,13 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,\n \t\tgoto out;\n \t}\n \n+\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\t\tvalue = (0x1804 & ~0x3F3F) | (24 << 8) | 4;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = (0x50 & ~0x7F) | 16 | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t}\n out:\n \treturn err;\n }\n@@ -1977,18 +2010,7 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n \t\t * MPLLA_DIV8_CLK_EN=0\n \t\t */\n \t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);\n-\t\t/* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register\n-\t\t * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4\n-\t\t */\n-\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n-\t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n-\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n-\t\t/* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register\n-\t\t * Bit[6](TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36\n-\t\t */\n-\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n-\t\tvalue = (value & ~0x7F) | 16 | (1 << 6);\n-\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\n \t\tif (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||\n \t\t\thw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {\n \t\t\t/* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register\n@@ -2055,18 +2077,7 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n \t\t * Bit[12:8](RX_VREF_CTRL) = 5'hF\n \t\t */\n \t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n-\t\t/* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register\n-\t\t * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4\n-\t\t */\n-\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n-\t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n-\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n-\t\t/* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register Bit[6]\n-\t\t * (TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36\n-\t\t */\n-\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n-\t\tvalue = (value & ~0x7F) | 16 | (1 << 6);\n-\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\n \t\tif (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||\n \t\t\thw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {\n \t\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);\n@@ -2123,6 +2134,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n \t\tgoto out;\n \t}\n \n+\tif (hw->fw_version <= TXGBE_FW_N_TXEQ) {\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n+\t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\tvalue = (value & ~0x7F) | 16 | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t}\n out:\n \treturn err;\n }\n@@ -2133,13 +2153,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n  */\n u64 txgbe_autoc_read(struct txgbe_hw *hw)\n {\n-\tu64 autoc = 0;\n+\tu64 autoc;\n \tu32 sr_pcs_ctl;\n \tu32 sr_pma_ctl1;\n \tu32 sr_an_ctl;\n \tu32 sr_an_adv_reg2;\n \tu8 type = hw->subsystem_device_id & 0xFF;\n \n+\tautoc = hw->mac.autoc;\n+\n \tif (hw->phy.multispeed_fiber) {\n \t\tautoc |= TXGBE_AUTOC_LMS_10G;\n \t} else if (type == TXGBE_DEV_ID_SFP) {\n@@ -2195,11 +2217,11 @@ u64 txgbe_autoc_read(struct txgbe_hw *hw)\n \t} else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {\n \t\t/* KX/KX4/KR backplane auto-negotiation enable */\n \t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)\n-\t\t\tautoc |= TXGBE_AUTOC_10G_KR;\n+\t\t\tautoc |= TXGBE_AUTOC_KR_SUPP;\n \t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)\n-\t\t\tautoc |= TXGBE_AUTOC_10G_KX4;\n+\t\t\tautoc |= TXGBE_AUTOC_KX4_SUPP;\n \t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)\n-\t\t\tautoc |= TXGBE_AUTOC_1G_KX;\n+\t\t\tautoc |= TXGBE_AUTOC_KX_SUPP;\n \t\tautoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;\n \t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |\n \t\t\t\tTXGBE_PHYSICAL_LAYER_10GBASE_KX4 |\n@@ -2221,7 +2243,7 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)\n \tu32 mactxcfg = 0;\n \tu8 device_type = hw->subsystem_device_id & 0xFF;\n \n-\tspeed = TXGBE_AUTOC_SPEED(autoc);\n+\tspeed = TXGBD_AUTOC_SPEED(autoc);\n \tautoc &= ~TXGBE_AUTOC_SPEED_MASK;\n \tautoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);\n \tautoc &= ~TXGBE_AUTOC_AUTONEG;\n@@ -2241,6 +2263,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)\n \t\t\tdefault:\n \t\t\t\treturn;\n \t\t\t}\n+\t\t} else {\n+\t\t\ttxgbe_set_link_to_kr(hw, !autoneg);\n \t\t}\n \t} else if (device_type == TXGBE_DEV_ID_XAUI ||\n \t\t   device_type == TXGBE_DEV_ID_SGMII ||\n@@ -2249,10 +2273,11 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)\n \t\t   (device_type == TXGBE_DEV_ID_SFI_XAUI &&\n \t\t   hw->phy.media_type == txgbe_media_type_copper)) {\n \t\tif (speed == TXGBE_LINK_SPEED_10GB_FULL) {\n-\t\t\ttxgbe_set_link_to_kx4(hw, autoneg);\n+\t\t\ttxgbe_set_link_to_kx4(hw, 0);\n \t\t} else {\n \t\t\ttxgbe_set_link_to_kx(hw, speed, 0);\n-\t\t\ttxgbe_set_sgmii_an37_ability(hw);\n+\t\t\tif (hw->devarg.auto_neg == 1)\n+\t\t\t\ttxgbe_set_sgmii_an37_ability(hw);\n \t\t}\n \t} else if (hw->phy.media_type == txgbe_media_type_fiber) {\n \t\ttxgbe_set_link_to_sfi(hw, speed);\n@@ -2264,6 +2289,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)\n \t\tmactxcfg = TXGBE_MACTXCFG_SPEED_1G;\n \n \t/* enable mac transmitter */\n-\twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_SPEED_MASK, mactxcfg);\n+\twr32m(hw, TXGBE_MACTXCFG,\n+\t\tTXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE,\n+\t\tmactxcfg | TXGBE_MACTXCFG_TXE);\n }\n \ndiff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h\nindex 4a5b90077..b804d2406 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.h\n+++ b/drivers/net/txgbe/base/txgbe_phy.h\n@@ -18,11 +18,27 @@\n #define   SR_PCS_CTRL2_TYPE_SEL_R       LS16(0, 0, 0x3)\n #define   SR_PCS_CTRL2_TYPE_SEL_X       LS16(1, 0, 0x3)\n #define   SR_PCS_CTRL2_TYPE_SEL_W       LS16(2, 0, 0x3)\n+#define SR_XS_PCS_KR_STS1\t\t0x030020\n+#define   SR_XS_PCS_KR_STS1_PLU\t\tMS16(12, 0x1)\n #define SR_PMA_CTRL1                    0x010000\n #define   SR_PMA_CTRL1_SS13             MS16(13, 0x1)\n #define   SR_PMA_CTRL1_SS13_KX          LS16(0, 13, 0x1)\n #define   SR_PMA_CTRL1_SS13_KX4         LS16(1, 13, 0x1)\n #define   SR_PMA_CTRL1_LB               MS16(0, 0x1)\n+#define SR_PMA_KR_PMD_CTRL\t\t0x010096\n+#define   SR_PMA_KR_PMD_CTRL_EN_TR\tMS16(1, 0x1)\n+#define   SR_PMA_KR_PMD_CTRL_RS_TR\tMS16(0, 0x1)\n+#define SR_PMA_KR_PMD_STS\t\t0x010097\n+#define   SR_PMA_KR_PMD_STS_TR_FAIL\tMS16(3, 0x1)\n+#define   SR_PMA_KR_PMD_STS_RCV\t\tMS16(0, 0x1)\n+#define SR_PMA_KR_LP_CEU\t\t0x010098\n+#define SR_PMA_KR_LP_CESTS\t\t0x010099\n+#define   SR_PMA_KR_LP_CESTS_RR\t\tMS16(15, 0x1)\n+#define SR_PMA_KR_LD_CEU\t\t0x01009A\n+#define SR_PMA_KR_LD_CESTS\t\t0x01009B\n+#define   SR_PMA_KR_LD_CESTS_RR\t\tMS16(15, 0x1)\n+#define SR_PMA_KR_FEC_CTRL              0x0100AB\n+#define   SR_PMA_KR_FEC_CTRL_EN\t\tMS16(0, 0x1)\n #define SR_MII_MMD_CTL                  0x1F0000\n #define   SR_MII_MMD_CTL_AN_EN              0x1000\n #define   SR_MII_MMD_CTL_RESTART_AN         0x0200\n@@ -33,26 +49,80 @@\n #define   SR_MII_MMD_AN_ADV_PAUSE_ASM   0x80\n #define   SR_MII_MMD_AN_ADV_PAUSE_SYM   0x100\n #define SR_MII_MMD_LP_BABL              0x1F0005\n+\n+#define BP_TYPE_KX\t\t0x20\n+#define BP_TYPE_KX4\t\t0x40\n+#define BP_TYPE_KX4_KX\t\t0x60\n+#define BP_TYPE_KR\t\t0x80\n+#define BP_TYPE_KR_KX\t\t0xA0\n+#define BP_TYPE_KR_KX4\t\t0xC0\n+#define BP_TYPE_KR_KX4_KX\t0xE0\n+\n #define SR_AN_CTRL                      0x070000\n #define   SR_AN_CTRL_RSTRT_AN           MS16(9, 0x1)\n #define   SR_AN_CTRL_AN_EN              MS16(12, 0x1)\n+#define   SR_AN_CTRL_EXT_NP             MS16(13, 0x1)\n #define SR_AN_MMD_ADV_REG1                0x070010\n #define   SR_AN_MMD_ADV_REG1_PAUSE(v)      ((0x3 & (v)) << 10)\n #define   SR_AN_MMD_ADV_REG1_PAUSE_SYM      0x400\n #define   SR_AN_MMD_ADV_REG1_PAUSE_ASM      0x800\n-#define SR_AN_MMD_ADV_REG2                0x070011\n-#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KX4    0x40\n-#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KX     0x20\n-#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KR     0x80\n-#define   SR_AN_MMD_ADV_REG2_BP_TYPE_MASK   0xFFFF\n+#define   SR_AN_MMD_ADV_REG1_NP(v)\t  RS16(v, 15, 0x1)\n+#define SR_AN_MMD_ADV_REG2\t\t  0x070011\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KX4\tBP_TYPE_KX4\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KX\t\tBP_TYPE_KX\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KR\t\tBP_TYPE_KR\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KX4_KX\tBP_TYPE_KX4_KX\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX\tBP_TYPE_KR_KX\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4\tBP_TYPE_KR_KX4\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX\tBP_TYPE_KR_KX4_KX\n+#define   SR_AN_MMD_ADV_REG2_BP_TYPE_MASK\t0xFFFF\n+#define SR_AN_MMD_ADV_REG3                0x070012\n+#define   SR_AN_MMD_ADV_REG3_FCE(v)\t  RS16(v, 14, 0x3)\n #define SR_AN_MMD_LP_ABL1                 0x070013\n+#define   SR_MMD_LP_ABL1_ADV_NP(v)\t  RS16(v, 15, 0x1)\n+#define SR_AN_MMD_LP_ABL2\t\t  0x070014\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KX4\t\tBP_TYPE_KX4\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KX\t\tBP_TYPE_KX\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KR\t\tBP_TYPE_KR\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KX4_KX\tBP_TYPE_KX4_KX\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX\tBP_TYPE_KR_KX\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4\tBP_TYPE_KR_KX4\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX\tBP_TYPE_KR_KX4_KX\n+#define   SR_AN_MMD_LP_ABL2_BP_TYPE_MASK\t0xFFFF\n+#define SR_AN_MMD_LP_ABL3\t\t  0x070015\n+#define   SR_AN_MMD_LP_ABL3_FCE(v)\t  RS16(v, 14, 0x3)\n+#define SR_AN_XNP_TX1\t\t\t  0x070016\n+#define   SR_AN_XNP_TX1_NP\t\t  MS16(15, 0x1)\n+#define SR_AN_LP_XNP_ABL1\t\t  0x070019\n+#define   SR_AN_LP_XNP_ABL1_NP(v)\t  RS16(v, 15, 0x1)\n+\n+#define VR_AN_INTR_MSK\t\t\t  0x078001\n+#define   VR_AN_INTR_CMPLT_IE\t\t  MS16(0, 0x1)\n+#define   VR_AN_INTR_LINK_IE\t\t  MS16(1, 0x1)\n+#define   VR_AN_INTR_PG_RCV_IE\t\t  MS16(2, 0x1)\n+#define VR_AN_INTR\t\t\t  0x078002\n+#define   VR_AN_INTR_CMPLT\t\t  MS16(0, 0x1)\n+#define   VR_AN_INTR_LINK\t\t  MS16(1, 0x1)\n+#define   VR_AN_INTR_PG_RCV\t\t  MS16(2, 0x1)\n #define VR_AN_KR_MODE_CL                  0x078003\n+#define   VR_AN_KR_MODE_CL_PDET\t\t  MS16(0, 0x1)\n #define VR_XS_OR_PCS_MMD_DIGI_CTL1        0x038000\n #define   VR_XS_OR_PCS_MMD_DIGI_CTL1_ENABLE 0x1000\n #define   VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST 0x8000\n+#define VR_XS_OR_PCS_MMD_DIGI_CTL2        0x038001\n #define VR_XS_OR_PCS_MMD_DIGI_STATUS      0x038010\n #define   VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK            0x1C\n #define   VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD      0x10\n+#define VR_PMA_KRTR_PRBS_CTRL0\t\t  0x018003\n+#define   VR_PMA_KRTR_PRBS31_EN\t\t  MS16(1, 0x1)\n+#define   VR_PMA_KRTR_PRBS_MODE_EN\t  MS16(0, 0x1)\n+#define VR_PMA_KRTR_PRBS_CTRL1\t\t  0x018004\n+#define   VR_PMA_KRTR_PRBS_TIME_LMT\t  MS16(0, 0xFFFF)\n+#define VR_PMA_KRTR_PRBS_CTRL2\t\t  0x018005\n+#define   VR_PMA_KRTR_PRBS_ERR_LIM\t  MS16(0, 0x2FFF)\n+#define VR_PMA_KRTR_TIMER_CTRL0\t\t  0x018006\n+#define   VR_PMA_KRTR_TIMER_MAX_WAIT\t  MS16(0, 0xFFFF)\n+#define VR_PMA_KRTR_TIMER_CTRL2\t\t  0x018008\n \n #define TXGBE_PHY_MPLLA_CTL0                    0x018071\n #define TXGBE_PHY_MPLLA_CTL3                    0x018077\n@@ -71,6 +141,7 @@\n #define TXGBE_PHY_RX_EQ_CTL                     0x01805C\n #define TXGBE_PHY_TX_EQ_CTL0                    0x018036\n #define TXGBE_PHY_TX_EQ_CTL1                    0x018037\n+#define   TXGBE_PHY_TX_EQ_CTL1_DEF\t\tMS16(7, 0x1)\n #define TXGBE_PHY_TX_RATE_CTL                   0x018034\n #define TXGBE_PHY_RX_RATE_CTL                   0x018054\n #define TXGBE_PHY_TX_GEN_CTL2                   0x018032\n@@ -80,12 +151,14 @@\n #define TXGBE_PHY_RX_POWER_ST_CTL               0x018055\n #define TXGBE_PHY_TX_POWER_ST_CTL               0x018035\n #define TXGBE_PHY_TX_GENCTRL1                   0x018031\n+#define TXGBE_PHY_EQ_INIT_CTL0\t\t\t0x01803A\n+#define TXGBE_PHY_EQ_INIT_CTL1\t\t\t0x01803B\n \n #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX              32\n #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_10GBASER_KR             33\n #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER                   40\n #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_MASK                    0xFF\n-#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX           0x46\n+#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX           0x56\n #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR          0x7B\n #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER                0x56\n #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_MASK                 0x7FF\n@@ -151,6 +224,11 @@\n #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10                      0x200\n #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_16P5                    0x400\n #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_MASK                    0x700\n+#define TXGBE_PHY_LANE0_TX_EQ_CTL1\t\t\t\t0x100E\n+#define   TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(v)\t\t\tRS16(v, 6, 0x3F)\n+#define TXGBE_PHY_LANE0_TX_EQ_CTL2\t\t\t\t0x100F\n+#define   TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE\t\t\tMS16(0, 0x3F)\n+#define   TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(v)\t\t\tRS16(v, 6, 0x3F)\n \n /******************************************************************************\n  * SFP I2C Registers:\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 89d68d81f..a50e7b154 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -617,9 +617,10 @@ struct txgbe_mac_info {\n \tu32 rx_pb_size;\n \tu32 max_tx_queues;\n \tu32 max_rx_queues;\n+\tu64 autoc;\n+\tu64 orig_autoc;  /* cached value of AUTOC */\n \tu8  san_mac_rar_index;\n \tbool get_link_status;\n-\tu64 orig_autoc;  /* cached value of AUTOC */\n \tbool orig_link_settings_stored;\n \tbool autotry_restart;\n \tu8 flags;\ndiff --git a/drivers/net/txgbe/txgbe_logs.h b/drivers/net/txgbe/txgbe_logs.h\nindex f44ca06ee..da059d7d2 100644\n--- a/drivers/net/txgbe/txgbe_logs.h\n+++ b/drivers/net/txgbe/txgbe_logs.h\n@@ -51,4 +51,14 @@ extern int txgbe_logtype_tx_free;\n #define PMD_INIT_FUNC_TRACE()     TLOG_DEBUG(\" >>\")\n #define DEBUGFUNC(fmt)            TLOG_DEBUG(fmt)\n \n+#undef TXGBE_DEBUG_BP\n+#ifdef TXGBE_DEBUG_BP\n+#define BP_LOG(fmt, ...) \\\n+\t\tRTE_LOG(CRIT, PMD, \"[%lu.%lu]%s(%d): \" fmt, \\\n+\t\t\tusec_stamp() / 1000000, usec_stamp() % 1000000, \\\n+\t\t\t__func__, __LINE__, ## __VA_ARGS__)\n+#else\n+#define BP_LOG(fmt, ...) do { } while (0)\n+#endif\n+\n #endif /* _TXGBE_LOGS_H_ */\n",
    "prefixes": [
        "v2",
        "4/7"
    ]
}