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GET /api/patches/88246/?format=api
{ "id": 88246, "url": "https://patches.dpdk.org/api/patches/88246/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210225182250.1149592-8-thomas@monjalon.net/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210225182250.1149592-8-thomas@monjalon.net>", "list_archive_url": "https://inbox.dpdk.org/dev/20210225182250.1149592-8-thomas@monjalon.net", "date": "2021-02-25T18:22:40", "name": "[v5,07/17] drivers: replace page size definitions with function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4a0eaa2e7ea47fcc119a2a0007e4912551d0a52d", "submitter": { "id": 685, "url": "https://patches.dpdk.org/api/people/685/?format=api", "name": "Thomas Monjalon", "email": "thomas@monjalon.net" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210225182250.1149592-8-thomas@monjalon.net/mbox/", "series": [ { "id": 15388, "url": "https://patches.dpdk.org/api/series/15388/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=15388", "date": "2021-02-25T18:22:33", "name": "Alpine/musl build support", "version": 5, "mbox": "https://patches.dpdk.org/series/15388/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/88246/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/88246/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 24780A034F;\n\tThu, 25 Feb 2021 19:24:13 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2D72416085C;\n\tThu, 25 Feb 2021 19:23:39 +0100 (CET)", "from new4-smtp.messagingengine.com (new4-smtp.messagingengine.com\n [66.111.4.230]) by mails.dpdk.org (Postfix) with ESMTP id A555C16084E\n for <dev@dpdk.org>; Thu, 25 Feb 2021 19:23:37 +0100 (CET)", "from compute2.internal (compute2.nyi.internal [10.202.2.42])\n by mailnew.nyi.internal (Postfix) with ESMTP id 5239A5803FE;\n Thu, 25 Feb 2021 13:23:37 -0500 (EST)", "from mailfrontend1 ([10.202.2.162])\n by compute2.internal (MEProxy); Thu, 25 Feb 2021 13:23:37 -0500", "from xps.monjalon.net (184.203.134.77.rev.sfr.net [77.134.203.184])\n by mail.messagingengine.com (Postfix) with ESMTPA id E3483240065;\n Thu, 25 Feb 2021 13:23:34 -0500 (EST)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding; s=fm3; bh=8gpzf0Sjg0pFg\n z0tirn8khUVRosbgkJrdOOzJgHtKUA=; b=RK9tlDNtaKjISNuE7jxlHyOgPE4A+\n VWsTfQFFq5H5WvVWVI96oBslFYzSx/wnzu+87g/r16KyfcUfDFaKBNMTUa1FBzeo\n f/8cQXQo4mN/fwZwPeW34pzGv62sRQ2Cv7/8BSPcFkwnwihJ0J6TP5uKH/S4UWsM\n L21tH+CrHSaDAFN50hYTDZ3Nkrjaon+6Zi+DVlB70Qg4iEHmzxhaj6cjsHN3XE9+\n g9lPHuSVbpbzJHWd4zUDjZHM0oXhxyeA2PjnKTfVLu4XyN6SQt+UvwTaYHoXA7ok\n +eebcld4fTdIJ5pcNZgciH/yIOjSCcWhIow4qqTc3rruKg2qLXQ4reCqA==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n messagingengine.com; h=cc:content-transfer-encoding:date:from\n :in-reply-to:message-id:mime-version:references:subject:to\n :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=\n fm2; bh=8gpzf0Sjg0pFgz0tirn8khUVRosbgkJrdOOzJgHtKUA=; b=nIuQAl6f\n fTsmt8Tpyoai1AiL/bh0r4JVLM4ejevmwPkJDHhzu0tuX1TpUrbB9ZADb7uxPqaU\n 4zTb9/DEvkk4OkxsGevJwnLK0y/ddo/3FeUDxoUAQgFnxS4grQO+Hyemy+dVwxmw\n BvsAMUK4X5wy+b8UgUh6TbJqADV3VQQaee5QPgUejsmHx/Lw8YF8neavqYF1PfBA\n HFt1EHVB5NB1XlwG23xncS6DkARkB4RQXNrNe4dPSE52GYJuMdXxvcdBm9+8zx92\n Bgm7XvxNBI/wwtqZwFFqjTaFMEdmqI8/smyIIcrdUeMlMioywqV7s7XIb9U7eKg7\n YdG9tXAGFG21Bg==" ], "X-ME-Sender": "<xms:KOs3YBccCQVnqoI0Gtd3kWfmFoDffYDhtuCDOFgJl834c80wbBug0w>\n <xme:KOs3YPO7R3M9_3VUpYqhG2qdpwB3P4sskRhNqunXddpAazoAPxyfICd6VNwZ2wjdB\n s5GOkFdcWhwaGALpA>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgeduledrkeelgdduudegucetufdoteggodetrfdotf\n fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen\n uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne\n cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefvhhhomhgr\n shcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjhgrlhhonhdrnhgvtheqnecugg\n ftrfgrthhtvghrnhepheefieekleefieeljedtvdehgeejvdevfedufeetleejfeethfel\n gfffudektdeunecuffhomhgrihhnpehpmhgurdhnvghtnecukfhppeejjedrudefgedrvd\n dtfedrudekgeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhr\n ohhmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght", "X-ME-Proxy": "<xmx:KOs3YKiwy30Q_Pps5d05IdGz4gpxxFmyYQhVk0qCnTr9MWw9Qjp7oQ>\n <xmx:KOs3YK-TNGA2x0I4Yo0zcPS4bq9ndeZp5GXnhd5rhyajIiZXNmSd3A>\n <xmx:KOs3YNvfqVbTloqKh1DLt5xy4MthNY-k6IB_bQYp0pqd0Pkup20O1Q>\n <xmx:Kes3YOkehHSTslULZ2e53U6cpOiZluusuCJELEKcP7aW3o5-aiu2rg>", "From": "Thomas Monjalon <thomas@monjalon.net>", "To": "dev@dpdk.org", "Cc": "ncopa@alpinelinux.org, Anatoly Burakov <anatoly.burakov@intel.com>,\n Stephen Hemminger <sthemmin@microsoft.com>, Long Li <longli@microsoft.com>,\n Jay Zhou <jianjay.zhou@huawei.com>,\n Timothy McDaniel <timothy.mcdaniel@intel.com>,\n Rasesh Mody <rmody@marvell.com>, Shahed Shaikh <shshaikh@marvell.com>,\n Andrew Boyer <aboyer@pensando.io>,\n Maxime Coquelin <maxime.coquelin@redhat.com>,\n Chenbo Xia <chenbo.xia@intel.com>, Xiao Wang <xiao.w.wang@intel.com>", "Date": "Thu, 25 Feb 2021 19:22:40 +0100", "Message-Id": "<20210225182250.1149592-8-thomas@monjalon.net>", "X-Mailer": "git-send-email 2.30.1", "In-Reply-To": "<20210225182250.1149592-1-thomas@monjalon.net>", "References": "<20190313170657.16688-1-ncopa@alpinelinux.org>\n <20210225182250.1149592-1-thomas@monjalon.net>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 07/17] drivers: replace page size definitions\n with function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The page size is often retrieved from the macro PAGE_SIZE.\nIf PAGE_SIZE is not defined, it is either using hard coded default,\nor getting the system value from the UNIX-only function sysconf().\n\nSuch definitions are replaced with the generic function\nrte_mem_page_size() defined for each supported OS.\n\nRemoving PAGE_SIZE definitions will fix dlb drivers for musl libc,\nbecause #ifdef checks were missing, causing redefinition errors.\n\nSigned-off-by: Thomas Monjalon <thomas@monjalon.net>\n---\n drivers/bus/pci/linux/pci_vfio.c | 9 ++-------\n drivers/bus/vmbus/linux/vmbus_uio.c | 4 ++--\n drivers/bus/vmbus/private.h | 5 +----\n drivers/bus/vmbus/rte_vmbus_reg.h | 2 +-\n drivers/bus/vmbus/vmbus_common_uio.c | 4 ++--\n drivers/crypto/virtio/virtio_pci.h | 3 ++-\n drivers/event/dlb/dlb.c | 7 +++++--\n drivers/event/dlb/dlb_priv.h | 2 --\n drivers/event/dlb/pf/base/dlb_osdep.h | 2 +-\n drivers/event/dlb/pf/dlb_main.h | 5 +----\n drivers/event/dlb/pf/dlb_pf.c | 10 ++++++----\n drivers/event/dlb2/dlb2_priv.h | 2 --\n drivers/event/dlb2/pf/base/dlb2_osdep.h | 2 +-\n drivers/event/dlb2/pf/dlb2_main.h | 5 +----\n drivers/event/dlb2/pf/dlb2_pf.c | 8 ++++----\n drivers/net/bnx2x/ecore_fw_defs.h | 18 ++++++++++++------\n drivers/net/ionic/ionic_lif.c | 25 ++++++++++++++-----------\n drivers/net/ionic/ionic_main.c | 3 ++-\n drivers/net/ionic/ionic_osdep.h | 2 +-\n drivers/net/netvsc/hn_rndis.c | 12 ++++++------\n drivers/net/netvsc/hn_rxtx.c | 10 ++++++----\n drivers/net/netvsc/hn_var.h | 9 +++------\n drivers/net/virtio/virtio.h | 2 +-\n drivers/net/virtio/virtio_ethdev.c | 6 +++---\n drivers/net/virtio/virtio_ethdev.h | 4 ----\n drivers/vdpa/ifc/ifcvf_vdpa.c | 17 +++++++----------\n 26 files changed, 84 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c\nindex e3f7b6abeb..9d689d6fd9 100644\n--- a/drivers/bus/pci/linux/pci_vfio.c\n+++ b/drivers/bus/pci/linux/pci_vfio.c\n@@ -38,11 +38,6 @@\n \n #ifdef VFIO_PRESENT\n \n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n-#endif\n-#define PAGE_MASK (~(PAGE_SIZE - 1))\n-\n static struct rte_tailq_elem rte_vfio_tailq = {\n \t.name = \"VFIO_RESOURCE_LIST\",\n };\n@@ -507,8 +502,8 @@ pci_vfio_mmap_bar(int vfio_dev_fd, struct mapped_pci_resource *vfio_res,\n \t\t */\n \t\tuint32_t table_start = msix_table->offset;\n \t\tuint32_t table_end = table_start + msix_table->size;\n-\t\ttable_end = RTE_ALIGN(table_end, PAGE_SIZE);\n-\t\ttable_start = RTE_ALIGN_FLOOR(table_start, PAGE_SIZE);\n+\t\ttable_end = RTE_ALIGN(table_end, rte_mem_page_size());\n+\t\ttable_start = RTE_ALIGN_FLOOR(table_start, rte_mem_page_size());\n \n \t\t/* If page-aligned start of MSI-X table is less than the\n \t\t * actual MSI-X table start address, reassign to the actual\ndiff --git a/drivers/bus/vmbus/linux/vmbus_uio.c b/drivers/bus/vmbus/linux/vmbus_uio.c\nindex 5dc0c47de6..b52ca5bf1d 100644\n--- a/drivers/bus/vmbus/linux/vmbus_uio.c\n+++ b/drivers/bus/vmbus/linux/vmbus_uio.c\n@@ -154,7 +154,7 @@ vmbus_uio_map_resource_by_index(struct rte_vmbus_device *dev, int idx,\n \t\tvmbus_map_addr = vmbus_find_max_end_va();\n \n \t/* offset is special in uio it indicates which resource */\n-\toffset = idx * PAGE_SIZE;\n+\toffset = idx * rte_mem_page_size();\n \n \tmapaddr = vmbus_map_resource(vmbus_map_addr, fd, offset, size, flags);\n \tclose(fd);\n@@ -224,7 +224,7 @@ static int vmbus_uio_map_subchan(const struct rte_vmbus_device *dev,\n \t}\n \tfile_size = sb.st_size;\n \n-\tif (file_size == 0 || (file_size & (PAGE_SIZE - 1))) {\n+\tif (file_size == 0 || (file_size & (rte_mem_page_size() - 1))) {\n \t\tVMBUS_LOG(ERR, \"incorrect size %s: %zu\",\n \t\t\t ring_path, file_size);\n \ndiff --git a/drivers/bus/vmbus/private.h b/drivers/bus/vmbus/private.h\nindex f19b14e4a6..528d60a42f 100644\n--- a/drivers/bus/vmbus/private.h\n+++ b/drivers/bus/vmbus/private.h\n@@ -9,13 +9,10 @@\n #include <stdbool.h>\n #include <sys/uio.h>\n #include <rte_log.h>\n+#include <rte_eal_paging.h>\n #include <rte_vmbus_reg.h>\n #include <rte_bus_vmbus.h>\n \n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE\t4096\n-#endif\n-\n extern struct rte_vmbus_bus rte_vmbus_bus;\n \n extern int vmbus_logtype_bus;\ndiff --git a/drivers/bus/vmbus/rte_vmbus_reg.h b/drivers/bus/vmbus/rte_vmbus_reg.h\nindex f5a0693dcb..8562672979 100644\n--- a/drivers/bus/vmbus/rte_vmbus_reg.h\n+++ b/drivers/bus/vmbus/rte_vmbus_reg.h\n@@ -100,7 +100,7 @@ struct vmbus_bufring {\n \t\tuint32_t value;\n \t} feature_bits;\n \n-\t/* Pad it to PAGE_SIZE so that data starts on page boundary */\n+\t/* Pad it to rte_mem_page_size() so that data starts on page boundary */\n \tuint8_t\treserved2[4028];\n \n \t/*\ndiff --git a/drivers/bus/vmbus/vmbus_common_uio.c b/drivers/bus/vmbus/vmbus_common_uio.c\nindex a689bf11b3..8582e32c1d 100644\n--- a/drivers/bus/vmbus/vmbus_common_uio.c\n+++ b/drivers/bus/vmbus/vmbus_common_uio.c\n@@ -63,7 +63,7 @@ vmbus_uio_map_secondary(struct rte_vmbus_device *dev)\n \n \tfor (i = 0; i != uio_res->nb_maps; i++) {\n \t\tvoid *mapaddr;\n-\t\toff_t offset = i * PAGE_SIZE;\n+\t\toff_t offset = i * rte_mem_page_size();\n \n \t\tmapaddr = vmbus_map_resource(uio_res->maps[i].addr,\n \t\t\t\t\t fd, offset,\n@@ -175,7 +175,7 @@ vmbus_uio_map_resource(struct rte_vmbus_device *dev)\n \t}\n \n \tdev->int_page = (uint32_t *)((char *)uio_res->maps[HV_INT_PAGE_MAP].addr\n-\t\t\t\t + (PAGE_SIZE >> 1));\n+\t\t\t\t + (rte_mem_page_size() >> 1));\n \tdev->monitor_page = uio_res->maps[HV_MON_PAGE_MAP].addr;\n \treturn 0;\n }\ndiff --git a/drivers/crypto/virtio/virtio_pci.h b/drivers/crypto/virtio/virtio_pci.h\nindex d9a214dfd0..0a7ea1bb64 100644\n--- a/drivers/crypto/virtio/virtio_pci.h\n+++ b/drivers/crypto/virtio/virtio_pci.h\n@@ -7,6 +7,7 @@\n \n #include <stdint.h>\n \n+#include <rte_eal_paging.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\n #include <rte_cryptodev.h>\n@@ -67,7 +68,7 @@ struct virtqueue;\n *\n * Note the sizeof(struct vring_desc) is 16 bytes.\n */\n-#define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16))\n+#define VIRTIO_MAX_INDIRECT ((int) (rte_mem_page_size() / 16))\n \n /* Do we get callbacks when the ring is completely used, even if we've\n * suppressed them?\ndiff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nindex 2fbfc6aed4..60084ced3b 100644\n--- a/drivers/event/dlb/dlb.c\n+++ b/drivers/event/dlb/dlb.c\n@@ -23,6 +23,7 @@\n #include <rte_io.h>\n #include <rte_kvargs.h>\n #include <rte_log.h>\n+#include <rte_eal_paging.h>\n #include <rte_malloc.h>\n #include <rte_mbuf.h>\n #include <rte_power_intrinsics.h>\n@@ -991,7 +992,8 @@ dlb_hw_create_ldb_port(struct dlb_eventdev *dlb,\n \t\tgoto error_exit;\n \t}\n \n-\tqm_port->pp_mmio_base = DLB_LDB_PP_BASE + PAGE_SIZE * qm_port_id;\n+\tqm_port->pp_mmio_base = DLB_LDB_PP_BASE +\n+\t\t\trte_mem_page_size() * qm_port_id;\n \tqm_port->id = qm_port_id;\n \n \t/* The credit window is one high water mark of QEs */\n@@ -1181,7 +1183,8 @@ dlb_hw_create_dir_port(struct dlb_eventdev *dlb,\n \t\tgoto error_exit;\n \t}\n \n-\tqm_port->pp_mmio_base = DLB_DIR_PP_BASE + PAGE_SIZE * qm_port_id;\n+\tqm_port->pp_mmio_base = DLB_DIR_PP_BASE +\n+\t\t\trte_mem_page_size() * qm_port_id;\n \tqm_port->id = qm_port_id;\n \n \t/* The credit window is one high water mark of QEs */\ndiff --git a/drivers/event/dlb/dlb_priv.h b/drivers/event/dlb/dlb_priv.h\nindex 272e17482f..ca4d6a84cf 100644\n--- a/drivers/event/dlb/dlb_priv.h\n+++ b/drivers/event/dlb/dlb_priv.h\n@@ -76,8 +76,6 @@\n \n #define PP_BASE(is_dir) ((is_dir) ? DLB_DIR_PP_BASE : DLB_LDB_PP_BASE)\n \n-#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n-\n #define DLB_NUM_QES_PER_CACHE_LINE 4\n \n #define DLB_MAX_ENQUEUE_DEPTH 64\ndiff --git a/drivers/event/dlb/pf/base/dlb_osdep.h b/drivers/event/dlb/pf/base/dlb_osdep.h\nindex 0c119b759a..dee20660ed 100644\n--- a/drivers/event/dlb/pf/base/dlb_osdep.h\n+++ b/drivers/event/dlb/pf/base/dlb_osdep.h\n@@ -92,7 +92,7 @@ static inline void *os_map_producer_port(struct dlb_hw *hw,\n \n \n \tpp_dma_base = (uintptr_t)hw->func_kva + DLB_PP_BASE(is_ldb);\n-\taddr = (pp_dma_base + (PAGE_SIZE * port_id));\n+\taddr = (pp_dma_base + (rte_mem_page_size() * port_id));\n \n \treturn (void *)(uintptr_t)addr;\n \ndiff --git a/drivers/event/dlb/pf/dlb_main.h b/drivers/event/dlb/pf/dlb_main.h\nindex 22e215223d..e66ba228d1 100644\n--- a/drivers/event/dlb/pf/dlb_main.h\n+++ b/drivers/event/dlb/pf/dlb_main.h\n@@ -10,10 +10,7 @@\n #include <rte_spinlock.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\n-\n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n-#endif\n+#include <rte_eal_paging.h>\n \n #include \"base/dlb_hw_types.h\"\n #include \"../dlb_user.h\"\ndiff --git a/drivers/event/dlb/pf/dlb_pf.c b/drivers/event/dlb/pf/dlb_pf.c\nindex 876c68e51d..5445c2d57d 100644\n--- a/drivers/event/dlb/pf/dlb_pf.c\n+++ b/drivers/event/dlb/pf/dlb_pf.c\n@@ -304,7 +304,7 @@ dlb_pf_ldb_port_create(struct dlb_hw_dev *handle,\n \talloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);\n \n \tport_base = dlb_alloc_coherent_aligned(&mz, &pc_dma_base,\n-\t\t\t\t\t alloc_sz, PAGE_SIZE);\n+\t\t\t\t\t alloc_sz, rte_mem_page_size());\n \tif (port_base == NULL)\n \t\treturn -ENOMEM;\n \n@@ -329,7 +329,8 @@ dlb_pf_ldb_port_create(struct dlb_hw_dev *handle,\n \n \tpp_dma_base = (uintptr_t)dlb_dev->hw.func_kva + PP_BASE(is_dir);\n \tdlb_port[response.id][DLB_LDB].pp_addr =\n-\t\t(void *)(uintptr_t)(pp_dma_base + (PAGE_SIZE * response.id));\n+\t\t\t(void *)(uintptr_t)(pp_dma_base +\n+\t\t\t(rte_mem_page_size() * response.id));\n \n \tdlb_port[response.id][DLB_LDB].cq_base =\n \t\t(void *)(uintptr_t)(port_base + (2 * RTE_CACHE_LINE_SIZE));\n@@ -382,7 +383,7 @@ dlb_pf_dir_port_create(struct dlb_hw_dev *handle,\n \talloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);\n \n \tport_base = dlb_alloc_coherent_aligned(&mz, &pc_dma_base,\n-\t\t\t\t\t alloc_sz, PAGE_SIZE);\n+\t\t\t\t\t alloc_sz, rte_mem_page_size());\n \tif (port_base == NULL)\n \t\treturn -ENOMEM;\n \n@@ -407,7 +408,8 @@ dlb_pf_dir_port_create(struct dlb_hw_dev *handle,\n \n \tpp_dma_base = (uintptr_t)dlb_dev->hw.func_kva + PP_BASE(is_dir);\n \tdlb_port[response.id][DLB_DIR].pp_addr =\n-\t\t(void *)(uintptr_t)(pp_dma_base + (PAGE_SIZE * response.id));\n+\t\t\t(void *)(uintptr_t)(pp_dma_base +\n+\t\t\t(rte_mem_page_size() * response.id));\n \n \tdlb_port[response.id][DLB_DIR].cq_base =\n \t\t(void *)(uintptr_t)(port_base + (2 * RTE_CACHE_LINE_SIZE));\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex b73cf3ff14..eb1a932399 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -78,8 +78,6 @@\n \t\t\t\t DLB2_LDB_CQ_MAX_SIZE)\n #define PP_BASE(is_dir) ((is_dir) ? DLB2_DIR_PP_BASE : DLB2_LDB_PP_BASE)\n \n-#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n-\n #define DLB2_NUM_QES_PER_CACHE_LINE 4\n \n #define DLB2_MAX_ENQUEUE_DEPTH 64\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_osdep.h b/drivers/event/dlb2/pf/base/dlb2_osdep.h\nindex c4c34eba5f..aa101a49a3 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_osdep.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_osdep.h\n@@ -89,7 +89,7 @@ static inline void *os_map_producer_port(struct dlb2_hw *hw,\n \tuint64_t pp_dma_base;\n \n \tpp_dma_base = (uintptr_t)hw->func_kva + DLB2_PP_BASE(is_ldb);\n-\taddr = (pp_dma_base + (PAGE_SIZE * port_id));\n+\taddr = (pp_dma_base + (rte_mem_page_size() * port_id));\n \n \treturn (void *)(uintptr_t)addr;\n }\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb2/pf/dlb2_main.h\nindex f3bee71fb6..9eeda482a3 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.h\n+++ b/drivers/event/dlb2/pf/dlb2_main.h\n@@ -10,10 +10,7 @@\n #include <rte_spinlock.h>\n #include <rte_pci.h>\n #include <rte_bus_pci.h>\n-\n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n-#endif\n+#include <rte_eal_paging.h>\n \n #include \"base/dlb2_hw_types.h\"\n #include \"../dlb2_user.h\"\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex b85fd3ec56..cfb22efe8a 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -285,7 +285,7 @@ dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle,\n \talloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);\n \n \tport_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,\n-\t\t\t\t\t\tPAGE_SIZE);\n+\t\t\t\t\t\trte_mem_page_size());\n \tif (port_base == NULL)\n \t\treturn -ENOMEM;\n \n@@ -308,7 +308,7 @@ dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle,\n \n \tpp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);\n \tdlb2_port[response.id][DLB2_LDB_PORT].pp_addr =\n-\t\t(void *)(pp_base + (PAGE_SIZE * response.id));\n+\t\t(void *)(pp_base + (rte_mem_page_size() * response.id));\n \n \tdlb2_port[response.id][DLB2_LDB_PORT].cq_base = (void *)(port_base);\n \tmemset(&port_memory, 0, sizeof(port_memory));\n@@ -360,7 +360,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,\n \talloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);\n \n \tport_base = dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz,\n-\t\t\t\t\t\tPAGE_SIZE);\n+\t\t\t\t\t\trte_mem_page_size());\n \tif (port_base == NULL)\n \t\treturn -ENOMEM;\n \n@@ -383,7 +383,7 @@ dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,\n \n \tpp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);\n \tdlb2_port[response.id][DLB2_DIR_PORT].pp_addr =\n-\t\t(void *)(pp_base + (PAGE_SIZE * response.id));\n+\t\t(void *)(pp_base + (rte_mem_page_size() * response.id));\n \n \tdlb2_port[response.id][DLB2_DIR_PORT].cq_base =\n \t\t(void *)(port_base);\ndiff --git a/drivers/net/bnx2x/ecore_fw_defs.h b/drivers/net/bnx2x/ecore_fw_defs.h\nindex 5397a701aa..93bca8ad33 100644\n--- a/drivers/net/bnx2x/ecore_fw_defs.h\n+++ b/drivers/net/bnx2x/ecore_fw_defs.h\n@@ -13,6 +13,8 @@\n #ifndef ECORE_FW_DEFS_H\n #define ECORE_FW_DEFS_H\n \n+#include <rte_eal_paging.h>\n+\n #define CSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[152].base)\n #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n \t(IRO[151].base + ((assertListEntry) * IRO[151].m1))\n@@ -252,7 +254,8 @@\n #define X_ETH_LOCAL_RING_SIZE 13\n #define FIRST_BD_IN_PKT\t0\n #define PARSE_BD_INDEX 1\n-#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))\n+#define NUM_OF_ETH_BDS_IN_PAGE \\\n+\t(rte_mem_page_size() / (STRUCT_SIZE(eth_tx_bd) / 8))\n #define U_ETH_NUM_OF_SGES_TO_FETCH 8\n #define U_ETH_MAX_SGES_FOR_PACKET 3\n \n@@ -265,11 +268,14 @@\n #define IP_HEADER_ALIGNMENT_PADDING 2\n \n #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \\\n-\t(0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))\n+\t(0xFFFF - ((rte_mem_page_size() / ((STRUCT_SIZE(eth_rx_sge)) / 8)) - 1))\n \n-#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))\n-#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))\n-#define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))\n+#define TU_ETH_CQES_PER_PAGE \\\n+\t(rte_mem_page_size() / (STRUCT_SIZE(eth_rx_cqe) / 8))\n+#define U_ETH_BDS_PER_PAGE \\\n+\t(rte_mem_page_size() / (STRUCT_SIZE(eth_rx_bd) / 8))\n+#define U_ETH_SGES_PER_PAGE \\\n+\t(rte_mem_page_size() / (STRUCT_SIZE(eth_rx_sge) / 8))\n \n #define U_ETH_BDS_PER_PAGE_MASK\t(U_ETH_BDS_PER_PAGE-1)\n #define U_ETH_CQE_PER_PAGE_MASK\t(TU_ETH_CQES_PER_PAGE-1)\n@@ -396,7 +402,7 @@\n \n /* Event Ring definitions */\n #define C_ERES_PER_PAGE \\\n-\t(PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))\n+\t(rte_mem_page_size() / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))\n #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)\n \n /* number of statistic command */\ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex e083f92417..395e5acc8b 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -617,18 +617,18 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \tcq_size = num_descs * cq_desc_size;\n \tsg_size = num_descs * sg_desc_size;\n \n-\ttotal_size = RTE_ALIGN(q_size, PAGE_SIZE) +\n-\t\tRTE_ALIGN(cq_size, PAGE_SIZE);\n+\ttotal_size = RTE_ALIGN(q_size, rte_mem_page_size()) +\n+\t\t\tRTE_ALIGN(cq_size, rte_mem_page_size());\n \t/*\n \t * Note: aligning q_size/cq_size is not enough due to cq_base address\n \t * aligning as q_base could be not aligned to the page.\n-\t * Adding PAGE_SIZE.\n+\t * Adding rte_mem_page_size().\n \t */\n-\ttotal_size += PAGE_SIZE;\n+\ttotal_size += rte_mem_page_size();\n \n \tif (flags & IONIC_QCQ_F_SG) {\n-\t\ttotal_size += RTE_ALIGN(sg_size, PAGE_SIZE);\n-\t\ttotal_size += PAGE_SIZE;\n+\t\ttotal_size += RTE_ALIGN(sg_size, rte_mem_page_size());\n+\t\ttotal_size += rte_mem_page_size();\n \t}\n \n \tnew = rte_zmalloc(\"ionic\", sizeof(*new), 0);\n@@ -679,13 +679,16 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,\n \tq_base = new->base;\n \tq_base_pa = new->base_pa;\n \n-\tcq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE);\n-\tcq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE);\n+\tcq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size,\n+\t\t\trte_mem_page_size());\n+\tcq_base_pa = RTE_ALIGN(q_base_pa + q_size,\n+\t\t\trte_mem_page_size());\n \n \tif (flags & IONIC_QCQ_F_SG) {\n \t\tsg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size,\n-\t\t\tPAGE_SIZE);\n-\t\tsg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE);\n+\t\t\t\trte_mem_page_size());\n+\t\tsg_base_pa = RTE_ALIGN(cq_base_pa + cq_size,\n+\t\t\t\trte_mem_page_size());\n \t\tionic_q_sg_map(&new->q, sg_base, sg_base_pa);\n \t}\n \n@@ -975,7 +978,7 @@ ionic_lif_alloc(struct ionic_lif *lif)\n \n \tIONIC_PRINT(DEBUG, \"Allocating Lif Info\");\n \n-\tlif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE);\n+\tlif->info_sz = RTE_ALIGN(sizeof(*lif->info), rte_mem_page_size());\n \n \tlif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev,\n \t\t\"lif_info\", 0 /* queue_idx*/,\ndiff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c\nindex 3f1a764888..3ee4999fa5 100644\n--- a/drivers/net/ionic/ionic_main.c\n+++ b/drivers/net/ionic/ionic_main.c\n@@ -375,7 +375,8 @@ ionic_port_init(struct ionic_adapter *adapter)\n \tif (idev->port_info)\n \t\treturn 0;\n \n-\tidev->port_info_sz = RTE_ALIGN(sizeof(*idev->port_info), PAGE_SIZE);\n+\tidev->port_info_sz = RTE_ALIGN(sizeof(*idev->port_info),\n+\t\t\trte_mem_page_size());\n \n \tsnprintf(z_name, sizeof(z_name), \"%s_port_%s_info\",\n \t\tIONIC_DRV_NAME, adapter->name);\ndiff --git a/drivers/net/ionic/ionic_osdep.h b/drivers/net/ionic/ionic_osdep.h\nindex a6575c36b5..89ed106d11 100644\n--- a/drivers/net/ionic/ionic_osdep.h\n+++ b/drivers/net/ionic/ionic_osdep.h\n@@ -17,6 +17,7 @@\n #include <rte_byteorder.h>\n #include <rte_io.h>\n #include <rte_memory.h>\n+#include <rte_eal_paging.h>\n \n #include \"ionic_logs.h\"\n \n@@ -25,7 +26,6 @@\n \n #ifndef PAGE_SHIFT\n #define PAGE_SHIFT 12\n-#define PAGE_SIZE (1 << PAGE_SHIFT)\n #endif\n \n #define __iomem\ndiff --git a/drivers/net/netvsc/hn_rndis.c b/drivers/net/netvsc/hn_rndis.c\nindex e317539de7..e3f7e636d7 100644\n--- a/drivers/net/netvsc/hn_rndis.c\n+++ b/drivers/net/netvsc/hn_rndis.c\n@@ -67,7 +67,7 @@ hn_rndis_rid(struct hn_data *hv)\n \n static void *hn_rndis_alloc(size_t size)\n {\n-\treturn rte_zmalloc(\"RNDIS\", size, PAGE_SIZE);\n+\treturn rte_zmalloc(\"RNDIS\", size, rte_mem_page_size());\n }\n \n #ifdef RTE_LIBRTE_NETVSC_DEBUG_DUMP\n@@ -265,17 +265,17 @@ static int hn_nvs_send_rndis_ctrl(struct vmbus_channel *chan,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (unlikely(reqlen > PAGE_SIZE)) {\n+\tif (unlikely(reqlen > rte_mem_page_size())) {\n \t\tPMD_DRV_LOG(ERR, \"RNDIS request %u greater than page size\",\n \t\t\t reqlen);\n \t\treturn -EINVAL;\n \t}\n \n-\tsg.page = addr / PAGE_SIZE;\n+\tsg.page = addr / rte_mem_page_size();\n \tsg.ofs = addr & PAGE_MASK;\n \tsg.len = reqlen;\n \n-\tif (sg.ofs + reqlen > PAGE_SIZE) {\n+\tif (sg.ofs + reqlen > rte_mem_page_size()) {\n \t\tPMD_DRV_LOG(ERR, \"RNDIS request crosses page boundary\");\n \t\treturn -EINVAL;\n \t}\n@@ -479,7 +479,7 @@ hn_rndis_query(struct hn_data *hv, uint32_t oid,\n \t\treturn -ENOMEM;\n \n \tcomp_len = sizeof(*comp) + odlen;\n-\tcomp = rte_zmalloc(\"QUERY\", comp_len, PAGE_SIZE);\n+\tcomp = rte_zmalloc(\"QUERY\", comp_len, rte_mem_page_size());\n \tif (!comp) {\n \t\terror = -ENOMEM;\n \t\tgoto done;\n@@ -736,7 +736,7 @@ hn_rndis_set(struct hn_data *hv, uint32_t oid, const void *data, uint32_t dlen)\n \tint error;\n \n \treqlen = sizeof(*req) + dlen;\n-\treq = rte_zmalloc(\"RNDIS_SET\", reqlen, PAGE_SIZE);\n+\treq = rte_zmalloc(\"RNDIS_SET\", reqlen, rte_mem_page_size());\n \tif (!req)\n \t\treturn -ENOMEM;\n \ndiff --git a/drivers/net/netvsc/hn_rxtx.c b/drivers/net/netvsc/hn_rxtx.c\nindex 0f4ef0100b..c6bf7cc132 100644\n--- a/drivers/net/netvsc/hn_rxtx.c\n+++ b/drivers/net/netvsc/hn_rxtx.c\n@@ -1387,7 +1387,8 @@ static unsigned int hn_get_slots(const struct rte_mbuf *m)\n \t\tunsigned int size = rte_pktmbuf_data_len(m);\n \t\tunsigned int offs = rte_mbuf_data_iova(m) & PAGE_MASK;\n \n-\t\tslots += (offs + size + PAGE_SIZE - 1) / PAGE_SIZE;\n+\t\tslots += (offs + size + rte_mem_page_size() - 1) /\n+\t\t\t\trte_mem_page_size();\n \t\tm = m->next;\n \t}\n \n@@ -1402,12 +1403,13 @@ static unsigned int hn_fill_sg(struct vmbus_gpa *sg,\n \n \twhile (m) {\n \t\trte_iova_t addr = rte_mbuf_data_iova(m);\n-\t\tunsigned int page = addr / PAGE_SIZE;\n+\t\tunsigned int page = addr / rte_mem_page_size();\n \t\tunsigned int offset = addr & PAGE_MASK;\n \t\tunsigned int len = rte_pktmbuf_data_len(m);\n \n \t\twhile (len > 0) {\n-\t\t\tunsigned int bytes = RTE_MIN(len, PAGE_SIZE - offset);\n+\t\t\tunsigned int bytes = RTE_MIN(len,\n+\t\t\t\t\trte_mem_page_size() - offset);\n \n \t\t\tsg[segs].page = page;\n \t\t\tsg[segs].ofs = offset;\n@@ -1450,7 +1452,7 @@ static int hn_xmit_sg(struct hn_tx_queue *txq,\n \taddr = txq->tx_rndis_iova +\n \t\t((char *)txd->rndis_pkt - (char *)txq->tx_rndis);\n \n-\tsg[0].page = addr / PAGE_SIZE;\n+\tsg[0].page = addr / rte_mem_page_size();\n \tsg[0].ofs = addr & PAGE_MASK;\n \tsg[0].len = RNDIS_PACKET_MSG_OFFSET_ABS(hn_rndis_pktlen(txd->rndis_pkt));\n \tsegs = 1;\ndiff --git a/drivers/net/netvsc/hn_var.h b/drivers/net/netvsc/hn_var.h\nindex b7405ca726..43642408bc 100644\n--- a/drivers/net/netvsc/hn_var.h\n+++ b/drivers/net/netvsc/hn_var.h\n@@ -6,6 +6,8 @@\n * All rights reserved.\n */\n \n+#include <rte_eal_paging.h>\n+\n /*\n * Tunable ethdev params\n */\n@@ -28,13 +30,8 @@\n \n #define HN_RX_EXTMBUF_ENABLE\t0\n \n-/* Buffers need to be aligned */\n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE 4096\n-#endif\n-\n #ifndef PAGE_MASK\n-#define PAGE_MASK (PAGE_SIZE - 1)\n+#define PAGE_MASK (rte_mem_page_size() - 1)\n #endif\n \n struct hn_data;\ndiff --git a/drivers/net/virtio/virtio.h b/drivers/net/virtio/virtio.h\nindex 21d54904e7..2c987d19ab 100644\n--- a/drivers/net/virtio/virtio.h\n+++ b/drivers/net/virtio/virtio.h\n@@ -98,7 +98,7 @@\n *\n * Note the sizeof(struct vring_desc) is 16 bytes.\n */\n-#define VIRTIO_MAX_INDIRECT ((int)(PAGE_SIZE / 16))\n+#define VIRTIO_MAX_INDIRECT ((int)(rte_mem_page_size() / 16))\n \n /*\n * Maximum number of virtqueues per device.\ndiff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c\nindex 333a5243a9..289b240c4e 100644\n--- a/drivers/net/virtio/virtio_ethdev.c\n+++ b/drivers/net/virtio/virtio_ethdev.c\n@@ -21,8 +21,8 @@\n #include <rte_errno.h>\n #include <rte_cpuflags.h>\n #include <rte_vect.h>\n-\n #include <rte_memory.h>\n+#include <rte_eal_paging.h>\n #include <rte_eal.h>\n #include <rte_dev.h>\n #include <rte_cycles.h>\n@@ -469,7 +469,7 @@ virtio_init_queue(struct rte_eth_dev *dev, uint16_t queue_idx)\n \t\tsz_hdr_mz = vq_size * sizeof(struct virtio_tx_region);\n \t} else if (queue_type == VTNET_CQ) {\n \t\t/* Allocate a page for control vq command, data and status */\n-\t\tsz_hdr_mz = PAGE_SIZE;\n+\t\tsz_hdr_mz = rte_mem_page_size();\n \t}\n \n \tvq = rte_zmalloc_socket(vq_name, size, RTE_CACHE_LINE_SIZE,\n@@ -568,7 +568,7 @@ virtio_init_queue(struct rte_eth_dev *dev, uint16_t queue_idx)\n \t\tcvq->mz = mz;\n \t\tcvq->virtio_net_hdr_mz = hdr_mz;\n \t\tcvq->virtio_net_hdr_mem = hdr_mz->iova;\n-\t\tmemset(cvq->virtio_net_hdr_mz->addr, 0, PAGE_SIZE);\n+\t\tmemset(cvq->virtio_net_hdr_mz->addr, 0, rte_mem_page_size());\n \n \t\thw->cvq = cvq;\n \t}\ndiff --git a/drivers/net/virtio/virtio_ethdev.h b/drivers/net/virtio/virtio_ethdev.h\nindex 873327d989..5a501e7890 100644\n--- a/drivers/net/virtio/virtio_ethdev.h\n+++ b/drivers/net/virtio/virtio_ethdev.h\n@@ -11,10 +11,6 @@\n \n #include \"virtio.h\"\n \n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE 4096\n-#endif\n-\n #define VIRTIO_MAX_RX_QUEUES 128U\n #define VIRTIO_MAX_TX_QUEUES 128U\n #define VIRTIO_MAX_MAC_ADDRS 64\ndiff --git a/drivers/vdpa/ifc/ifcvf_vdpa.c b/drivers/vdpa/ifc/ifcvf_vdpa.c\nindex 6a1b44bc77..39237aecf7 100644\n--- a/drivers/vdpa/ifc/ifcvf_vdpa.c\n+++ b/drivers/vdpa/ifc/ifcvf_vdpa.c\n@@ -11,6 +11,7 @@\n #include <linux/virtio_net.h>\n #include <stdbool.h>\n \n+#include <rte_eal_paging.h>\n #include <rte_malloc.h>\n #include <rte_memory.h>\n #include <rte_bus_pci.h>\n@@ -30,10 +31,6 @@ RTE_LOG_REGISTER(ifcvf_vdpa_logtype, pmd.net.ifcvf_vdpa, NOTICE);\n \trte_log(RTE_LOG_ ## level, ifcvf_vdpa_logtype, \\\n \t\t\"IFCVF %s(): \" fmt \"\\n\", __func__, ##args)\n \n-#ifndef PAGE_SIZE\n-#define PAGE_SIZE 4096\n-#endif\n-\n #define IFCVF_USED_RING_LEN(size) \\\n \t((size) * sizeof(struct vring_used_elem) + sizeof(uint16_t) * 3)\n \n@@ -600,11 +597,11 @@ m_ifcvf_start(struct ifcvf_internal *internal)\n \tfor (i = 0; i < nr_vring; i++) {\n \t\trte_vhost_get_vhost_vring(vid, i, &vq);\n \n-\t\tsize = RTE_ALIGN_CEIL(vring_size(vq.size, PAGE_SIZE),\n-\t\t\t\tPAGE_SIZE);\n-\t\tvring_buf = rte_zmalloc(\"ifcvf\", size, PAGE_SIZE);\n+\t\tsize = RTE_ALIGN_CEIL(vring_size(vq.size, rte_mem_page_size()),\n+\t\t\t\trte_mem_page_size());\n+\t\tvring_buf = rte_zmalloc(\"ifcvf\", size, rte_mem_page_size());\n \t\tvring_init(&internal->m_vring[i], vq.size, vring_buf,\n-\t\t\t\tPAGE_SIZE);\n+\t\t\t\trte_mem_page_size());\n \n \t\tret = rte_vfio_container_dma_map(internal->vfio_container_fd,\n \t\t\t(uint64_t)(uintptr_t)vring_buf, m_vring_iova, size);\n@@ -686,8 +683,8 @@ m_ifcvf_stop(struct ifcvf_internal *internal)\n \t\tlen = IFCVF_USED_RING_LEN(vq.size);\n \t\trte_vhost_log_used_vring(vid, i, 0, len);\n \n-\t\tsize = RTE_ALIGN_CEIL(vring_size(vq.size, PAGE_SIZE),\n-\t\t\t\tPAGE_SIZE);\n+\t\tsize = RTE_ALIGN_CEIL(vring_size(vq.size, rte_mem_page_size()),\n+\t\t\t\trte_mem_page_size());\n \t\trte_vfio_container_dma_unmap(internal->vfio_container_fd,\n \t\t\t(uint64_t)(uintptr_t)internal->m_vring[i].desc,\n \t\t\tm_vring_iova, size);\n", "prefixes": [ "v5", "07/17" ] }