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GET /api/patches/87363/?format=api
{ "id": 87363, "url": "https://patches.dpdk.org/api/patches/87363/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-7-pnalla@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210126213051.57281-7-pnalla@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210126213051.57281-7-pnalla@marvell.com", "date": "2021-01-26T21:30:47", "name": "[v3,07/11] net/octeontx_ep: Added tx queue setup and release", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0d3557cd4d4e7399feb1fd3377cf2ad1e70b0a4a", "submitter": { "id": 2074, "url": "https://patches.dpdk.org/api/people/2074/?format=api", "name": "Pradeep Nalla", "email": "pnalla@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210126213051.57281-7-pnalla@marvell.com/mbox/", "series": [ { "id": 14962, "url": "https://patches.dpdk.org/api/series/14962/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14962", "date": "2021-01-26T21:30:42", "name": "[v3,01/11] net/octeontx_ep: add build and doc infrastructure", "version": 3, "mbox": "https://patches.dpdk.org/series/14962/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/87363/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/87363/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F0083A052A;\n\tTue, 26 Jan 2021 22:32:29 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1F7D8140D56;\n\tTue, 26 Jan 2021 22:31:57 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9309D140D0A\n for <dev@dpdk.org>; Tue, 26 Jan 2021 22:31:48 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 10QL0J6D025557 for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:47 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 368m6uhds1-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 26 Jan 2021 13:31:47 -0800", "from SC-EXCH02.marvell.com (10.93.176.82) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:46 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 26 Jan 2021 13:31:45 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 26 Jan 2021 13:31:45 -0800", "from sburla-Super-Server.caveonetworks.com (unknown [10.106.27.196])\n by maili.marvell.com (Postfix) with ESMTP id 2A65E3F703F;\n Tue, 26 Jan 2021 13:31:45 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=9PkxR0eiKBPXTOzM/jJCNuHfilhPv81oeZZIPWLB3zI=;\n b=SwPcRshdP0mTUADJP/MNvyFVB5P9wTLr6KLyPMgUo5/owmGUq0r6Pbp3uL8b41aJXnZ3\n AZxRzcde+RCedCpRHkJX1k36OdPLpx64EMeqT0jw+UDOCacAfUmbOesyVpTmOWoZN1e0\n xLampW69W1FJinQoBAxhI610hUR+JMfYduFxkpqgH6tsN36WduAnxJlNG7j8lvOatA7C\n uv1fl4N0YZW4qQecgaZj0iQEXdyl163/mEpZEy1lwP990joPLloix2wMEn1U7Bj/WlON\n Fk6cwtVk9zBDj3aimOB8tuCBylKztA4d3cPqJcD5XqJFAalZuhfpzyTpoct4cMkPKCqh tA==", "From": "Nalla Pradeep <pnalla@marvell.com>", "To": "", "CC": "<jerinj@marvell.com>, <sburla@marvell.com>, <dev@dpdk.org>, Nalla Pradeep\n <pnalla@marvell.com>", "Date": "Tue, 26 Jan 2021 13:30:47 -0800", "Message-ID": "<20210126213051.57281-7-pnalla@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210126213051.57281-1-pnalla@marvell.com>", "References": "<20210126213051.57281-1-pnalla@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2021-01-26_11:2021-01-26,\n 2021-01-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 07/11] net/octeontx_ep: Added tx queue setup\n and release", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Transmit queue setup involves allocating memory for the command queue\nconsidering tx descriptor count and initializing data structure\nrepresenting the queue. Transmit queue release function frees the\ncommand queue.\n\nSigned-off-by: Nalla Pradeep <pnalla@marvell.com>\n---\n drivers/net/octeontx_ep/otx_ep_common.h | 89 +++++++++++++++-\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 81 ++++++++++++++\n drivers/net/octeontx_ep/otx_ep_rxtx.c | 135 ++++++++++++++++++++++++\n 3 files changed, 303 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex 6be5c5a76..e1b4ff270 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -42,7 +42,21 @@\n \trte_write64(val, ((base_addr) + off)); \\\n \t}\n \n-struct otx_ep_device;\n+/* OTX_EP IQ request list */\n+struct otx_ep_instr_list {\n+\tvoid *buf;\n+\tuint32_t reqtype;\n+};\n+#define OTX_EP_IQREQ_LIST_SIZE\t(sizeof(struct otx_ep_instr_list))\n+\n+/* Input Queue statistics. Each input queue has four stats fields. */\n+struct otx_ep_iq_stats {\n+\tuint64_t instr_posted; /* Instructions posted to this queue. */\n+\tuint64_t instr_processed; /* Instructions processed in this queue. */\n+\tuint64_t instr_dropped; /* Instructions that could not be processed */\n+\tuint64_t tx_pkts;\n+\tuint64_t tx_bytes;\n+};\n \n /* Structure to define the configuration attributes for each Input queue. */\n struct otx_ep_iq_config {\n@@ -56,6 +70,66 @@ struct otx_ep_iq_config {\n \tuint32_t pending_list_size;\n };\n \n+/** The instruction (input) queue.\n+ * The input queue is used to post raw (instruction) mode data or packet data\n+ * to OCTEON TX2 device from the host. Each IQ of a OTX_EP EP VF device has one\n+ * such structure to represent it.\n+ */\n+struct otx_ep_instr_queue {\n+\tstruct otx_ep_device *otx_ep_dev;\n+\n+\tuint32_t q_no;\n+\tuint32_t pkt_in_done;\n+\n+\t/* Flag for 64 byte commands. */\n+\tuint32_t iqcmd_64B:1;\n+\tuint32_t rsvd:17;\n+\tuint32_t status:8;\n+\n+\t/* Number of descriptors in this ring. */\n+\tuint32_t nb_desc;\n+\n+\t/* Input ring index, where the driver should write the next packet */\n+\tuint32_t host_write_index;\n+\n+\t/* Input ring index, where the OCTEON TX2 should read the next packet */\n+\tuint32_t otx_read_index;\n+\n+\tuint32_t reset_instr_cnt;\n+\n+\t/** This index aids in finding the window in the queue where OCTEON TX2\n+\t * has read the commands.\n+\t */\n+\tuint32_t flush_index;\n+\n+\t/* This keeps track of the instructions pending in this queue. */\n+\tuint64_t instr_pending;\n+\n+\t/* Pointer to the Virtual Base addr of the input ring. */\n+\tuint8_t *base_addr;\n+\n+\t/* This IQ request list */\n+\tstruct otx_ep_instr_list *req_list;\n+\n+\t/* OTX_EP doorbell register for the ring. */\n+\tvoid *doorbell_reg;\n+\n+\t/* OTX_EP instruction count register for this ring. */\n+\tvoid *inst_cnt_reg;\n+\n+\t/* Number of instructions pending to be posted to OCTEON TX2. */\n+\tuint32_t fill_cnt;\n+\n+\t/* Statistics for this input queue. */\n+\tstruct otx_ep_iq_stats stats;\n+\n+\t/* DMA mapped base address of the input descriptor ring. */\n+\tuint64_t base_addr_dma;\n+\n+\t/* Memory zone */\n+\tconst struct rte_memzone *iq_mz;\n+};\n+\n /** Descriptor format.\n * The descriptor ring is made of descriptors which have 2 64-bit values:\n * -# Physical (bus) address of the data buffer.\n@@ -218,6 +292,7 @@ struct otx_ep_config {\n \n /* Required functions for each VF device */\n struct otx_ep_fn_list {\n+\tvoid (*setup_iq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \tvoid (*setup_oq_regs)(struct otx_ep_device *otx_ep, uint32_t q_no);\n \n \tint (*setup_device_regs)(struct otx_ep_device *otx_ep);\n@@ -256,6 +331,12 @@ struct otx_ep_device {\n \n \tuint32_t max_rx_queues;\n \n+\t/* Num IQs */\n+\tuint32_t nb_tx_queues;\n+\n+\t/* The input instruction queues */\n+\tstruct otx_ep_instr_queue *instr_queue[OTX_EP_MAX_IOQS_PER_VF];\n+\n \t/* Num OQs */\n \tuint32_t nb_rx_queues;\n \n@@ -278,12 +359,16 @@ struct otx_ep_device {\n \tuint64_t tx_offloads;\n };\n \n+int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no,\n+\t\t int num_descs, unsigned int socket_id);\n+int otx_ep_delete_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no);\n+\n int otx_ep_setup_oqs(struct otx_ep_device *otx_ep, int oq_no, int num_descs,\n \t\t int desc_size, struct rte_mempool *mpool,\n \t\t unsigned int socket_id);\n int otx_ep_delete_oqs(struct otx_ep_device *otx_ep, uint32_t oq_no);\n-#define OTX_EP_MAX_PKT_SZ 64000U\n \n+#define OTX_EP_MAX_PKT_SZ 64000U\n #define OTX_EP_MAX_MAC_ADDRS 1\n \n extern int otx_net_ep_logtype;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex 3e2df4035..33ddc1aed 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -235,11 +235,83 @@ otx_ep_rx_queue_release(void *rxq)\n \t\totx_ep_err(\"Failed to delete OQ:%d\\n\", q_id);\n }\n \n+/**\n+ * Allocate and initialize SW ring. Initialize associated HW registers.\n+ *\n+ * @param eth_dev\n+ * Pointer to structure rte_eth_dev\n+ *\n+ * @param q_no\n+ * Queue number\n+ *\n+ * @param num_tx_descs\n+ * Number of ringbuffer descriptors\n+ *\n+ * @param socket_id\n+ * NUMA socket id, used for memory allocations\n+ *\n+ * @param tx_conf\n+ * Pointer to the structure rte_eth_txconf\n+ *\n+ * @return\n+ * - On success, return 0\n+ * - On failure, return -errno value\n+ */\n+static int\n+otx_ep_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no,\n+\t\t uint16_t num_tx_descs, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n+{\n+\tstruct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);\n+\tint retval;\n+\n+\tif (q_no >= otx_epvf->max_tx_queues) {\n+\t\totx_ep_err(\"Invalid tx queue number %u\\n\", q_no);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (num_tx_descs & (num_tx_descs - 1)) {\n+\t\totx_ep_err(\"Invalid tx desc number should be pow 2 %u\\n\",\n+\t\t\t num_tx_descs);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tretval = otx_ep_setup_iqs(otx_epvf, q_no, num_tx_descs, socket_id);\n+\n+\tif (retval) {\n+\t\totx_ep_err(\"IQ(TxQ) creation failed.\\n\");\n+\t\treturn retval;\n+\t}\n+\n+\teth_dev->data->tx_queues[q_no] = otx_epvf->instr_queue[q_no];\n+\totx_ep_dbg(\"tx queue[%d] setup\\n\", q_no);\n+\treturn 0;\n+}\n+\n+/**\n+ * Release the transmit queue/ringbuffer. Called by\n+ * the upper layers.\n+ *\n+ * @param txq\n+ * Opaque pointer to the transmit queue to release\n+ *\n+ * @return\n+ * - nothing\n+ */\n+static void\n+otx_ep_tx_queue_release(void *txq)\n+{\n+\tstruct otx_ep_instr_queue *tq = (struct otx_ep_instr_queue *)txq;\n+\n+\totx_ep_delete_iqs(tq->otx_ep_dev, tq->q_no);\n+}\n+\n /* Define our ethernet definitions */\n static const struct eth_dev_ops otx_ep_eth_dev_ops = {\n \t.dev_configure\t\t= otx_ep_dev_configure,\n \t.rx_queue_setup\t = otx_ep_rx_queue_setup,\n \t.rx_queue_release\t= otx_ep_rx_queue_release,\n+\t.tx_queue_setup\t = otx_ep_tx_queue_setup,\n+\t.tx_queue_release\t= otx_ep_tx_queue_release,\n \t.dev_infos_get\t\t= otx_ep_dev_info_get,\n };\n \n@@ -264,6 +336,15 @@ otx_epdev_exit(struct rte_eth_dev *eth_dev)\n \t}\n \totx_ep_info(\"Num OQs:%d freed\\n\", otx_epvf->nb_rx_queues);\n \n+\tnum_queues = otx_epvf->nb_tx_queues;\n+\tfor (q = 0; q < num_queues; q++) {\n+\t\tif (otx_ep_delete_iqs(otx_epvf, q)) {\n+\t\t\totx_ep_err(\"Failed to delete IQ:%d\\n\", q);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\totx_ep_dbg(\"Num IQs:%d freed\\n\", otx_epvf->nb_tx_queues);\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.c b/drivers/net/octeontx_ep/otx_ep_rxtx.c\nindex e5b228f26..666411e7c 100644\n--- a/drivers/net/octeontx_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.c\n@@ -36,6 +36,141 @@ otx_ep_dmazone_free(const struct rte_memzone *mz)\n \t\totx_ep_err(\"Memzone free failed : ret = %d\\n\", ret);\n }\n \n+/* Free IQ resources */\n+int\n+otx_ep_delete_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no)\n+{\n+\tstruct otx_ep_instr_queue *iq;\n+\n+\tiq = otx_ep->instr_queue[iq_no];\n+\tif (iq == NULL) {\n+\t\totx_ep_err(\"Invalid IQ[%d]\\n\", iq_no);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trte_free(iq->req_list);\n+\tiq->req_list = NULL;\n+\n+\tif (iq->iq_mz) {\n+\t\totx_ep_dmazone_free(iq->iq_mz);\n+\t\tiq->iq_mz = NULL;\n+\t}\n+\n+\trte_free(otx_ep->instr_queue[iq_no]);\n+\totx_ep->instr_queue[iq_no] = NULL;\n+\n+\totx_ep->nb_tx_queues--;\n+\n+\totx_ep_info(\"IQ[%d] is deleted\\n\", iq_no);\n+\n+\treturn 0;\n+}\n+\n+/* IQ initialization */\n+static int\n+otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n+\t\t unsigned int socket_id)\n+{\n+\tconst struct otx_ep_config *conf;\n+\tstruct otx_ep_instr_queue *iq;\n+\tuint32_t q_size;\n+\n+\tconf = otx_ep->conf;\n+\tiq = otx_ep->instr_queue[iq_no];\n+\tq_size = conf->iq.instr_type * num_descs;\n+\n+\t/* IQ memory creation for Instruction submission to OCTEON TX2 */\n+\tiq->iq_mz = rte_eth_dma_zone_reserve(otx_ep->eth_dev,\n+\t\t\t\t\t \"instr_queue\", iq_no, q_size,\n+\t\t\t\t\t OTX_EP_PCI_RING_ALIGN,\n+\t\t\t\t\t socket_id);\n+\tif (iq->iq_mz == NULL) {\n+\t\totx_ep_err(\"IQ[%d] memzone alloc failed\\n\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\tiq->base_addr_dma = iq->iq_mz->iova;\n+\tiq->base_addr = (uint8_t *)iq->iq_mz->addr;\n+\n+\tif (num_descs & (num_descs - 1)) {\n+\t\totx_ep_err(\"IQ[%d] descs not in power of 2\\n\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\tiq->nb_desc = num_descs;\n+\n+\t/* Create a IQ request list to hold requests that have been\n+\t * posted to OCTEON TX2. This list will be used for freeing the IQ\n+\t * data buffer(s) later once the OCTEON TX2 fetched the requests.\n+\t */\n+\tiq->req_list = rte_zmalloc_socket(\"request_list\",\n+\t\t\t(iq->nb_desc * OTX_EP_IQREQ_LIST_SIZE),\n+\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\trte_socket_id());\n+\tif (iq->req_list == NULL) {\n+\t\totx_ep_err(\"IQ[%d] req_list alloc failed\\n\", iq_no);\n+\t\tgoto iq_init_fail;\n+\t}\n+\n+\totx_ep_info(\"IQ[%d]: base: %p basedma: %lx count: %d\\n\",\n+\t\t iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,\n+\t\t iq->nb_desc);\n+\n+\tiq->otx_ep_dev = otx_ep;\n+\tiq->q_no = iq_no;\n+\tiq->fill_cnt = 0;\n+\tiq->host_write_index = 0;\n+\tiq->otx_read_index = 0;\n+\tiq->flush_index = 0;\n+\tiq->instr_pending = 0;\n+\n+\n+\n+\totx_ep->io_qmask.iq |= (1ull << iq_no);\n+\n+\t/* Set 32B/64B mode for each input queue */\n+\tif (conf->iq.instr_type == 64)\n+\t\totx_ep->io_qmask.iq64B |= (1ull << iq_no);\n+\n+\tiq->iqcmd_64B = (conf->iq.instr_type == 64);\n+\n+\t/* Set up IQ registers */\n+\totx_ep->fn_list.setup_iq_regs(otx_ep, iq_no);\n+\n+\treturn 0;\n+\n+iq_init_fail:\n+\treturn -ENOMEM;\n+}\n+\n+int\n+otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no, int num_descs,\n+\t\t unsigned int socket_id)\n+{\n+\tstruct otx_ep_instr_queue *iq;\n+\n+\tiq = (struct otx_ep_instr_queue *)rte_zmalloc(\"otx_ep_IQ\", sizeof(*iq),\n+\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (iq == NULL)\n+\t\treturn -ENOMEM;\n+\n+\totx_ep->instr_queue[iq_no] = iq;\n+\n+\tif (otx_ep_init_instr_queue(otx_ep, iq_no, num_descs, socket_id)) {\n+\t\totx_ep_err(\"IQ init is failed\\n\");\n+\t\tgoto delete_IQ;\n+\t}\n+\totx_ep->nb_tx_queues++;\n+\n+\totx_ep_info(\"IQ[%d] is created.\\n\", iq_no);\n+\n+\treturn 0;\n+\n+delete_IQ:\n+\totx_ep_delete_iqs(otx_ep, iq_no);\n+\treturn -ENOMEM;\n+}\n+\n static void\n otx_ep_droq_reset_indices(struct otx_ep_droq *droq)\n {\n", "prefixes": [ "v3", "07/11" ] }