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{
    "id": 86822,
    "url": "https://patches.dpdk.org/api/patches/86822/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210118203508.1332-3-aboyer@pensando.io/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210118203508.1332-3-aboyer@pensando.io>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210118203508.1332-3-aboyer@pensando.io",
    "date": "2021-01-18T20:34:57",
    "name": "[02/13] net/ionic: observe endianness in firmware commands",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "c6d2dc1fa6cd08acea6942df07e0414836923795",
    "submitter": {
        "id": 2036,
        "url": "https://patches.dpdk.org/api/people/2036/?format=api",
        "name": "Andrew Boyer",
        "email": "aboyer@pensando.io"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210118203508.1332-3-aboyer@pensando.io/mbox/",
    "series": [
        {
            "id": 14820,
            "url": "https://patches.dpdk.org/api/series/14820/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14820",
            "date": "2021-01-18T20:34:55",
            "name": "net/ionic: fixes and optimizations",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/14820/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/86822/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/86822/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "Delivered-To": "patchwork@inbox.dpdk.org",
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            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A1ACA0A03;\n\tMon, 18 Jan 2021 21:35:46 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 39489140E3A;\n\tMon, 18 Jan 2021 21:35:40 +0100 (CET)",
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        ],
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        "From": "Andrew Boyer <aboyer@pensando.io>",
        "To": "dev@dpdk.org",
        "Cc": "Alfredo Cardigliano <cardigliano@ntop.org>,\n Andrew Boyer <aboyer@pensando.io>",
        "Date": "Mon, 18 Jan 2021 12:34:57 -0800",
        "Message-Id": "<20210118203508.1332-3-aboyer@pensando.io>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20210118203508.1332-1-aboyer@pensando.io>",
        "References": "<20210118203508.1332-1-aboyer@pensando.io>",
        "Subject": "[dpdk-dev] [PATCH 02/13] net/ionic: observe endianness in firmware\n commands",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The IONIC firmware is little-endian.\n\nSigned-off-by: Andrew Boyer <aboyer@pensando.io>\n---\n drivers/net/ionic/ionic_dev.c    |  27 +++---\n drivers/net/ionic/ionic_ethdev.c |  27 +++---\n drivers/net/ionic/ionic_lif.c    | 138 ++++++++++++++++---------------\n drivers/net/ionic/ionic_main.c   |   6 +-\n 4 files changed, 109 insertions(+), 89 deletions(-)",
    "diff": "diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c\nindex 3507d4166f..c3016b2d50 100644\n--- a/drivers/net/ionic/ionic_dev.c\n+++ b/drivers/net/ionic/ionic_dev.c\n@@ -165,7 +165,7 @@ ionic_dev_cmd_port_init(struct ionic_dev *idev)\n \tunion ionic_dev_cmd cmd = {\n \t\t.port_init.opcode = IONIC_CMD_PORT_INIT,\n \t\t.port_init.index = 0,\n-\t\t.port_init.info_pa = idev->port_info_pa,\n+\t\t.port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa),\n \t};\n \n \tionic_dev_cmd_go(idev, &cmd);\n@@ -202,7 +202,7 @@ ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)\n \t\t.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,\n \t\t.port_setattr.index = 0,\n \t\t.port_setattr.attr = IONIC_PORT_ATTR_SPEED,\n-\t\t.port_setattr.speed = speed,\n+\t\t.port_setattr.speed = rte_cpu_to_le_32(speed),\n \t};\n \n \tionic_dev_cmd_go(idev, &cmd);\n@@ -215,7 +215,7 @@ ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)\n \t\t.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,\n \t\t.port_setattr.index = 0,\n \t\t.port_setattr.attr = IONIC_PORT_ATTR_MTU,\n-\t\t.port_setattr.mtu = mtu,\n+\t\t.port_setattr.mtu = rte_cpu_to_le_32(mtu),\n \t};\n \n \tionic_dev_cmd_go(idev, &cmd);\n@@ -292,7 +292,7 @@ ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa)\n {\n \tunion ionic_dev_cmd cmd = {\n \t\t.lif_init.opcode = IONIC_CMD_LIF_INIT,\n-\t\t.lif_init.info_pa = info_pa,\n+\t\t.lif_init.info_pa = rte_cpu_to_le_64(info_pa),\n \t};\n \n \tionic_dev_cmd_go(idev, &cmd);\n@@ -331,12 +331,12 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq)\n \tunion ionic_dev_cmd cmd = {\n \t\t.q_init.opcode = IONIC_CMD_Q_INIT,\n \t\t.q_init.type = q->type,\n-\t\t.q_init.index = q->index,\n-\t\t.q_init.flags = IONIC_QINIT_F_ENA,\n-\t\t.q_init.intr_index = IONIC_INTR_NONE,\n+\t\t.q_init.index = rte_cpu_to_le_32(q->index),\n+\t\t.q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),\n+\t\t.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n \t\t.q_init.ring_size = rte_log2_u32(q->num_descs),\n-\t\t.q_init.ring_base = q->base_pa,\n-\t\t.q_init.cq_ring_base = cq->base_pa,\n+\t\t.q_init.ring_base = rte_cpu_to_le_64(q->base_pa),\n+\t\t.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n \t};\n \n \tIONIC_PRINT(DEBUG, \"adminq.q_init.ver %u\", cmd.q_init.ver);\n@@ -517,9 +517,14 @@ ionic_adminq_cb(struct ionic_queue *q,\n \tstruct ionic_admin_ctx *ctx = cb_arg;\n \tstruct ionic_admin_comp *cq_desc_base = q->bound_cq->base;\n \tstruct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];\n+\tuint16_t comp_index;\n \n-\tif (unlikely(cq_desc->comp_index != q_desc_index)) {\n-\t\tIONIC_WARN_ON(cq_desc->comp_index != q_desc_index);\n+\tif (!ctx)\n+\t\treturn;\n+\n+\tcomp_index = rte_le_to_cpu_16(cq_desc->comp_index);\n+\tif (unlikely(comp_index != q_desc_index)) {\n+\t\tIONIC_WARN_ON(comp_index != q_desc_index);\n \t\treturn;\n \t}\n \ndiff --git a/drivers/net/ionic/ionic_ethdev.c b/drivers/net/ionic/ionic_ethdev.c\nindex 2face7c635..a5b2301e46 100644\n--- a/drivers/net/ionic/ionic_ethdev.c\n+++ b/drivers/net/ionic/ionic_ethdev.c\n@@ -374,13 +374,15 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,\n \tstruct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);\n \tstruct ionic_adapter *adapter = lif->adapter;\n \tstruct ionic_identity *ident = &adapter->ident;\n+\tunion ionic_lif_config *cfg = &ident->lif.eth.config;\n \n \tIONIC_PRINT_CALL();\n \n \tdev_info->max_rx_queues = (uint16_t)\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);\n \tdev_info->max_tx_queues = (uint16_t)\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);\n+\n \t/* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */\n \tdev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN;\n \tdev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN;\n@@ -389,7 +391,7 @@ ionic_dev_info_get(struct rte_eth_dev *eth_dev,\n \tdev_info->max_mtu = IONIC_MAX_MTU;\n \n \tdev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;\n-\tdev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz;\n+\tdev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz);\n \tdev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;\n \n \tdev_info->speed_capa =\n@@ -534,6 +536,7 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,\n \tstruct ionic_adapter *adapter = lif->adapter;\n \tstruct ionic_identity *ident = &adapter->ident;\n \tuint32_t i, j, index, num;\n+\tuint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz);\n \n \tIONIC_PRINT_CALL();\n \n@@ -543,15 +546,15 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (reta_size != ident->lif.eth.rss_ind_tbl_sz) {\n+\tif (reta_size != tbl_sz) {\n \t\tIONIC_PRINT(ERR, \"The size of hash lookup table configured \"\n \t\t\t\"(%d) does not match the number hardware can support \"\n \t\t\t\"(%d)\",\n-\t\t\treta_size, ident->lif.eth.rss_ind_tbl_sz);\n+\t\t\treta_size, tbl_sz);\n \t\treturn -EINVAL;\n \t}\n \n-\tnum = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE;\n+\tnum = tbl_sz / RTE_RETA_GROUP_SIZE;\n \n \tfor (i = 0; i < num; i++) {\n \t\tfor (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {\n@@ -574,14 +577,15 @@ ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,\n \tstruct ionic_adapter *adapter = lif->adapter;\n \tstruct ionic_identity *ident = &adapter->ident;\n \tint i, num;\n+\tuint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz);\n \n \tIONIC_PRINT_CALL();\n \n-\tif (reta_size != ident->lif.eth.rss_ind_tbl_sz) {\n+\tif (reta_size != tbl_sz) {\n \t\tIONIC_PRINT(ERR, \"The size of hash lookup table configured \"\n \t\t\t\"(%d) does not match the number hardware can support \"\n \t\t\t\"(%d)\",\n-\t\t\treta_size, ident->lif.eth.rss_ind_tbl_sz);\n+\t\t\treta_size, tbl_sz);\n \t\treturn -EINVAL;\n \t}\n \n@@ -1228,11 +1232,12 @@ eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\tgoto err_free_adapter;\n \t}\n \n-\tadapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters;\n+\tadapter->max_mac_addrs =\n+\t\trte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters);\n \n-\tif (adapter->ident.dev.nlifs != 1) {\n+\tif (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) {\n \t\tIONIC_PRINT(ERR, \"Unexpected request for %d LIFs\",\n-\t\t\tadapter->ident.dev.nlifs);\n+\t\t\trte_le_to_cpu_32(adapter->ident.dev.nlifs));\n \t\tgoto err_free_adapter;\n \t}\n \ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex 856e977186..15e291b604 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -25,7 +25,7 @@ ionic_qcq_enable(struct ionic_qcq *qcq)\n \t\t.cmd.q_control = {\n \t\t\t.opcode = IONIC_CMD_Q_CONTROL,\n \t\t\t.type = q->type,\n-\t\t\t.index = q->index,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n \t\t\t.oper = IONIC_Q_ENABLE,\n \t\t},\n \t};\n@@ -43,7 +43,7 @@ ionic_qcq_disable(struct ionic_qcq *qcq)\n \t\t.cmd.q_control = {\n \t\t\t.opcode = IONIC_CMD_Q_CONTROL,\n \t\t\t.type = q->type,\n-\t\t\t.index = q->index,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n \t\t\t.oper = IONIC_Q_DISABLE,\n \t\t},\n \t};\n@@ -241,7 +241,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)\n \t\t.pending_work = true,\n \t\t.cmd.rx_filter_add = {\n \t\t\t.opcode = IONIC_CMD_RX_FILTER_ADD,\n-\t\t\t.match = IONIC_RX_FILTER_MATCH_MAC,\n+\t\t\t.match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC),\n \t\t},\n \t};\n \tint err;\n@@ -253,7 +253,7 @@ ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr)\n \t\treturn err;\n \n \tIONIC_PRINT(INFO, \"rx_filter add (id %d)\",\n-\t\tctx.comp.rx_filter_add.filter_id);\n+\t\trte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));\n \n \treturn ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);\n }\n@@ -280,7 +280,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)\n \t\treturn -ENOENT;\n \t}\n \n-\tctx.cmd.rx_filter_del.filter_id = f->filter_id;\n+\tctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);\n \tionic_rx_filter_free(f);\n \n \trte_spinlock_unlock(&lif->rx_filters.lock);\n@@ -290,7 +290,7 @@ ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr)\n \t\treturn err;\n \n \tIONIC_PRINT(INFO, \"rx_filter del (id %d)\",\n-\t\tctx.cmd.rx_filter_del.filter_id);\n+\t\trte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));\n \n \treturn 0;\n }\n@@ -364,8 +364,8 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)\n \t\t.pending_work = true,\n \t\t.cmd.rx_filter_add = {\n \t\t\t.opcode = IONIC_CMD_RX_FILTER_ADD,\n-\t\t\t.match = IONIC_RX_FILTER_MATCH_VLAN,\n-\t\t\t.vlan.vlan = vid,\n+\t\t\t.match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN),\n+\t\t\t.vlan.vlan = rte_cpu_to_le_16(vid),\n \t\t},\n \t};\n \tint err;\n@@ -375,7 +375,7 @@ ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid)\n \t\treturn err;\n \n \tIONIC_PRINT(INFO, \"rx_filter add VLAN %d (id %d)\", vid,\n-\t\tctx.comp.rx_filter_add.filter_id);\n+\t\trte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id));\n \n \treturn ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx);\n }\n@@ -402,7 +402,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)\n \t\treturn -ENOENT;\n \t}\n \n-\tctx.cmd.rx_filter_del.filter_id = f->filter_id;\n+\tctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id);\n \tionic_rx_filter_free(f);\n \trte_spinlock_unlock(&lif->rx_filters.lock);\n \n@@ -411,7 +411,7 @@ ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid)\n \t\treturn err;\n \n \tIONIC_PRINT(INFO, \"rx_filter del VLAN %d (id %d)\", vid,\n-\t\tctx.cmd.rx_filter_del.filter_id);\n+\t\trte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id));\n \n \treturn 0;\n }\n@@ -438,7 +438,7 @@ ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode)\n \t\t.pending_work = true,\n \t\t.cmd.rx_mode_set = {\n \t\t\t.opcode = IONIC_CMD_RX_MODE_SET,\n-\t\t\t.rx_mode = rx_mode,\n+\t\t\t.rx_mode = rte_cpu_to_le_16(rx_mode),\n \t\t},\n \t};\n \tint err;\n@@ -530,7 +530,7 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)\n \t\t.cmd.lif_setattr = {\n \t\t\t.opcode = IONIC_CMD_LIF_SETATTR,\n \t\t\t.attr = IONIC_LIF_ATTR_MTU,\n-\t\t\t.mtu = new_mtu,\n+\t\t\t.mtu = rte_cpu_to_le_32(new_mtu),\n \t\t},\n \t};\n \tint err;\n@@ -942,16 +942,19 @@ int\n ionic_lif_rss_config(struct ionic_lif *lif,\n \t\tconst uint16_t types, const uint8_t *key, const uint32_t *indir)\n {\n+\tstruct ionic_adapter *adapter = lif->adapter;\n \tstruct ionic_admin_ctx ctx = {\n \t\t.pending_work = true,\n \t\t.cmd.lif_setattr = {\n \t\t\t.opcode = IONIC_CMD_LIF_SETATTR,\n \t\t\t.attr = IONIC_LIF_ATTR_RSS,\n-\t\t\t.rss.types = types,\n-\t\t\t.rss.addr = lif->rss_ind_tbl_pa,\n+\t\t\t.rss.types = rte_cpu_to_le_16(types),\n+\t\t\t.rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa),\n \t\t},\n \t};\n \tunsigned int i;\n+\tuint16_t tbl_sz =\n+\t\trte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);\n \n \tIONIC_PRINT_CALL();\n \n@@ -961,7 +964,7 @@ ionic_lif_rss_config(struct ionic_lif *lif,\n \t\tmemcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);\n \n \tif (indir)\n-\t\tfor (i = 0; i < lif->adapter->ident.lif.eth.rss_ind_tbl_sz; i++)\n+\t\tfor (i = 0; i < tbl_sz; i++)\n \t\t\tlif->rss_ind_tbl[i] = indir[i];\n \n \tmemcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,\n@@ -973,6 +976,7 @@ ionic_lif_rss_config(struct ionic_lif *lif,\n static int\n ionic_lif_rss_setup(struct ionic_lif *lif)\n {\n+\tstruct ionic_adapter *adapter = lif->adapter;\n \tstatic const uint8_t toeplitz_symmetric_key[] = {\n \t\t0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,\n \t\t0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,\n@@ -981,7 +985,8 @@ ionic_lif_rss_setup(struct ionic_lif *lif)\n \t\t0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A,\n \t};\n \tuint32_t i;\n-\tuint16_t tbl_sz = lif->adapter->ident.lif.eth.rss_ind_tbl_sz;\n+\tuint16_t tbl_sz =\n+\t\trte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz);\n \n \tIONIC_PRINT_CALL();\n \n@@ -1107,7 +1112,8 @@ ionic_link_status_check(struct ionic_lif *lif)\n \t\treturn;\n \n \tif (link_up) {\n-\t\tadapter->link_speed = lif->info->status.link_speed;\n+\t\tadapter->link_speed =\n+\t\t\trte_le_to_cpu_32(lif->info->status.link_speed);\n \t\tIONIC_PRINT(DEBUG, \"Link up - %d Gbps\",\n \t\t\tadapter->link_speed);\n \t} else {\n@@ -1230,7 +1236,7 @@ ionic_lif_adminq_init(struct ionic_lif *lif)\n \tionic_dev_cmd_comp(idev, &comp);\n \n \tq->hw_type = comp.hw_type;\n-\tq->hw_index = comp.hw_index;\n+\tq->hw_index = rte_le_to_cpu_32(comp.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \tIONIC_PRINT(DEBUG, \"adminq->hw_type %d\", q->hw_type);\n@@ -1255,18 +1261,17 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)\n \t\t.cmd.q_init = {\n \t\t\t.opcode = IONIC_CMD_Q_INIT,\n \t\t\t.type = q->type,\n-\t\t\t.index = q->index,\n-\t\t\t.flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),\n-\t\t\t.intr_index = qcq->intr.index,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n+\t\t\t.intr_index = rte_cpu_to_le_16(qcq->intr.index),\n+\t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ |\n+\t\t\t\t\t\tIONIC_QINIT_F_ENA),\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.ring_base = q->base_pa,\n+\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n \t\t}\n \t};\n \n-\tIONIC_PRINT(DEBUG, \"notifyq_init.index %d\",\n-\t\tctx.cmd.q_init.index);\n-\tIONIC_PRINT(DEBUG, \"notifyq_init.ring_base 0x%\" PRIx64 \"\",\n-\t\tctx.cmd.q_init.ring_base);\n+\tIONIC_PRINT(DEBUG, \"notifyq_init.index %d\", q->index);\n+\tIONIC_PRINT(DEBUG, \"notifyq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"notifyq_init.ring_size %d\",\n \t\tctx.cmd.q_init.ring_size);\n \tIONIC_PRINT(DEBUG, \"notifyq_init.ver %u\", ctx.cmd.q_init.ver);\n@@ -1276,7 +1281,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)\n \t\treturn err;\n \n \tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = ctx.comp.q_init.hw_index;\n+\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n \tq->db = NULL;\n \n \tIONIC_PRINT(DEBUG, \"notifyq->hw_type %d\", q->hw_type);\n@@ -1299,7 +1304,7 @@ ionic_lif_set_features(struct ionic_lif *lif)\n \t\t.cmd.lif_setattr = {\n \t\t\t.opcode = IONIC_CMD_LIF_SETATTR,\n \t\t\t.attr = IONIC_LIF_ATTR_FEATURES,\n-\t\t\t.features = lif->features,\n+\t\t\t.features = rte_cpu_to_le_64(lif->features),\n \t\t},\n \t};\n \tint err;\n@@ -1308,8 +1313,8 @@ ionic_lif_set_features(struct ionic_lif *lif)\n \tif (err)\n \t\treturn err;\n \n-\tlif->hw_features = (ctx.cmd.lif_setattr.features &\n-\t\tctx.comp.lif_setattr.features);\n+\tlif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features &\n+\t\t\t\t\t\tctx.comp.lif_setattr.features);\n \n \tif (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)\n \t\tIONIC_PRINT(DEBUG, \"feature IONIC_ETH_HW_VLAN_TX_TAG\");\n@@ -1360,20 +1365,20 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)\n \t\t.cmd.q_init = {\n \t\t\t.opcode = IONIC_CMD_Q_INIT,\n \t\t\t.type = q->type,\n-\t\t\t.index = q->index,\n-\t\t\t.flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,\n-\t\t\t.intr_index = IONIC_INTR_NONE,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n+\t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |\n+\t\t\t\t\t\tIONIC_QINIT_F_ENA),\n+\t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.ring_base = q->base_pa,\n-\t\t\t.cq_ring_base = cq->base_pa,\n-\t\t\t.sg_ring_base = q->sg_base_pa,\n+\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n+\t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n+\t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n \t};\n \tint err;\n \n-\tIONIC_PRINT(DEBUG, \"txq_init.index %d\", ctx.cmd.q_init.index);\n-\tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\",\n-\t\tctx.cmd.q_init.ring_base);\n+\tIONIC_PRINT(DEBUG, \"txq_init.index %d\", q->index);\n+\tIONIC_PRINT(DEBUG, \"txq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"txq_init.ring_size %d\",\n \t\tctx.cmd.q_init.ring_size);\n \tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx.cmd.q_init.ver);\n@@ -1383,7 +1388,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)\n \t\treturn err;\n \n \tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = ctx.comp.q_init.hw_index;\n+\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \tIONIC_PRINT(DEBUG, \"txq->hw_type %d\", q->hw_type);\n@@ -1406,20 +1411,20 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)\n \t\t.cmd.q_init = {\n \t\t\t.opcode = IONIC_CMD_Q_INIT,\n \t\t\t.type = q->type,\n-\t\t\t.index = q->index,\n-\t\t\t.flags = IONIC_QINIT_F_SG | IONIC_QINIT_F_ENA,\n-\t\t\t.intr_index = IONIC_INTR_NONE,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n+\t\t\t.flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG |\n+\t\t\t\t\t\tIONIC_QINIT_F_ENA),\n+\t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n \t\t\t.ring_size = rte_log2_u32(q->num_descs),\n-\t\t\t.ring_base = q->base_pa,\n-\t\t\t.cq_ring_base = cq->base_pa,\n-\t\t\t.sg_ring_base = q->sg_base_pa,\n+\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n+\t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n+\t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n \t\t},\n \t};\n \tint err;\n \n-\tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", ctx.cmd.q_init.index);\n-\tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\",\n-\t\tctx.cmd.q_init.ring_base);\n+\tIONIC_PRINT(DEBUG, \"rxq_init.index %d\", q->index);\n+\tIONIC_PRINT(DEBUG, \"rxq_init.ring_base 0x%\" PRIx64 \"\", q->base_pa);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ring_size %d\",\n \t\tctx.cmd.q_init.ring_size);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx.cmd.q_init.ver);\n@@ -1429,7 +1434,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)\n \t\treturn err;\n \n \tq->hw_type = ctx.comp.q_init.hw_type;\n-\tq->hw_index = ctx.comp.q_init.hw_index;\n+\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n \tq->db = ionic_db_map(lif, q);\n \n \tqcq->flags |= IONIC_QCQ_F_INITED;\n@@ -1496,7 +1501,7 @@ ionic_lif_init(struct ionic_lif *lif)\n \tif (err)\n \t\treturn err;\n \n-\tlif->hw_index = comp.hw_index;\n+\tlif->hw_index = rte_cpu_to_le_16(comp.hw_index);\n \n \terr = ionic_lif_adminq_init(lif);\n \tif (err)\n@@ -1582,10 +1587,11 @@ ionic_lif_configure(struct ionic_lif *lif)\n \tstruct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode;\n \tstruct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode;\n \tstruct ionic_identity *ident = &lif->adapter->ident;\n+\tunion ionic_lif_config *cfg = &ident->lif.eth.config;\n \tuint32_t ntxqs_per_lif =\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);\n \tuint32_t nrxqs_per_lif =\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);\n \tuint32_t nrxqs = lif->eth_dev->data->nb_rx_queues;\n \tuint32_t ntxqs = lif->eth_dev->data->nb_tx_queues;\n \n@@ -1722,6 +1728,7 @@ ionic_lif_identify(struct ionic_adapter *adapter)\n {\n \tstruct ionic_dev *idev = &adapter->idev;\n \tstruct ionic_identity *ident = &adapter->ident;\n+\tunion ionic_lif_config *cfg = &ident->lif.eth.config;\n \tint err;\n \tunsigned int i;\n \tunsigned int lif_words = sizeof(ident->lif.words) /\n@@ -1741,23 +1748,23 @@ ionic_lif_identify(struct ionic_adapter *adapter)\n \t\tident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]);\n \n \tIONIC_PRINT(INFO, \"capabilities 0x%\" PRIx64 \" \",\n-\t\tident->lif.capabilities);\n+\t\trte_le_to_cpu_64(ident->lif.capabilities));\n \n \tIONIC_PRINT(INFO, \"eth.max_ucast_filters 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.max_ucast_filters);\n+\t\trte_le_to_cpu_32(ident->lif.eth.max_ucast_filters));\n \tIONIC_PRINT(INFO, \"eth.max_mcast_filters 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.max_mcast_filters);\n+\t\trte_le_to_cpu_32(ident->lif.eth.max_mcast_filters));\n \n \tIONIC_PRINT(INFO, \"eth.features 0x%\" PRIx64 \" \",\n-\t\tident->lif.eth.config.features);\n+\t\trte_le_to_cpu_64(cfg->features));\n \tIONIC_PRINT(INFO, \"eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_ADMINQ]);\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ]));\n \tIONIC_PRINT(INFO, \"eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_NOTIFYQ]);\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ]));\n \tIONIC_PRINT(INFO, \"eth.queue_count[IONIC_QTYPE_RXQ] 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]);\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]));\n \tIONIC_PRINT(INFO, \"eth.queue_count[IONIC_QTYPE_TXQ] 0x%\" PRIx32 \" \",\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]);\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]));\n \n \treturn 0;\n }\n@@ -1766,12 +1773,13 @@ int\n ionic_lifs_size(struct ionic_adapter *adapter)\n {\n \tstruct ionic_identity *ident = &adapter->ident;\n-\tuint32_t nintrs, dev_nintrs = ident->dev.nintrs;\n+\tunion ionic_lif_config *cfg = &ident->lif.eth.config;\n+\tuint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs);\n \n \tadapter->max_ntxqs_per_lif =\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]);\n \tadapter->max_nrxqs_per_lif =\n-\t\tident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];\n+\t\trte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]);\n \n \tnintrs = 1 /* notifyq */;\n \ndiff --git a/drivers/net/ionic/ionic_main.c b/drivers/net/ionic/ionic_main.c\nindex 467696a546..3f15a6f2f2 100644\n--- a/drivers/net/ionic/ionic_main.c\n+++ b/drivers/net/ionic/ionic_main.c\n@@ -340,8 +340,10 @@ ionic_port_identify(struct ionic_adapter *adapter)\n \t\t\t\tioread32(&idev->dev_cmd->data[i]);\n \t}\n \n-\tIONIC_PRINT(INFO, \"speed %d\", ident->port.config.speed);\n-\tIONIC_PRINT(INFO, \"mtu %d\", ident->port.config.mtu);\n+\tIONIC_PRINT(INFO, \"speed %d\",\n+\t\trte_le_to_cpu_32(ident->port.config.speed));\n+\tIONIC_PRINT(INFO, \"mtu %d\",\n+\t\trte_le_to_cpu_32(ident->port.config.mtu));\n \tIONIC_PRINT(INFO, \"state %d\", ident->port.config.state);\n \tIONIC_PRINT(INFO, \"an_enable %d\", ident->port.config.an_enable);\n \tIONIC_PRINT(INFO, \"fec_type %d\", ident->port.config.fec_type);\n",
    "prefixes": [
        "02/13"
    ]
}