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GET /api/patches/86727/?format=api
{ "id": 86727, "url": "https://patches.dpdk.org/api/patches/86727/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210117102123.19045-5-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210117102123.19045-5-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210117102123.19045-5-shirik@nvidia.com", "date": "2021-01-17T10:21:18", "name": "[v7,4/9] common/mlx5: check GENEVE TLV support in HCA attributes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b719d747844975cb20bed9e5a7ecdf86546bdb4f", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210117102123.19045-5-shirik@nvidia.com/mbox/", "series": [ { "id": 14793, "url": "https://patches.dpdk.org/api/series/14793/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14793", "date": "2021-01-17T10:21:14", "name": "ethdev: introduce GENEVE header TLV option item", "version": 7, "mbox": "https://patches.dpdk.org/series/14793/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/86727/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/86727/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E2F44A09E4;\n\tSun, 17 Jan 2021 11:22:27 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 51F3D140DD8;\n\tSun, 17 Jan 2021 11:22:15 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by mails.dpdk.org (Postfix) with ESMTP id 22BFB140DD2\n for <dev@dpdk.org>; Sun, 17 Jan 2021 11:22:13 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 17 Jan 2021 12:22:09 +0200", "from nvidia.com (c-141-140-1-007.mtl.labs.mlnx [10.141.140.7])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10HALkmJ003653;\n Sun, 17 Jan 2021 12:22:09 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, orika@nvidia.com,\n ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com,\n andrew.rybchenko@oktetlabs.ru", "Date": "Sun, 17 Jan 2021 12:21:18 +0200", "Message-Id": "<20210117102123.19045-5-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20210117102123.19045-1-shirik@nvidia.com>", "References": "<20210114070743.2377-1-shirik@nvidia.com>\n <20210117102123.19045-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v7 4/9] common/mlx5: check GENEVE TLV support in\n HCA attributes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This is preparation step to support match on GENEVE TLV option.\n\nIn this Patch we add the HCA attributes that will allow\nsupporting GENEVE TLV option matching.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 7 +++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 4 ++++\n drivers/common/mlx5/mlx5_prm.h | 28 +++++++++++++++++++++++++---\n 3 files changed, 36 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 4d01f52986..861f75e47d 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -690,6 +690,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);\n \tattr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t flex_parser_protocols);\n+\tattr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tmax_geneve_tlv_options);\n+\tattr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\tmax_geneve_tlv_option_data_len);\n \tattr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);\n \tattr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n@@ -717,6 +721,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n \t\t\t\t\t general_obj_types) &\n \t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);\n+\tattr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr,\n+\t\t\t\t\t general_obj_types) &\n+\t\t\t\tMLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);\n \tattr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);\n \tattr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);\n \tattr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 8d993dfad7..1e0a48d810 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -97,6 +97,8 @@ struct mlx5_hca_attr {\n \tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n \tuint16_t lro_min_mss_size;\n \tuint32_t flex_parser_protocols;\n+\tuint32_t max_geneve_tlv_options;\n+\tuint32_t max_geneve_tlv_option_data_len;\n \tuint32_t hairpin:1;\n \tuint32_t log_max_hairpin_queues:5;\n \tuint32_t log_max_hairpin_wq_data_sz:5;\n@@ -116,6 +118,7 @@ struct mlx5_hca_attr {\n \tuint32_t regex:1;\n \tuint32_t regexp_num_of_engines;\n \tuint32_t log_max_ft_sampler_num:8;\n+\tuint32_t geneve_tlv_opt;\n \tstruct mlx5_hca_qos_attr qos;\n \tstruct mlx5_hca_vdpa_attr vdpa;\n \tint log_max_qp_sz;\n@@ -481,6 +484,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,\n __rte_internal\n int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,\n \t\t\t\tuint32_t arg, uint32_t *data, uint32_t dw_cnt);\n+\n /**\n * Create virtio queue counters object DevX API.\n *\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex ad07e79d78..c9eba22ad7 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -789,7 +789,7 @@ struct mlx5_ifc_fte_match_set_misc3_bits {\n \tu8 icmp_code[0x8];\n \tu8 icmpv6_type[0x8];\n \tu8 icmpv6_code[0x8];\n-\tu8 reserved_at_120[0x20];\n+\tu8 geneve_tlv_option_0_data[0x20];\n \tu8 gtpu_teid[0x20];\n \tu8 gtpu_msg_type[0x08];\n \tu8 gtpu_msg_flags[0x08];\n@@ -1087,6 +1087,8 @@ enum {\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)\n #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \\\n \t\t\t(1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)\n+#define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \\\n+\t\t\t(1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT)\n \n enum {\n \tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n@@ -1385,8 +1387,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_500[0x20];\n \tu8 num_of_uars_per_page[0x20];\n \tu8 flex_parser_protocols[0x20];\n-\tu8 reserved_at_560[0x20];\n-\tu8 reserved_at_580[0x3c];\n+\tu8 max_geneve_tlv_options[0x8];\n+\tu8 reserved_at_568[0x3];\n+\tu8 max_geneve_tlv_option_data_len[0x5];\n+\tu8 reserved_at_570[0x4c];\n \tu8 mini_cqe_resp_stride_index[0x1];\n \tu8 cqe_128_always[0x1];\n \tu8 cqe_compression_128[0x1];\n@@ -2297,6 +2301,7 @@ struct mlx5_ifc_create_cq_in_bits {\n };\n \n enum {\n+\tMLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,\n \tMLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,\n \tMLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,\n@@ -2331,6 +2336,17 @@ struct mlx5_ifc_virtio_q_counters_bits {\n \tu8 reserved_at_180[0x50];\n };\n \n+struct mlx5_ifc_geneve_tlv_option_bits {\n+\tu8 modify_field_select[0x40];\n+\tu8 reserved_at_40[0x18];\n+\tu8 geneve_option_fte_index[0x8];\n+\tu8 option_class[0x10];\n+\tu8 option_type[0x8];\n+\tu8 reserved_at_78[0x3];\n+\tu8 option_data_length[0x5];\n+\tu8 reserved_at_80[0x180];\n+};\n+\n struct mlx5_ifc_create_virtio_q_counters_in_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n@@ -2340,6 +2356,12 @@ struct mlx5_ifc_query_virtio_q_counters_out_bits {\n \tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n \tstruct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;\n };\n+\n+struct mlx5_ifc_create_geneve_tlv_option_in_bits {\n+\tstruct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;\n+\tstruct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;\n+};\n+\n enum {\n \tMLX5_VIRTQ_STATE_INIT = 0,\n \tMLX5_VIRTQ_STATE_RDY = 1,\n", "prefixes": [ "v7", "4/9" ] }