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GET /api/patches/85732/?format=api
{ "id": 85732, "url": "https://patches.dpdk.org/api/patches/85732/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201225080358.366162-1-asomalap@amd.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201225080358.366162-1-asomalap@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201225080358.366162-1-asomalap@amd.com", "date": "2020-12-25T08:03:58", "name": "[v3] crypto/ccp: enable IOMMU for CCP", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7fe930c7e524244fd6023af30a56ef7c04aaa846", "submitter": { "id": 1439, "url": "https://patches.dpdk.org/api/people/1439/?format=api", "name": "AMARANATH SOMALAPURAM", "email": "asomalap@amd.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201225080358.366162-1-asomalap@amd.com/mbox/", "series": [ { "id": 14464, "url": "https://patches.dpdk.org/api/series/14464/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14464", "date": "2020-12-25T08:03:58", "name": "[v3] crypto/ccp: enable IOMMU for CCP", "version": 3, "mbox": "https://patches.dpdk.org/series/14464/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85732/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/85732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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"=?utf-8?q?QwYycaFYEPSe49xCBZwtjNOjmE+a+q?=\n\t=?utf-8?q?HOerMeKqP5/Zwf9Z5yd5aRBpnv51YCy8ic941VFU9e8Uxh2Opd72QJXCxona6HH2s?=\n\t=?utf-8?q?ETDdH9/ft+nq/Q3p7wn8Mq1KQi6B5cZ+Dt1PTsME4NSWtiW7xH5LdeW6qP+6uDvPF?=\n\t=?utf-8?q?kDHFwutgWt6VdgUNMaozlGD6dL3vVLsbkqm35v28lfyWYSWVnBFWrczPBgKAQgY79?=\n\t=?utf-8?q?EMirdJnxVg5SxrtLgMCydtOGmEmd0pGU2Ajguv23TYPFU42AM157aNVE1N2QPUzu2?=\n\t=?utf-8?q?xvF3o+eK6HfmaZzkNfJR8zFaXn7pJYxy5rGldK38IdnoRLbVLgBBpc8C7YNJosg1L?=\n\t=?utf-8?q?p7OdLStpzl6gZovTV+1p8G5NIz+ze9Sk0iUp9qUy3Y94X66lWp/ItEu+NjIqNcX2t?=\n\t=?utf-8?q?3XxnM3LFxvNyKh7iqyP6HhySdGVBecCSC9Du4/j/l5wKZpyFX4MW6lA9/HjEQ6QLK?=\n\t=?utf-8?q?Nx8xEP+8fq+Mk7K/U3nL8IB7r/1ykIf2+cVXNf0u+7bf111haRVWtPvSRdKKPrfhw?=\n\t=?utf-8?q?rZv7Rvcr//koE3izBzhTHi/ZhTM9F5l8J8Sp71KfAv+TodmmT3mD+mtadaHjas8yk?=\n\t=?utf-8?q?8pYDOlmylW0IxSuY3T4+THJrOo0/W7bFeKk716vH6BZGcOQO2xWHxxVF4HMR0T6+x?=\n\t=?utf-8?q?arghNwzMRCxdaCP13fkyjb/c/ysCe0qlMl4GIgRGgVWbblvQcJFicZL+cg5X4iMO1?=\n\t=?utf-8?q?bd3MtiwnKiRjXz8Jqu4Qd1ArjGNOdccMNL0Voz257YYkzfmIWu3ni5GbaqBeYz6vC?=\n\t=?utf-8?q?euu4VeYF1MgSVyq/H4GK9ODoxaI2tnsC2eLhOi7KuIFucI/JDbuhxJe18kKCNUPbr?=\n\t=?utf-8?q?x4IA/6UCB+HVRm0ZIUWoqr5iO1EUaGmF93r3u+30GkLEYEazX8/H/iB+AVgio8otH?=\n\t=?utf-8?q?EwrB/acB/7KmVfnlE5b+MjYnqg8PLBZUtR2YbIfYsWv0p5NFo38uJcOvYkzXjVw+Y?=\n\t=?utf-8?q?I4TVpFcA9MDANWlfSve?=", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-AuthSource": "BYAPR12MB2821.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Dec 2020 08:06:18.0553 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3dfcb5eb-71ed-48ac-a2a8-08d8a8abf552", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n Rr9qxgqgUYYPePctiqWmmp65mRM4cBCvJXtKJCFEccENOgtFd3sltwvV+5nT6l96WK86HoqWrV92QlXyHRHZOQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4885", "Subject": "[dpdk-dev] [PATCH v3] crypto/ccp: enable IOMMU for CCP", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Amaranath Somalapuram <Amaranath.Somalapuram@amd.com>\n\nCCP use vdev framework, and vdev framework don’t support IOMMU.\nAdding custom IOMMU support for AMD CCP driver.\n\nSigned-off-by: Amaranath Somalapuram <Amaranath.Somalapuram@amd.com>\n---\n drivers/crypto/ccp/ccp_crypto.c | 114 ++++++++++++++++++++++++-------\n drivers/crypto/ccp/ccp_dev.c | 54 +++------------\n drivers/crypto/ccp/ccp_pci.c | 1 +\n drivers/crypto/ccp/rte_ccp_pmd.c | 3 +\n 4 files changed, 104 insertions(+), 68 deletions(-)", "diff": "diff --git a/drivers/crypto/ccp/ccp_crypto.c b/drivers/crypto/ccp/ccp_crypto.c\nindex db3fb6eff..f37d35f18 100644\n--- a/drivers/crypto/ccp/ccp_crypto.c\n+++ b/drivers/crypto/ccp/ccp_crypto.c\n@@ -31,8 +31,10 @@\n #include <openssl/err.h>\n #include <openssl/hmac.h>\n \n+extern int iommu_mode;\n+void *sha_ctx;\n /* SHA initial context values */\n-static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = {\n+uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = {\n \tSHA1_H4, SHA1_H3,\n \tSHA1_H2, SHA1_H1,\n \tSHA1_H0, 0x0U,\n@@ -744,8 +746,13 @@ ccp_configure_session_cipher(struct ccp_session *sess,\n \t\tCCP_LOG_ERR(\"Invalid CCP Engine\");\n \t\treturn -ENOTSUP;\n \t}\n-\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n-\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\tif (iommu_mode == 2) {\n+\t\tsess->cipher.nonce_phys = rte_mem_virt2iova(sess->cipher.nonce);\n+\t\tsess->cipher.key_phys = rte_mem_virt2iova(sess->cipher.key_ccp);\n+\t} else {\n+\t\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n+\t\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\t}\n \treturn 0;\n }\n \n@@ -784,6 +791,7 @@ ccp_configure_session_auth(struct ccp_session *sess,\n \t\tsess->auth.ctx = (void *)ccp_sha1_init;\n \t\tsess->auth.ctx_len = CCP_SB_BYTES;\n \t\tsess->auth.offset = CCP_SB_BYTES - SHA1_DIGEST_SIZE;\n+\t\trte_memcpy(sha_ctx, sess->auth.ctx, SHA_COMMON_DIGEST_SIZE);\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n \t\tif (sess->auth_opt) {\n@@ -822,6 +830,7 @@ ccp_configure_session_auth(struct ccp_session *sess,\n \t\tsess->auth.ctx = (void *)ccp_sha224_init;\n \t\tsess->auth.ctx_len = CCP_SB_BYTES;\n \t\tsess->auth.offset = CCP_SB_BYTES - SHA224_DIGEST_SIZE;\n+\t\trte_memcpy(sha_ctx, sess->auth.ctx, SHA256_DIGEST_SIZE);\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n \t\tif (sess->auth_opt) {\n@@ -884,6 +893,7 @@ ccp_configure_session_auth(struct ccp_session *sess,\n \t\tsess->auth.ctx = (void *)ccp_sha256_init;\n \t\tsess->auth.ctx_len = CCP_SB_BYTES;\n \t\tsess->auth.offset = CCP_SB_BYTES - SHA256_DIGEST_SIZE;\n+\t\trte_memcpy(sha_ctx, sess->auth.ctx, SHA256_DIGEST_SIZE);\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n \t\tif (sess->auth_opt) {\n@@ -946,6 +956,7 @@ ccp_configure_session_auth(struct ccp_session *sess,\n \t\tsess->auth.ctx = (void *)ccp_sha384_init;\n \t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n \t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA384_DIGEST_SIZE;\n+\t\trte_memcpy(sha_ctx, sess->auth.ctx, SHA512_DIGEST_SIZE);\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n \t\tif (sess->auth_opt) {\n@@ -1010,6 +1021,7 @@ ccp_configure_session_auth(struct ccp_session *sess,\n \t\tsess->auth.ctx = (void *)ccp_sha512_init;\n \t\tsess->auth.ctx_len = CCP_SB_BYTES << 1;\n \t\tsess->auth.offset = (CCP_SB_BYTES << 1) - SHA512_DIGEST_SIZE;\n+\t\trte_memcpy(sha_ctx, sess->auth.ctx, SHA512_DIGEST_SIZE);\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n \t\tif (sess->auth_opt) {\n@@ -1159,8 +1171,13 @@ ccp_configure_session_aead(struct ccp_session *sess,\n \t\tCCP_LOG_ERR(\"Unsupported aead algo\");\n \t\treturn -ENOTSUP;\n \t}\n-\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n-\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\tif (iommu_mode == 2) {\n+\t\tsess->cipher.nonce_phys = rte_mem_virt2iova(sess->cipher.nonce);\n+\t\tsess->cipher.key_phys = rte_mem_virt2iova(sess->cipher.key_ccp);\n+\t} else {\n+\t\tsess->cipher.nonce_phys = rte_mem_virt2phy(sess->cipher.nonce);\n+\t\tsess->cipher.key_phys = rte_mem_virt2phy(sess->cipher.key_ccp);\n+\t}\n \treturn 0;\n }\n \n@@ -1575,11 +1592,16 @@ ccp_perform_hmac(struct rte_crypto_op *op,\n \t\t\t\t\t op->sym->auth.data.offset);\n \tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n-\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\tif (iommu_mode == 2) {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2iova(append_ptr);\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)addr);\n+\t} else {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n+\t}\n \tdest_addr_t = dest_addr;\n \n \t/** Load PHash1 to LSB*/\n-\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n \tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n \tpst.len = session->auth.ctx_len;\n \tpst.dir = 1;\n@@ -1659,7 +1681,10 @@ ccp_perform_hmac(struct rte_crypto_op *op,\n \n \t/** Load PHash2 to LSB*/\n \taddr += session->auth.ctx_len;\n-\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n+\tif (iommu_mode == 2)\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2iova((void *)addr);\n+\telse\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)addr);\n \tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n \tpst.len = session->auth.ctx_len;\n \tpst.dir = 1;\n@@ -1745,15 +1770,19 @@ ccp_perform_sha(struct rte_crypto_op *op,\n \n \tsrc_addr = rte_pktmbuf_iova_offset(op->sym->m_src,\n \t\t\t\t\t op->sym->auth.data.offset);\n-\n \tappend_ptr = (void *)rte_pktmbuf_append(op->sym->m_src,\n \t\t\t\t\t\tsession->auth.ctx_len);\n-\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\tif (iommu_mode == 2) {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2iova(append_ptr);\n+\t\tpst.src_addr = (phys_addr_t)sha_ctx;\n+\t} else {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2phy(append_ptr);\n+\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)\n+\t\t\t\t\t\t session->auth.ctx);\n+\t}\n \n \t/** Passthru sha context*/\n \n-\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)\n-\t\t\t\t\t\t session->auth.ctx);\n \tpst.dest_addr = (phys_addr_t)(cmd_q->sb_sha * CCP_SB_BYTES);\n \tpst.len = session->auth.ctx_len;\n \tpst.dir = 1;\n@@ -1840,10 +1869,16 @@ ccp_perform_sha3_hmac(struct rte_crypto_op *op,\n \t\tCCP_LOG_ERR(\"CCP MBUF append failed\\n\");\n \t\treturn -1;\n \t}\n-\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\tif (iommu_mode == 2) {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2iova((void *)append_ptr);\n+\t\tctx_paddr = (phys_addr_t)rte_mem_virt2iova(\n+\t\t\t\t\tsession->auth.pre_compute);\n+\t} else {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\t\tctx_paddr = (phys_addr_t)rte_mem_virt2phy(\n+\t\t\t\t\tsession->auth.pre_compute);\n+\t}\n \tdest_addr_t = dest_addr + (session->auth.ctx_len / 2);\n-\tctx_paddr = (phys_addr_t)rte_mem_virt2phy((void\n-\t\t\t\t\t\t *)session->auth.pre_compute);\n \tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n \tmemset(desc, 0, Q_DESC_SIZE);\n \n@@ -1964,7 +1999,7 @@ ccp_perform_sha3(struct rte_crypto_op *op,\n \tstruct ccp_session *session;\n \tunion ccp_function function;\n \tstruct ccp_desc *desc;\n-\tuint8_t *ctx_addr, *append_ptr;\n+\tuint8_t *ctx_addr = NULL, *append_ptr = NULL;\n \tuint32_t tail;\n \tphys_addr_t src_addr, dest_addr, ctx_paddr;\n \n@@ -1980,9 +2015,15 @@ ccp_perform_sha3(struct rte_crypto_op *op,\n \t\tCCP_LOG_ERR(\"CCP MBUF append failed\\n\");\n \t\treturn -1;\n \t}\n-\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\tif (iommu_mode == 2) {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2iova((void *)append_ptr);\n+\t\tctx_paddr = (phys_addr_t)rte_mem_virt2iova((void *)ctx_addr);\n+\t} else {\n+\t\tdest_addr = (phys_addr_t)rte_mem_virt2phy((void *)append_ptr);\n+\t\tctx_paddr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\t}\n+\n \tctx_addr = session->auth.sha3_ctx;\n-\tctx_paddr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n \n \tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n \tmemset(desc, 0, Q_DESC_SIZE);\n@@ -2056,7 +2097,13 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op,\n \n \t\tctx_addr = session->auth.pre_compute;\n \t\tmemset(ctx_addr, 0, AES_BLOCK_SIZE);\n-\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\t\tif (iommu_mode == 2)\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2iova(\n+\t\t\t\t\t\t\t(void *)ctx_addr);\n+\t\telse\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy(\n+\t\t\t\t\t\t\t(void *)ctx_addr);\n+\n \t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n \t\tpst.len = CCP_SB_BYTES;\n \t\tpst.dir = 1;\n@@ -2094,7 +2141,12 @@ ccp_perform_aes_cmac(struct rte_crypto_op *op,\n \t} else {\n \t\tctx_addr = session->auth.pre_compute + CCP_SB_BYTES;\n \t\tmemset(ctx_addr, 0, AES_BLOCK_SIZE);\n-\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *)ctx_addr);\n+\t\tif (iommu_mode == 2)\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2iova(\n+\t\t\t\t\t\t\t(void *)ctx_addr);\n+\t\telse\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy(\n+\t\t\t\t\t\t\t(void *)ctx_addr);\n \t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n \t\tpst.len = CCP_SB_BYTES;\n \t\tpst.dir = 1;\n@@ -2288,8 +2340,12 @@ ccp_perform_3des(struct rte_crypto_op *op,\n \n \t\trte_memcpy(lsb_buf + (CCP_SB_BYTES - session->iv.length),\n \t\t\t iv, session->iv.length);\n-\n-\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy((void *) lsb_buf);\n+\t\tif (iommu_mode == 2)\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2iova(\n+\t\t\t\t\t\t\t(void *) lsb_buf);\n+\t\telse\n+\t\t\tpst.src_addr = (phys_addr_t)rte_mem_virt2phy(\n+\t\t\t\t\t\t\t(void *) lsb_buf);\n \t\tpst.dest_addr = (phys_addr_t)(cmd_q->sb_iv * CCP_SB_BYTES);\n \t\tpst.len = CCP_SB_BYTES;\n \t\tpst.dir = 1;\n@@ -2312,7 +2368,10 @@ ccp_perform_3des(struct rte_crypto_op *op,\n \telse\n \t\tdest_addr = src_addr;\n \n-\tkey_addr = rte_mem_virt2phy(session->cipher.key_ccp);\n+\tif (iommu_mode == 2)\n+\t\tkey_addr = rte_mem_virt2iova(session->cipher.key_ccp);\n+\telse\n+\t\tkey_addr = rte_mem_virt2phy(session->cipher.key_ccp);\n \n \tdesc = &cmd_q->qbase_desc[cmd_q->qidx];\n \n@@ -2707,8 +2766,13 @@ process_ops_to_enqueue(struct ccp_qp *qp,\n \tb_info->lsb_buf_idx = 0;\n \tb_info->desccnt = 0;\n \tb_info->cmd_q = cmd_q;\n-\tb_info->lsb_buf_phys =\n-\t\t(phys_addr_t)rte_mem_virt2phy((void *)b_info->lsb_buf);\n+\tif (iommu_mode == 2)\n+\t\tb_info->lsb_buf_phys =\n+\t\t\t(phys_addr_t)rte_mem_virt2iova((void *)b_info->lsb_buf);\n+\telse\n+\t\tb_info->lsb_buf_phys =\n+\t\t\t(phys_addr_t)rte_mem_virt2phy((void *)b_info->lsb_buf);\n+\n \trte_atomic64_sub(&b_info->cmd_q->free_slots, slots_req);\n \n \tb_info->head_offset = (uint32_t)(cmd_q->qbase_phys_addr + cmd_q->qidx *\ndiff --git a/drivers/crypto/ccp/ccp_dev.c b/drivers/crypto/ccp/ccp_dev.c\nindex 664ddc174..ee6882b8a 100644\n--- a/drivers/crypto/ccp/ccp_dev.c\n+++ b/drivers/crypto/ccp/ccp_dev.c\n@@ -23,6 +23,7 @@\n #include \"ccp_pci.h\"\n #include \"ccp_pmd_private.h\"\n \n+int iommu_mode;\n struct ccp_list ccp_list = TAILQ_HEAD_INITIALIZER(ccp_list);\n static int ccp_dev_id;\n \n@@ -512,7 +513,7 @@ ccp_add_device(struct ccp_device *dev, int type)\n \n \t\tCCP_WRITE_REG(vaddr, CMD_CLK_GATE_CTL_OFFSET, 0x00108823);\n \t}\n-\tCCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x00001249);\n+\tCCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x0);\n \n \t/* Copy the private LSB mask to the public registers */\n \tstatus_lo = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET);\n@@ -657,9 +658,7 @@ ccp_probe_device(const char *dirname, uint16_t domain,\n \tstruct rte_pci_device *pci;\n \tchar filename[PATH_MAX];\n \tunsigned long tmp;\n-\tint uio_fd = -1, i, uio_num;\n-\tchar uio_devname[PATH_MAX];\n-\tvoid *map_addr;\n+\tint uio_fd = -1;\n \n \tccp_dev = rte_zmalloc(\"ccp_device\", sizeof(*ccp_dev),\n \t\t\t RTE_CACHE_LINE_SIZE);\n@@ -710,46 +709,14 @@ ccp_probe_device(const char *dirname, uint16_t domain,\n \tsnprintf(filename, sizeof(filename), \"%s/resource\", dirname);\n \tif (ccp_pci_parse_sysfs_resource(filename, pci) < 0)\n \t\tgoto fail;\n+\tif (iommu_mode == 2)\n+\t\tpci->kdrv = RTE_PCI_KDRV_VFIO;\n+\telse if (iommu_mode == 0)\n+\t\tpci->kdrv = RTE_PCI_KDRV_IGB_UIO;\n+\telse if (iommu_mode == 1)\n+\t\tpci->kdrv = RTE_PCI_KDRV_UIO_GENERIC;\n \n-\tuio_num = ccp_find_uio_devname(dirname);\n-\tif (uio_num < 0) {\n-\t\t/*\n-\t\t * It may take time for uio device to appear,\n-\t\t * wait here and try again\n-\t\t */\n-\t\tusleep(100000);\n-\t\tuio_num = ccp_find_uio_devname(dirname);\n-\t\tif (uio_num < 0)\n-\t\t\tgoto fail;\n-\t}\n-\tsnprintf(uio_devname, sizeof(uio_devname), \"/dev/uio%u\", uio_num);\n-\n-\tuio_fd = open(uio_devname, O_RDWR | O_NONBLOCK);\n-\tif (uio_fd < 0)\n-\t\tgoto fail;\n-\tif (flock(uio_fd, LOCK_EX | LOCK_NB))\n-\t\tgoto fail;\n-\n-\t/* Map the PCI memory resource of device */\n-\tfor (i = 0; i < PCI_MAX_RESOURCE; i++) {\n-\n-\t\tchar devname[PATH_MAX];\n-\t\tint res_fd;\n-\n-\t\tif (pci->mem_resource[i].phys_addr == 0)\n-\t\t\tcontinue;\n-\t\tsnprintf(devname, sizeof(devname), \"%s/resource%d\", dirname, i);\n-\t\tres_fd = open(devname, O_RDWR);\n-\t\tif (res_fd < 0)\n-\t\t\tgoto fail;\n-\t\tmap_addr = mmap(NULL, pci->mem_resource[i].len,\n-\t\t\t\tPROT_READ | PROT_WRITE,\n-\t\t\t\tMAP_SHARED, res_fd, 0);\n-\t\tif (map_addr == MAP_FAILED)\n-\t\t\tgoto fail;\n-\n-\t\tpci->mem_resource[i].addr = map_addr;\n-\t}\n+\trte_pci_map_device(pci);\n \n \t/* device is valid, add in list */\n \tif (ccp_add_device(ccp_dev, ccp_type)) {\n@@ -784,6 +751,7 @@ ccp_probe_devices(const struct rte_pci_id *ccp_id)\n \tif (module_idx < 0)\n \t\treturn -1;\n \n+\tiommu_mode = module_idx;\n \tTAILQ_INIT(&ccp_list);\n \tdir = opendir(SYSFS_PCI_DEVICES);\n \tif (dir == NULL)\ndiff --git a/drivers/crypto/ccp/ccp_pci.c b/drivers/crypto/ccp/ccp_pci.c\nindex 1702a09c4..38029a908 100644\n--- a/drivers/crypto/ccp/ccp_pci.c\n+++ b/drivers/crypto/ccp/ccp_pci.c\n@@ -15,6 +15,7 @@\n static const char * const uio_module_names[] = {\n \t\"igb_uio\",\n \t\"uio_pci_generic\",\n+\t\"vfio_pci\"\n };\n \n int\ndiff --git a/drivers/crypto/ccp/rte_ccp_pmd.c b/drivers/crypto/ccp/rte_ccp_pmd.c\nindex 000b2f4fe..ba379a19f 100644\n--- a/drivers/crypto/ccp/rte_ccp_pmd.c\n+++ b/drivers/crypto/ccp/rte_ccp_pmd.c\n@@ -22,6 +22,7 @@\n static unsigned int ccp_pmd_init_done;\n uint8_t ccp_cryptodev_driver_id;\n uint8_t cryptodev_cnt;\n+extern void *sha_ctx;\n \n struct ccp_pmd_init_params {\n \tstruct rte_cryptodev_pmd_init_params def_p;\n@@ -305,6 +306,7 @@ cryptodev_ccp_remove(struct rte_vdev_device *dev)\n \n \tccp_pmd_init_done = 0;\n \tname = rte_vdev_device_name(dev);\n+\trte_free(sha_ctx);\n \tif (name == NULL)\n \t\treturn -EINVAL;\n \n@@ -388,6 +390,7 @@ cryptodev_ccp_probe(struct rte_vdev_device *vdev)\n \t};\n \tconst char *input_args;\n \n+\tsha_ctx = (void *)rte_malloc(NULL, SHA512_DIGEST_SIZE, 64);\n \tif (ccp_pmd_init_done) {\n \t\tRTE_LOG(INFO, PMD, \"CCP PMD already initialized\\n\");\n \t\treturn -EFAULT;\n", "prefixes": [ "v3" ] }