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GET /api/patches/85591/?format=api
{ "id": 85591, "url": "https://patches.dpdk.org/api/patches/85591/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201221074518.35083-1-kirankumark@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201221074518.35083-1-kirankumark@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201221074518.35083-1-kirankumark@marvell.com", "date": "2020-12-21T07:45:18", "name": "net/octeontx2: add support for 24B custom L2 header parsing", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7a3b7b18e1d52e0a255e57e818098479fe23a999", "submitter": { "id": 1260, "url": "https://patches.dpdk.org/api/people/1260/?format=api", "name": "Kiran Kumar Kokkilagadda", "email": "kirankumark@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201221074518.35083-1-kirankumark@marvell.com/mbox/", "series": [ { "id": 14401, "url": "https://patches.dpdk.org/api/series/14401/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14401", "date": "2020-12-21T07:45:18", "name": "net/octeontx2: add support for 24B custom L2 header parsing", "version": 1, "mbox": "https://patches.dpdk.org/series/14401/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85591/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85591/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8150FA09EF;\n\tMon, 21 Dec 2020 08:45:34 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B5C6CBD7;\n\tMon, 21 Dec 2020 08:45:33 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 8E405CBB4\n for <dev@dpdk.org>; Mon, 21 Dec 2020 08:45:30 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 0BL7aJb5026875 for <dev@dpdk.org>; Sun, 20 Dec 2020 23:45:28 -0800", "from sc-exch02.marvell.com ([199.233.58.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 35hfru3ghs-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 20 Dec 2020 23:45:28 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com\n (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sun, 20 Dec 2020 23:45:27 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sun, 20 Dec 2020 23:45:27 -0800", "from localhost.localdomain (unknown [10.28.34.15])\n by maili.marvell.com (Postfix) with ESMTP id 086DF3F703F;\n Sun, 20 Dec 2020 23:45:25 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-transfer-encoding :\n content-type; s=pfpt0220; bh=KR2JfgdrcdZHwQkSd90+wTvgfKbVTPqPCL5XsGlXZ8E=;\n b=Kt6nis3BUzhsVMhImaIgjit+o6ee6CpbeM+sw/0f0PdS7GheD4SGRXMU5B+UdoZNZysM\n YBD3vKwyFzwIeqdSgThoK3M6rlnKw1WNTU5FOMy1sM/ofJDZgRO8cyj0J+9cYMVE2tW+\n q7G8DZ7w8sUdU1zEQ1Th2wTZnc3gF8Fqu/1tyhJeukHWZ2pV7oSxJtDw/Iyl2Yf9q7wA\n dOrgidNGp8DMOOQIu6kmKKjk6gj3EVvcyhwjEDLl3LzuUFDNlgA7Ov/233vNMd3WLRLQ\n K6BEYm/JmNZfMCmz2BT28vt+GNCG8CgoouNW0bLvh8vyg2Dhj61dnRsGor+5moazX/8O lg==", "From": "<kirankumark@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 21 Dec 2020 13:15:18 +0530", "Message-ID": "<20201221074518.35083-1-kirankumark@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737\n definitions=2020-12-21_02:2020-12-19,\n 2020-12-21 signatures=0", "Subject": "[dpdk-dev] [PATCH] net/octeontx2: add support for 24B custom L2\n\theader parsing", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kiran Kumar K <kirankumark@marvell.com>\n\nAdding support to parse 24B custom L2 header. Added devargs support to\nconfigure the PKIND, and removed the restriction to support custom\nheaders on non SDP interface.\n\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\n---\n doc/guides/nics/octeontx2.rst | 2 +-\n drivers/common/octeontx2/hw/otx2_npc.h | 21 ++++++++++++++++++++-\n drivers/common/octeontx2/otx2_mbox.h | 15 ++++++++++++++-\n drivers/net/octeontx2/otx2_ethdev.c | 19 +++++++++++++------\n drivers/net/octeontx2/otx2_ethdev_devargs.c | 8 ++++++--\n drivers/net/octeontx2/otx2_rss.c | 2 +-\n 6 files changed, 55 insertions(+), 12 deletions(-)", "diff": "diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex a4f224424..5e1621c1b 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -167,7 +167,7 @@ Runtime Config Options\n \n With the above configuration, higig2 will be enabled on that port and the\n traffic on this port should be higig2 traffic only. Supported switch header\n- types are \"higig2\", \"dsa\" and \"chlen90b\".\n+ types are \"higig2\", \"dsa\", \"chlen90b\" and \"chlen24b\".\n \n - ``RSS tag as XOR`` (default ``0``)\n \ndiff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h\nindex 45e60dfd5..dd507d57a 100644\n--- a/drivers/common/octeontx2/hw/otx2_npc.h\n+++ b/drivers/common/octeontx2/hw/otx2_npc.h\n@@ -185,7 +185,11 @@ enum npc_kpu_la_ltype {\n \tNPC_LT_LA_IH_2_ETHER,\n \tNPC_LT_LA_HIGIG2_ETHER,\n \tNPC_LT_LA_IH_NIX_HIGIG2_ETHER,\n-\tNPC_LT_LA_CH_LEN_90B_ETHER, /* Custom L2 header of length 90 bytes */\n+\tNPC_LT_LA_CUSTOM_L2_90B_ETHER,\n+\tNPC_LT_LA_CPT_HDR,\n+\tNPC_LT_LA_CUSTOM_L2_24B_ETHER,\n+\tNPC_LT_LA_CUSTOM0 = 0xE,\n+\tNPC_LT_LA_CUSTOM1 = 0xF,\n };\n \n enum npc_kpu_lb_ltype {\n@@ -200,6 +204,9 @@ enum npc_kpu_lb_ltype {\n \tNPC_LT_LB_EDSA_VLAN,\n \tNPC_LT_LB_EXDSA,\n \tNPC_LT_LB_EXDSA_VLAN,\n+\tNPC_LT_LB_FDSA,\n+\tNPC_LT_LB_CUSTOM0 = 0xE,\n+\tNPC_LT_LB_CUSTOM1 = 0xF,\n };\n \n enum npc_kpu_lc_ltype {\n@@ -213,6 +220,8 @@ enum npc_kpu_lc_ltype {\n \tNPC_LT_LC_MPLS,\n \tNPC_LT_LC_NSH,\n \tNPC_LT_LC_FCOE,\n+\tNPC_LT_LC_CUSTOM0 = 0xE,\n+\tNPC_LT_LC_CUSTOM1 = 0xF,\n };\n \n /* Don't modify Ltypes up to SCTP, otherwise it will\n@@ -224,6 +233,8 @@ enum npc_kpu_ld_ltype {\n \tNPC_LT_LD_ICMP,\n \tNPC_LT_LD_SCTP,\n \tNPC_LT_LD_ICMP6,\n+\tNPC_LT_LD_CUSTOM0,\n+\tNPC_LT_LD_CUSTOM1,\n \tNPC_LT_LD_IGMP = 8,\n \tNPC_LT_LD_AH,\n \tNPC_LT_LD_GRE,\n@@ -244,6 +255,8 @@ enum npc_kpu_le_ltype {\n \tNPC_LT_LE_TU_MPLS_IN_GRE,\n \tNPC_LT_LE_TU_NSH_IN_GRE,\n \tNPC_LT_LE_TU_MPLS_IN_UDP,\n+\tNPC_LT_LE_CUSTOM0 = 0xE,\n+\tNPC_LT_LE_CUSTOM1 = 0xF,\n };\n \n enum npc_kpu_lf_ltype {\n@@ -253,6 +266,8 @@ enum npc_kpu_lf_ltype {\n \tNPC_LT_LF_TU_NSH_IN_VXLANGPE,\n \tNPC_LT_LF_TU_MPLS_IN_NSH,\n \tNPC_LT_LF_TU_3RD_NSH,\n+\tNPC_LT_LF_CUSTOM0 = 0xE,\n+\tNPC_LT_LF_CUSTOM1 = 0xF,\n };\n \n enum npc_kpu_lg_ltype {\n@@ -260,6 +275,8 @@ enum npc_kpu_lg_ltype {\n \tNPC_LT_LG_TU_IP6,\n \tNPC_LT_LG_TU_ARP,\n \tNPC_LT_LG_TU_ETHER_IN_NSH,\n+\tNPC_LT_LG_CUSTOM0 = 0xE,\n+\tNPC_LT_LG_CUSTOM1 = 0xF,\n };\n \n /* Don't modify Ltypes up to SCTP, otherwise it will\n@@ -274,6 +291,8 @@ enum npc_kpu_lh_ltype {\n \tNPC_LT_LH_TU_IGMP = 8,\n \tNPC_LT_LH_TU_ESP,\n \tNPC_LT_LH_TU_AH,\n+\tNPC_LT_LH_CUSTOM0 = 0xE,\n+\tNPC_LT_LH_CUSTOM1 = 0xF,\n };\n \n /* Structures definitions */\ndiff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex f6d884c19..7e7667bf0 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -353,13 +353,26 @@ struct ready_msg_rsp {\n \tuint16_t __otx2_io rclk_freq; /* RCLK frequency */\n };\n \n+enum npc_pkind_type {\n+\tNPC_RX_CHLEN24B_PKIND = 57ULL,\n+\tNPC_RX_CPT_HDR_PKIND,\n+\tNPC_RX_CHLEN90B_PKIND,\n+\tNPC_TX_HIGIG_PKIND,\n+\tNPC_RX_HIGIG_PKIND,\n+\tNPC_RX_EDSA_PKIND,\n+\tNPC_TX_DEF_PKIND,\n+};\n+\n+#define OTX2_PRIV_FLAGS_CH_LEN_90B 254\n+#define OTX2_PRIV_FLAGS_CH_LEN_24B 255\n+\n /* Struct to set pkind */\n struct npc_set_pkind {\n \tstruct mbox_msghdr hdr;\n #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)\n #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)\n #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)\n-#define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)\n+#define OTX2_PRIV_FLAGS_FDSA BIT_ULL(3)\n #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)\n \tuint64_t __otx2_io mode;\n #define PKIND_TX\t\tBIT_ULL(0)\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 6cebbe677..9bfe95d6b 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -112,15 +112,18 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)\n \tif (dev->npc_flow.switch_header_type == 0)\n \t\treturn 0;\n \n-\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&\n-\t !otx2_dev_is_sdp(dev)) {\n-\t\totx2_err(\"chlen90b is not supported on non-SDP device\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \t/* Notify AF about higig2 config */\n \treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n \treq->mode = dev->npc_flow.switch_header_type;\n+\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {\n+\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n+\t\treq->pkind = NPC_RX_CHLEN90B_PKIND;\n+\t} else if (dev->npc_flow.switch_header_type ==\n+\t\t OTX2_PRIV_FLAGS_CH_LEN_24B) {\n+\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n+\t\treq->pkind = NPC_RX_CHLEN24B_PKIND;\n+\t}\n+\n \tif (enable == 0)\n \t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n \treq->dir = PKIND_RX;\n@@ -129,6 +132,10 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)\n \t\treturn rc;\n \treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n \treq->mode = dev->npc_flow.switch_header_type;\n+\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||\n+\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)\n+\t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n+\n \tif (enable == 0)\n \t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n \treq->dir = PKIND_TX;\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c\nindex d4a85bf55..71d3e9747 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c\n@@ -114,7 +114,11 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)\n \t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;\n \n \tif (strcmp(value, \"chlen90b\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_LEN_90B;\n+\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_90B;\n+\n+\tif (strcmp(value, \"chlen24b\") == 0)\n+\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;\n+\n \treturn 0;\n }\n \n@@ -198,7 +202,7 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,\n \t\t\t OTX2_MAX_SQB_COUNT \"=<8-512>\"\n \t\t\t OTX2_FLOW_PREALLOC_SIZE \"=<1-32>\"\n \t\t\t OTX2_FLOW_MAX_PRIORITY \"=<1-32>\"\n-\t\t\t OTX2_SWITCH_HEADER_TYPE \"=<higig2|dsa|chlen90b>\"\n+\t\t\t OTX2_SWITCH_HEADER_TYPE \"=<higig2|dsa|chlen90b|chlen24b>\"\n \t\t\t OTX2_RSS_TAG_AS_XOR \"=1\"\n \t\t\t OTX2_NPA_LOCK_MASK \"=<1-65535>\"\n \t\t\t OTX2_LOCK_RX_CTX \"=1\"\ndiff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c\nindex 3ba2366b8..7dbe5f69a 100644\n--- a/drivers/net/octeontx2/otx2_rss.c\n+++ b/drivers/net/octeontx2/otx2_rss.c\n@@ -234,7 +234,7 @@ otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t ethdev_rss,\n \tdev->rss_info.nix_rss = ethdev_rss;\n \n \tif (ethdev_rss & ETH_RSS_L2_PAYLOAD &&\n-\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B) {\n+\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {\n \t\tflowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;\n \t}\n \n", "prefixes": [] }