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GET /api/patches/85571/?format=api
{ "id": 85571, "url": "https://patches.dpdk.org/api/patches/85571/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/258c7004de1206e4d3bd4c4bca9f35ed318ebceb.1608504560.git.rahul.lakkireddy@chelsio.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<258c7004de1206e4d3bd4c4bca9f35ed318ebceb.1608504560.git.rahul.lakkireddy@chelsio.com>", "list_archive_url": "https://inbox.dpdk.org/dev/258c7004de1206e4d3bd4c4bca9f35ed318ebceb.1608504560.git.rahul.lakkireddy@chelsio.com", "date": "2020-12-20T22:47:42", "name": "[3/3] net/cxgbe: implement ethdev ops to configure link FEC", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a5dc9dbcebc8a0dda6f822d245efd00fa15dff2e", "submitter": { "id": 241, "url": "https://patches.dpdk.org/api/people/241/?format=api", "name": "Rahul Lakkireddy", "email": "rahul.lakkireddy@chelsio.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/258c7004de1206e4d3bd4c4bca9f35ed318ebceb.1608504560.git.rahul.lakkireddy@chelsio.com/mbox/", "series": [ { "id": 14394, "url": "https://patches.dpdk.org/api/series/14394/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14394", "date": "2020-12-20T22:47:39", "name": "net/cxgbe: rework link config and add FEC support", "version": 1, "mbox": "https://patches.dpdk.org/series/14394/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85571/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85571/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8CE17A09FD;\n\tMon, 21 Dec 2020 00:05:00 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7F58BCC33;\n\tMon, 21 Dec 2020 00:04:14 +0100 (CET)", "from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8])\n by dpdk.org (Postfix) with ESMTP id 570C9CC33\n for <dev@dpdk.org>; Mon, 21 Dec 2020 00:04:13 +0100 (CET)", "from localhost (scalar.blr.asicdesigners.com [10.193.185.94])\n by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id 0BKN49EO011892;\n Sun, 20 Dec 2020 15:04:09 -0800" ], "From": "Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>", "To": "dev@dpdk.org", "Cc": "kaara.satwik@chelsio.com", "Date": "Mon, 21 Dec 2020 04:17:42 +0530", "Message-Id": "\n <258c7004de1206e4d3bd4c4bca9f35ed318ebceb.1608504560.git.rahul.lakkireddy@chelsio.com>", "X-Mailer": "git-send-email 2.5.3", "In-Reply-To": [ "<cover.1608504560.git.rahul.lakkireddy@chelsio.com>", "<cover.1608504560.git.rahul.lakkireddy@chelsio.com>" ], "References": [ "<cover.1608504560.git.rahul.lakkireddy@chelsio.com>", "<cover.1608504560.git.rahul.lakkireddy@chelsio.com>" ], "Subject": "[dpdk-dev] [PATCH 3/3] net/cxgbe: implement ethdev ops to configure\n\tlink FEC", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Karra Satwik <kaara.satwik@chelsio.com>\n\nAdd ethdev ops to query and configure link FEC.\n\nSigned-off-by: Karra Satwik <kaara.satwik@chelsio.com>\nSigned-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>\n---\n drivers/net/cxgbe/base/common.h | 2 +\n drivers/net/cxgbe/base/t4_hw.c | 79 ++++++++++++++\n drivers/net/cxgbe/base/t4fw_interface.h | 6 ++\n drivers/net/cxgbe/cxgbe_ethdev.c | 133 ++++++++++++++++++++++++\n 4 files changed, 220 insertions(+)", "diff": "diff --git a/drivers/net/cxgbe/base/common.h b/drivers/net/cxgbe/base/common.h\nindex a244df7a0..202a2f4ba 100644\n--- a/drivers/net/cxgbe/base/common.h\n+++ b/drivers/net/cxgbe/base/common.h\n@@ -331,6 +331,8 @@ static inline int t4_link_l1cfg_ns(struct port_info *pi, u32 caps)\n int t4_set_link_speed(struct port_info *pi, u32 speed, u32 *new_caps);\n int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,\n \t\t u8 pause_rx, u32 *new_caps);\n+int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,\n+\t\t u8 fec_none, u32 *new_caps);\n unsigned int t4_fwcap_to_speed(u32 caps);\n void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,\n \t\t const unsigned short *alpha, const unsigned short *beta);\ndiff --git a/drivers/net/cxgbe/base/t4_hw.c b/drivers/net/cxgbe/base/t4_hw.c\nindex 3c0990cb3..e87823f8f 100644\n--- a/drivers/net/cxgbe/base/t4_hw.c\n+++ b/drivers/net/cxgbe/base/t4_hw.c\n@@ -4475,6 +4475,76 @@ int t4_set_link_pause(struct port_info *pi, u8 autoneg, u8 pause_tx,\n \treturn 0;\n }\n \n+int t4_set_link_fec(struct port_info *pi, u8 fec_rs, u8 fec_baser,\n+\t\t u8 fec_none, u32 *new_caps)\n+{\n+\tstruct link_config *lc = &pi->link_cfg;\n+\tu32 max_speed, caps = *new_caps;\n+\n+\tif (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))\n+\t\treturn -EOPNOTSUPP;\n+\n+\t/* Link might be down. In that case consider the max\n+\t * speed advertised\n+\t */\n+\tmax_speed = t4_fwcap_to_speed(lc->link_caps);\n+\tif (!max_speed)\n+\t\tmax_speed = t4_fwcap_to_speed(lc->acaps);\n+\n+\tcaps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);\n+\tif (fec_rs) {\n+\t\tswitch (max_speed) {\n+\t\tcase 100000:\n+\t\tcase 25000:\n+\t\t\tcaps |= FW_PORT_CAP32_FEC_RS;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\t}\n+\n+\tif (fec_baser) {\n+\t\tswitch (max_speed) {\n+\t\tcase 50000:\n+\t\tcase 25000:\n+\t\t\tcaps |= FW_PORT_CAP32_FEC_BASER_RS;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\t}\n+\n+\tif (fec_none)\n+\t\tcaps |= FW_PORT_CAP32_FEC_NO_FEC;\n+\n+\tif (!(caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) {\n+\t\t/* No explicit encoding is requested.\n+\t\t * So, default back to AUTO.\n+\t\t */\n+\t\tswitch (max_speed) {\n+\t\tcase 100000:\n+\t\t\tcaps |= FW_PORT_CAP32_FEC_RS |\n+\t\t\t\tFW_PORT_CAP32_FEC_NO_FEC;\n+\t\t\tbreak;\n+\t\tcase 50000:\n+\t\t\tcaps |= FW_PORT_CAP32_FEC_BASER_RS |\n+\t\t\t\tFW_PORT_CAP32_FEC_NO_FEC;\n+\t\t\tbreak;\n+\t\tcase 25000:\n+\t\t\tcaps |= FW_PORT_CAP32_FEC_RS |\n+\t\t\t\tFW_PORT_CAP32_FEC_BASER_RS |\n+\t\t\t\tFW_PORT_CAP32_FEC_NO_FEC;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn -EOPNOTSUPP;\n+\t\t}\n+\t}\n+\n+\t*new_caps = caps;\n+\n+\treturn 0;\n+}\n+\n /**\n * t4_handle_get_port_info - process a FW reply message\n * @pi: the port info\n@@ -4652,6 +4722,15 @@ void t4_init_link_config(struct port_info *pi, u32 pcaps, u32 acaps,\n \tif (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE)\n \t\tlc->admin_caps &= ~FW_PORT_CAP32_FORCE_PAUSE;\n \n+\t/* Reset FEC caps to default values */\n+\tif (lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) {\n+\t\tlc->admin_caps &= ~V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);\n+\t\tt4_set_link_fec(pi, 0, 0, 0, &lc->admin_caps);\n+\t}\n+\n+\tif (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)\n+\t\tlc->admin_caps &= ~FW_PORT_CAP32_FORCE_FEC;\n+\n \t/* Reset MDI to AUTO */\n \tif (lc->pcaps & FW_PORT_CAP32_MDIAUTO) {\n \t\tlc->admin_caps &= ~V_FW_PORT_CAP32_MDI(M_FW_PORT_CAP32_MDI);\ndiff --git a/drivers/net/cxgbe/base/t4fw_interface.h b/drivers/net/cxgbe/base/t4fw_interface.h\nindex cfd03cf34..240e0ee49 100644\n--- a/drivers/net/cxgbe/base/t4fw_interface.h\n+++ b/drivers/net/cxgbe/base/t4fw_interface.h\n@@ -1615,7 +1615,9 @@ struct fw_vi_stats_cmd {\n #define FW_PORT_CAP32_MDIAUTO 0x00400000UL\n #define FW_PORT_CAP32_FEC_RS 0x00800000UL\n #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL\n+#define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL\n #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL\n+#define FW_PORT_CAP32_FORCE_FEC 0x20000000UL\n \n #define S_FW_PORT_CAP32_SPEED 0\n #define M_FW_PORT_CAP32_SPEED 0xfff\n@@ -1641,6 +1643,10 @@ enum fw_port_mdi32 {\n #define G_FW_PORT_CAP32_MDI(x) \\\n \t(((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)\n \n+#define S_FW_PORT_CAP32_FEC 23\n+#define M_FW_PORT_CAP32_FEC 0x1f\n+#define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)\n+\n enum fw_port_action {\n \tFW_PORT_ACTION_L1_CFG32 = 0x0009,\n \tFW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,\ndiff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c\nindex c58e63918..6f481551d 100644\n--- a/drivers/net/cxgbe/cxgbe_ethdev.c\n+++ b/drivers/net/cxgbe/cxgbe_ethdev.c\n@@ -1193,6 +1193,136 @@ int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)\n \treturn 0;\n }\n \n+static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc,\n+\t\t\t\t\t struct rte_eth_fec_capa *capa_arr)\n+{\n+\tint num = 0;\n+\n+\tif (lc->pcaps & FW_PORT_CAP32_SPEED_100G) {\n+\t\tif (capa_arr) {\n+\t\t\tcapa_arr[num].speed = ETH_SPEED_NUM_100G;\n+\t\t\tcapa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |\n+\t\t\t\t\t RTE_ETH_FEC_MODE_CAPA_MASK(RS);\n+\t\t}\n+\t\tnum++;\n+\t}\n+\n+\tif (lc->pcaps & FW_PORT_CAP32_SPEED_50G) {\n+\t\tif (capa_arr) {\n+\t\t\tcapa_arr[num].speed = ETH_SPEED_NUM_50G;\n+\t\t\tcapa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |\n+\t\t\t\t\t RTE_ETH_FEC_MODE_CAPA_MASK(BASER);\n+\t\t}\n+\t\tnum++;\n+\t}\n+\n+\tif (lc->pcaps & FW_PORT_CAP32_SPEED_25G) {\n+\t\tif (capa_arr) {\n+\t\t\tcapa_arr[num].speed = ETH_SPEED_NUM_25G;\n+\t\t\tcapa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |\n+\t\t\t\t\t RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |\n+\t\t\t\t\t RTE_ETH_FEC_MODE_CAPA_MASK(RS);\n+\t\t}\n+\t\tnum++;\n+\t}\n+\n+\treturn num;\n+}\n+\n+static int cxgbe_fec_get_capability(struct rte_eth_dev *dev,\n+\t\t\t\t struct rte_eth_fec_capa *speed_fec_capa,\n+\t\t\t\t unsigned int num)\n+{\n+\tstruct port_info *pi = dev->data->dev_private;\n+\tstruct link_config *lc = &pi->link_cfg;\n+\tu8 num_entries;\n+\n+\tif (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tnum_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL);\n+\tif (!speed_fec_capa || num < num_entries)\n+\t\treturn num_entries;\n+\n+\treturn cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa);\n+}\n+\n+static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa)\n+{\n+\tstruct port_info *pi = dev->data->dev_private;\n+\tstruct link_config *lc = &pi->link_cfg;\n+\tu32 fec_caps = 0, caps = lc->link_caps;\n+\n+\tif (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (caps & FW_PORT_CAP32_FEC_NO_FEC) {\n+\t\tfec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC);\n+\t\tgoto out;\n+\t}\n+\n+\tif (caps & FW_PORT_CAP32_FEC_BASER_RS) {\n+\t\tfec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER);\n+\t\tgoto out;\n+\t}\n+\n+\tif (caps & FW_PORT_CAP32_FEC_RS) {\n+\t\tfec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS);\n+\t\tgoto out;\n+\t}\n+\n+\tfec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(AUTO);\n+\n+out:\n+\t*fec_capa = fec_caps;\n+\treturn 0;\n+}\n+\n+static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa)\n+{\n+\tstruct port_info *pi = dev->data->dev_private;\n+\tu8 fec_rs = 0, fec_baser = 0, fec_none = 0;\n+\tstruct link_config *lc = &pi->link_cfg;\n+\tu32 new_caps = lc->admin_caps;\n+\tint ret;\n+\n+\tif (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)))\n+\t\treturn -EOPNOTSUPP;\n+\n+\tif (!fec_capa)\n+\t\treturn -EINVAL;\n+\n+\tif (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO))\n+\t\tgoto set_fec;\n+\n+\tif (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC))\n+\t\tfec_none = 1;\n+\n+\tif (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER))\n+\t\tfec_baser = 1;\n+\n+\tif (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS))\n+\t\tfec_rs = 1;\n+\n+set_fec:\n+\tret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps);\n+\tif (ret != 0)\n+\t\treturn ret;\n+\n+\tif (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)\n+\t\tnew_caps |= FW_PORT_CAP32_FORCE_FEC;\n+\telse\n+\t\tnew_caps &= ~FW_PORT_CAP32_FORCE_FEC;\n+\n+\tif (new_caps != lc->admin_caps) {\n+\t\tret = t4_link_l1cfg(pi, new_caps);\n+\t\tif (ret == 0)\n+\t\t\tlc->admin_caps = new_caps;\n+\t}\n+\n+\treturn ret;\n+}\n+\n static const struct eth_dev_ops cxgbe_eth_dev_ops = {\n \t.dev_start\t\t= cxgbe_dev_start,\n \t.dev_stop\t\t= cxgbe_dev_stop,\n@@ -1230,6 +1360,9 @@ static const struct eth_dev_ops cxgbe_eth_dev_ops = {\n \t.mac_addr_set\t\t= cxgbe_mac_addr_set,\n \t.reta_update = cxgbe_dev_rss_reta_update,\n \t.reta_query = cxgbe_dev_rss_reta_query,\n+\t.fec_get_capability = cxgbe_fec_get_capability,\n+\t.fec_get = cxgbe_fec_get,\n+\t.fec_set = cxgbe_fec_set,\n };\n \n /*\n", "prefixes": [ "3/3" ] }