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GET /api/patches/85516/?format=api
{ "id": 85516, "url": "https://patches.dpdk.org/api/patches/85516/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201220052430.99990-7-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201220052430.99990-7-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201220052430.99990-7-ajit.khaparde@broadcom.com", "date": "2020-12-20T05:24:30", "name": "[6/6] net/bnxt: add Rx logic for 58818 chips", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1963d638fb847d911cd498a0a4d768edc351b8c3", "submitter": { "id": 2064, "url": "https://patches.dpdk.org/api/people/2064/?format=api", "name": "Ajit Khaparde", "email": "ajitkhaparde@gmail.com" }, "delegate": { "id": 1766, "url": "https://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201220052430.99990-7-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 14388, "url": "https://patches.dpdk.org/api/series/14388/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14388", "date": "2020-12-20T05:24:24", "name": "net/bnxt: add support for Stingray2", "version": 1, "mbox": "https://patches.dpdk.org/series/14388/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85516/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/85516/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AF732A052A;\n\tSun, 20 Dec 2020 06:26:31 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 399C1CC27;\n\tSun, 20 Dec 2020 06:24:50 +0100 (CET)", "from mail-pf1-f172.google.com (mail-pf1-f172.google.com\n [209.85.210.172]) by dpdk.org (Postfix) with ESMTP id BB9B9CB85\n for <dev@dpdk.org>; Sun, 20 Dec 2020 06:24:43 +0100 (CET)", "by mail-pf1-f172.google.com with SMTP id c79so4471298pfc.2\n for <dev@dpdk.org>; Sat, 19 Dec 2020 21:24:43 -0800 (PST)", "from localhost.localdomain ([192.19.223.252])\n by smtp.gmail.com with ESMTPSA id b11sm12936544pfr.38.2020.12.19.21.24.41\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Sat, 19 Dec 2020 21:24:42 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=ImehS+rNNbsQQ+Cd4vIqvI7YrBcETW0F9myuMUBwSTU=;\n b=abGPDfXcIOTf70IfapLSRBlQp6euVHkd3OVtt2AfnvVK8Wk1Ea+FxUcWZYY0VMKYWQ\n NAPFAM2TffQj6Gpiicw1IFAyRcjf4FdxHA1qMZnrGuVX181Pg28JJRvmAcExNh8XXp7F\n xz7kbGSjeP4Zj89Kghp/YFcgtpvkvTkbSlkPXnAHF6XsF9MrTjUaIU+cdh36sRrL7tzs\n kyB7y9KvK9wRt0SacsLeuph1zyCq5q4GShmsWufyzDfIqtyi8ULWXboI/WpLb8GixT84\n +o11bDKmD52GgobRfQDE+VaQ8gGhQBTBSeNRxq346QwerSAA+ibW+YJD0GRgHBn6OkKc\n f6jg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=ImehS+rNNbsQQ+Cd4vIqvI7YrBcETW0F9myuMUBwSTU=;\n b=cjUE/oAIkZdh9CydAM7QvlaL9BCUOB1oDXTRTUKQdVX7WmxfBlFlcoEycFkV0n7VSd\n txFmVkIWdaxfKRirRRJmSvlNigNG/TxBiMiDuzQWqUDCGflpTtnDRxCNbl3eVvTxamS/\n TtF/IHQA/qEn/zdBww8DlnyXI8Ht9IvSZlVKBETdpZQ9gnX2iEtOy0evLxCpbIRyVqPZ\n 0DQLYBof3o0jFfrdwwJULYtHu6z0ZxwDsbMySD9h4hO2h8xeMA5CvtzKyVzVq8Oac+F+\n 4bKaiSWu51iS2cq4CWQHBfF+Pq0ykMC1F9q0lzH8QUufiYPO6fBa7w680oXFwfONT9j/\n jjqQ==", "X-Gm-Message-State": "AOAM531ox5k/X5rOYr/a3LNQCHhNmbVPREyMDdF6Q9aDVzDzXi735LoI\n VaMciC9eaRaS95quDCEiDAstQHaC06cP0Q==", "X-Google-Smtp-Source": "\n ABdhPJwTeBuOFpEVSB7YS22iEGxgx//lNdoFzpLPzdzaR3fgHla11SDnSikdc26laZvBaF3WmY3Vvw==", "X-Received": "by 2002:a65:4c4b:: with SMTP id l11mr6507212pgr.177.1608441882632;\n Sat, 19 Dec 2020 21:24:42 -0800 (PST)", "From": "Ajit Khaparde <ajitkhaparde@gmail.com>", "X-Google-Original-From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Kalesh AP <kalesh-anakkur.purayil@broadcom.com>", "Date": "Sat, 19 Dec 2020 21:24:30 -0800", "Message-Id": "<20201220052430.99990-7-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20201220052430.99990-1-ajit.khaparde@broadcom.com>", "References": "<20201220052430.99990-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 6/6] net/bnxt: add Rx logic for 58818 chips", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\n\n1. On the new 58818 chips, the RX completion is largely the same except\n for the new completion opcode and the stripped VLAN format and checksum\n status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2() and\n bnxt_rx_vlan_v2() to support the new RX completion logic.\n2. Disable vector mode RX/TX for 58818 chips for now.\n3. The cfa_code format on 58818 chips is different than legacy chips.\n So skip cfa_code parsing logic on 58818 chips for now.\n\nSigned-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt_ethdev.c | 15 ++-\n drivers/net/bnxt/bnxt_rxr.c | 24 +++--\n drivers/net/bnxt/bnxt_rxr.h | 191 +++++++++++++++++++++++++++++++++\n 3 files changed, 221 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex e11751cc1..ef6b611be 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -1159,6 +1159,12 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)\n {\n \tstruct bnxt *bp = eth_dev->data->dev_private;\n \n+\t/* Disable vector mode RX for Stingray2 for now */\n+\tif (BNXT_CHIP_SR2(bp)) {\n+\t\tbp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;\n+\t\treturn bnxt_recv_pkts;\n+\t}\n+\n #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)\n #ifndef RTE_LIBRTE_IEEE1588\n \t/*\n@@ -1199,12 +1205,17 @@ bnxt_receive_function(struct rte_eth_dev *eth_dev)\n }\n \n static eth_tx_burst_t\n-bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)\n+bnxt_transmit_function(struct rte_eth_dev *eth_dev)\n {\n+\tstruct bnxt *bp = eth_dev->data->dev_private;\n+\n+\t/* Disable vector mode TX for Stingray2 for now */\n+\tif (BNXT_CHIP_SR2(bp))\n+\t\treturn bnxt_xmit_pkts;\n+\n #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)\n #ifndef RTE_LIBRTE_IEEE1588\n \tuint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;\n-\tstruct bnxt *bp = eth_dev->data->dev_private;\n \n \t/*\n \t * Vector mode transmit can be enabled only if not using scatter rx\ndiff --git a/drivers/net/bnxt/bnxt_rxr.c b/drivers/net/bnxt/bnxt_rxr.c\nindex 96e995029..74efdd0d2 100644\n--- a/drivers/net/bnxt/bnxt_rxr.c\n+++ b/drivers/net/bnxt/bnxt_rxr.c\n@@ -775,7 +775,8 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \t\t\treturn -EBUSY;\n \t\t*rx_pkt = mbuf;\n \t\tgoto next_rx;\n-\t} else if (cmp_type != 0x11) {\n+\t} else if ((cmp_type != CMPL_BASE_TYPE_RX_L2) &&\n+\t\t (cmp_type != CMPL_BASE_TYPE_RX_L2_V2)) {\n \t\trc = -EINVAL;\n \t\tgoto next_rx;\n \t}\n@@ -799,8 +800,6 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \tmbuf->data_len = mbuf->pkt_len;\n \tmbuf->port = rxq->port_id;\n \n-\tbnxt_set_ol_flags(rxcmp, rxcmp1, mbuf);\n-\n #ifdef RTE_LIBRTE_IEEE1588\n \tif (unlikely((rte_le_to_cpu_16(rxcmp->flags_type) &\n \t\t RX_PKT_CMPL_FLAGS_MASK) ==\n@@ -810,17 +809,28 @@ static int bnxt_rx_pkt(struct rte_mbuf **rx_pkt,\n \t}\n #endif\n \n+\tif (cmp_type == CMPL_BASE_TYPE_RX_L2_V2) {\n+\t\tbnxt_parse_csum_v2(mbuf, rxcmp1);\n+\t\tbnxt_parse_pkt_type_v2(mbuf, rxcmp, rxcmp1);\n+\t\tbnxt_rx_vlan_v2(mbuf, rxcmp, rxcmp1);\n+\t\t/* TODO Add support for cfa_code parsing */\n+\t\tgoto reuse_rx_mbuf;\n+\t}\n+\n+\tbnxt_set_ol_flags(rxcmp, rxcmp1, mbuf);\n+\n+\tmbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);\n+\n \tif (BNXT_TRUFLOW_EN(bp))\n \t\tmark_id = bnxt_ulp_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf,\n \t\t\t\t\t\t &vfr_flag);\n \telse\n \t\tbnxt_set_mark_in_mbuf(rxq->bp, rxcmp1, mbuf);\n \n+reuse_rx_mbuf:\n \tif (agg_buf)\n \t\tbnxt_rx_pages(rxq, mbuf, &tmp_raw_cons, agg_buf, NULL);\n \n-\tmbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);\n-\n #ifdef BNXT_DEBUG\n \tif (rxcmp1->errors_v2 & RX_CMP_L2_ERRORS) {\n \t\t/* Re-install the mbuf back to the rx ring */\n@@ -933,8 +943,8 @@ uint16_t bnxt_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t\tcpr->cp_ring_struct->ring_mask,\n \t\t\t\t\tcpr->valid);\n \n-\t\t/* TODO: Avoid magic numbers... */\n-\t\tif ((CMP_TYPE(rxcmp) & 0x30) == 0x10) {\n+\t\tif ((CMP_TYPE(rxcmp) >= CMPL_BASE_TYPE_RX_TPA_START_V2) &&\n+\t\t (CMP_TYPE(rxcmp) <= RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG)) {\n \t\t\trc = bnxt_rx_pkt(&rx_pkts[nb_rx_pkts], rxq, &raw_cons);\n \t\t\tif (!rc)\n \t\t\t\tnb_rx_pkts++;\ndiff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h\nindex 7ca7e39e5..601f50205 100644\n--- a/drivers/net/bnxt/bnxt_rxr.h\n+++ b/drivers/net/bnxt/bnxt_rxr.h\n@@ -131,5 +131,196 @@ extern uint32_t bnxt_ol_flags_table[BNXT_OL_FLAGS_TBL_DIM];\n #define BNXT_OL_FLAGS_ERR_TBL_DIM 16\n extern uint32_t bnxt_ol_flags_err_table[BNXT_OL_FLAGS_ERR_TBL_DIM];\n \n+/* Stingray2 specific code for RX completion parsing */\n+#define RX_CMP_VLAN_VALID(rxcmp) \\\n+\t(((struct rx_pkt_v2_cmpl *)rxcmp)->metadata1_payload_offset &\t\\\n+\t RX_PKT_V2_CMPL_METADATA1_VALID)\n+\n+#define RX_CMP_METADATA0_VID(rxcmp1)\t\t\t\t\\\n+\t((((struct rx_pkt_v2_cmpl_hi *)rxcmp1)->metadata0) &\t\\\n+\t (RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK |\t\t\\\n+\t RX_PKT_V2_CMPL_HI_METADATA0_DE |\t\t\t\\\n+\t RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK))\n+\n+static inline void bnxt_rx_vlan_v2(struct rte_mbuf *mbuf,\n+\t\t\t\t struct rx_pkt_cmpl *rxcmp,\n+\t\t\t\t struct rx_pkt_cmpl_hi *rxcmp1)\n+{\n+\tif (RX_CMP_VLAN_VALID(rxcmp)) {\n+\t\tmbuf->vlan_tci = RX_CMP_METADATA0_VID(rxcmp1);\n+\t\tmbuf->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;\n+\t}\n+}\n+\n+#define RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK\t(0x1 << 3)\n+#define RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK\t(0x7 << 10)\n+#define RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK\t(0x1 << 13)\n #define RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK\t(0x1 << 14)\n+\n+#define RX_CMP_V2_CS_OK_HDR_CNT(flags)\t\t\t\t\\\n+\t(((flags) & RX_CMP_FLAGS2_CS_OK_HDR_CNT_MASK) >>\t\\\n+\t RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT)\n+\n+#define RX_CMP_V2_CS_ALL_OK_MODE(flags)\t\t\t\t\\\n+\t(((flags) & RX_CMP_FLAGS2_CS_ALL_OK_MODE_MASK))\n+\n+#define RX_CMP_FLAGS2_L3_CS_OK_MASK\t\t(0x7 << 10)\n+#define RX_CMP_FLAGS2_L4_CS_OK_MASK\t\t(0x38 << 10)\n+#define RX_CMP_FLAGS2_L3_CS_OK_SFT\t\t10\n+#define RX_CMP_FLAGS2_L4_CS_OK_SFT\t\t13\n+\n+#define RX_CMP_V2_L4_CS_OK(flags2)\t\t\t\\\n+\t(((flags2) & RX_CMP_FLAGS2_L4_CS_OK_MASK) >>\t\\\n+\t RX_CMP_FLAGS2_L4_CS_OK_SFT)\n+\n+#define RX_CMP_V2_L3_CS_OK(flags2)\t\t\t\\\n+\t(((flags2) & RX_CMP_FLAGS2_L3_CS_OK_MASK) >>\t\\\n+\t RX_CMP_FLAGS2_L3_CS_OK_SFT)\n+\n+#define RX_CMP_V2_L4_CS_ERR(err)\t\t\t\t\\\n+\t(((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) ==\t\\\n+\t RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR)\n+\n+#define RX_CMP_V2_L3_CS_ERR(err)\t\t\t\t\\\n+\t(((err) & RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK) ==\t\\\n+\t RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR)\n+\n+#define RX_CMP_V2_T_IP_CS_ERR(err)\t\t\t\t\\\n+\t(((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) ==\t\\\n+\t RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR)\n+\n+#define RX_CMP_V2_T_L4_CS_ERR(err)\t\t\t\t\\\n+\t(((err) & RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK) ==\t\\\n+\t RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR)\n+\n+#define RX_CMP_V2_OT_L4_CS_ERR(err)\t\t\t\t\t\\\n+\t(((err) & RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK) ==\t\\\n+\t RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR)\n+\n+static inline void bnxt_parse_csum_v2(struct rte_mbuf *mbuf,\n+\t\t\t\t struct rx_pkt_cmpl_hi *rxcmp1)\n+{\n+\tstruct rx_pkt_v2_cmpl_hi *v2_cmp =\n+\t\t(struct rx_pkt_v2_cmpl_hi *)(rxcmp1);\n+\tuint16_t error_v2 = rte_le_to_cpu_16(v2_cmp->errors_v2);\n+\tuint32_t flags2 = rte_le_to_cpu_32(v2_cmp->flags2);\n+\tuint32_t hdr_cnt = 0, t_pkt = 0;\n+\n+\tif (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {\n+\t\thdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);\n+\t\tif (hdr_cnt > 1)\n+\t\t\tt_pkt = 1;\n+\n+\t\tif (unlikely(RX_CMP_V2_L4_CS_ERR(error_v2)))\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n+\t\telse if (flags2 & RX_CMP_FLAGS2_L4_CSUM_ALL_OK_MASK)\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;\n+\t\telse\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;\n+\n+\t\tif (unlikely(RX_CMP_V2_L3_CS_ERR(error_v2)))\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\t\telse if (flags2 & RX_CMP_FLAGS2_IP_CSUM_ALL_OK_MASK)\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;\n+\t\telse\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;\n+\t} else {\n+\t\thdr_cnt = RX_CMP_V2_L4_CS_OK(flags2);\n+\t\tif (hdr_cnt > 1)\n+\t\t\tt_pkt = 1;\n+\n+\t\tif (RX_CMP_V2_L4_CS_OK(flags2))\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD;\n+\t\telse if (RX_CMP_V2_L4_CS_ERR(error_v2))\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n+\t\telse\n+\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;\n+\n+\t\tif (RX_CMP_V2_L3_CS_OK(flags2))\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD;\n+\t\telse if (RX_CMP_V2_L3_CS_ERR(error_v2))\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\t\telse\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_UNKNOWN;\n+\t}\n+\n+\tif (t_pkt) {\n+\t\tif (unlikely(RX_CMP_V2_OT_L4_CS_ERR(error_v2) ||\n+\t\t\t\t\tRX_CMP_V2_T_L4_CS_ERR(error_v2)))\n+\t\t\tmbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_BAD;\n+\t\telse\n+\t\t\tmbuf->ol_flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;\n+\n+\t\tif (unlikely(RX_CMP_V2_T_IP_CS_ERR(error_v2)))\n+\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\t}\n+}\n+\n+static inline void\n+bnxt_parse_pkt_type_v2(struct rte_mbuf *mbuf,\n+\t\t struct rx_pkt_cmpl *rxcmp,\n+\t\t struct rx_pkt_cmpl_hi *rxcmp1)\n+{\n+\tstruct rx_pkt_v2_cmpl *v2_cmp =\n+\t\t(struct rx_pkt_v2_cmpl *)(rxcmp);\n+\tstruct rx_pkt_v2_cmpl_hi *v2_cmp1 =\n+\t\t(struct rx_pkt_v2_cmpl_hi *)(rxcmp1);\n+\tuint16_t flags_type = v2_cmp->flags_type &\n+\t\trte_cpu_to_le_32(RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK);\n+\tuint32_t flags2 = rte_le_to_cpu_32(v2_cmp1->flags2);\n+\tuint32_t l3, pkt_type = 0, vlan = 0;\n+\tuint32_t ip6 = 0, t_pkt = 0;\n+\tuint32_t hdr_cnt, csum_count;\n+\n+\tif (RX_CMP_V2_CS_ALL_OK_MODE(flags2)) {\n+\t\thdr_cnt = RX_CMP_V2_CS_OK_HDR_CNT(flags2);\n+\t\tif (hdr_cnt > 1)\n+\t\t\tt_pkt = 1;\n+\t} else {\n+\t\tcsum_count = RX_CMP_V2_L4_CS_OK(flags2);\n+\t\tif (csum_count > 1)\n+\t\t\tt_pkt = 1;\n+\t}\n+\n+\tvlan = !!RX_CMP_VLAN_VALID(rxcmp);\n+\tpkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;\n+\n+\tip6 = !!(flags2 & RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE);\n+\n+\tif (!t_pkt && !ip6)\n+\t\tl3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;\n+\telse if (!t_pkt && ip6)\n+\t\tl3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;\n+\telse if (t_pkt && !ip6)\n+\t\tl3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;\n+\telse\n+\t\tl3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;\n+\n+\tswitch (flags_type) {\n+\tcase RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP):\n+\t\tif (!t_pkt)\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_L4_ICMP;\n+\t\telse\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;\n+\t\tbreak;\n+\tcase RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP):\n+\t\tif (!t_pkt)\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_L4_TCP;\n+\t\telse\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;\n+\t\tbreak;\n+\tcase RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP):\n+\t\tif (!t_pkt)\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_L4_UDP;\n+\t\telse\n+\t\t\tpkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;\n+\t\tbreak;\n+\tcase RTE_LE32(RX_PKT_V2_CMPL_FLAGS_ITYPE_IP):\n+\t\tpkt_type |= l3;\n+\t\tbreak;\n+\t}\n+\n+\tmbuf->packet_type = pkt_type;\n+}\n+\n #endif /* _BNXT_RXR_H_ */\n", "prefixes": [ "6/6" ] }