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GET /api/patches/85250/?format=api
{ "id": 85250, "url": "https://patches.dpdk.org/api/patches/85250/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201216142511.13660-5-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201216142511.13660-5-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201216142511.13660-5-shirik@nvidia.com", "date": "2020-12-16T14:25:09", "name": "[RFC,4/6] net/mlx5: add GTP PSC flow validation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "72f08928fc4c16de5634f427709cbe09f0b944a5", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201216142511.13660-5-shirik@nvidia.com/mbox/", "series": [ { "id": 14332, "url": "https://patches.dpdk.org/api/series/14332/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=14332", "date": "2020-12-16T14:25:05", "name": "add GTP PSC extension header support", "version": 1, "mbox": "https://patches.dpdk.org/series/14332/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/85250/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/85250/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3BF04A09EF;\n\tWed, 16 Dec 2020 15:27:21 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F293DCA06;\n\tWed, 16 Dec 2020 15:25:37 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 475EEC9E4\n for <dev@dpdk.org>; Wed, 16 Dec 2020 15:25:32 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n shirik@nvidia.com) with SMTP; 16 Dec 2020 16:25:27 +0200", "from nvidia.com (c-236-2-60-065.mtl.labs.mlnx [10.236.2.65])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 0BGEPF6f015188;\n Wed, 16 Dec 2020 16:25:27 +0200" ], "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "dev@dpdk.org", "Cc": "viacheslavo@nvidia.com, adrien.mazarguil@6wind.com, rasland@nvidia.com", "Date": "Wed, 16 Dec 2020 16:25:09 +0200", "Message-Id": "<20201216142511.13660-5-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20201216142511.13660-1-shirik@nvidia.com>", "References": "<1599118768-13265-1-git-send-email-shirik@nvidia.com>\n <20201216142511.13660-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [RFC 4/6] net/mlx5: add GTP PSC flow validation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In this patch we add validation routine for\nGTP PSC extension header.\n\nThe GTP PSC extension header must follow the\nGTP item.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 5 +++\n drivers/net/mlx5/mlx5_flow_dv.c | 70 +++++++++++++++++++++++++++++++++\n 2 files changed, 75 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex d85dd19929..fd6b24c32d 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -138,6 +138,9 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)\n #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)\n \n+/* Pattern tunnel Layer bits (continued). */\n+#define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -348,6 +351,8 @@ enum mlx5_feature_name {\n \n #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_ether_hdr) + \\\n \t\t\t\t\t sizeof(struct rte_ipv4_hdr))\n+/* GTP extension header flag. */\n+#define MLX5_GTP_EXT_HEADER_FLAG 4\n \n /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */\n #define MLX5_IPV4_FRAG_OFFSET_MASK \\\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex c31737652c..4f7a756214 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -1759,6 +1759,66 @@ flow_dv_validate_item_gtp(struct rte_eth_dev *dev,\n \t\t\t\t\t MLX5_ITEM_RANGE_NOT_ACCEPTED, error);\n }\n \n+/**\n+ * Validate GTP PSC item.\n+ *\n+ * @param[in] item\n+ * Item specification.\n+ * @param[in] last_item\n+ * Previous validated item in the pattern items.\n+ * @param[in] gtp_item\n+ * Previous GTP item specification.\n+ * @param[in] attr\n+ * Pointer to flow attributes.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,\n+\t\t\t uint64_t last_item,\n+\t\t\t const struct rte_flow_item *gtp_item,\n+\t\t\t const struct rte_flow_attr *attr,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tconst struct rte_flow_item_gtp *gtp_spec;\n+\tconst struct rte_flow_item_gtp *gtp_mask;\n+\tconst struct rte_flow_item_gtp_psc *mask;\n+\tconst struct rte_flow_item_gtp_psc nic_mask = {\n+\t\t.pdu_type = 0xFF,\n+\t\t.qfi = 0xFF,\n+\t};\n+\n+\tif (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t \"GTP PSC item must be preceded with GTP item\");\n+\tgtp_spec = gtp_item->spec;\n+\tgtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;\n+\t/* GTP spec and E flag is requested to match zero. */\n+\tif (gtp_spec &&\n+\t\t(gtp_mask->v_pt_rsv_flags &\n+\t\t~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,\n+\t\t\t \"GTP E flag must be 1 to match GTP PSC\");\n+\t/* Check the flow is not created in group zero. */\n+\tif (!attr->transfer && !attr->group)\n+\t\treturn rte_flow_error_set\n+\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t \"GTP PSC is not supported for group 0\");\n+\t/* GTP spec is here and E flag is requested to match zero. */\n+\tif (!item->spec)\n+\t\treturn 0;\n+\tmask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;\n+\treturn mlx5_flow_item_acceptable(item, (const uint8_t *)mask,\n+\t\t\t\t\t (const uint8_t *)&nic_mask,\n+\t\t\t\t\t sizeof(struct rte_flow_item_gtp_psc),\n+\t\t\t\t\t MLX5_ITEM_RANGE_NOT_ACCEPTED, error);\n+}\n+\n /**\n * Validate IPV4 item.\n * Use existing validation function mlx5_flow_validate_item_ipv4(), and\n@@ -5219,6 +5279,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \tint actions_n = 0;\n \tuint8_t item_ipv6_proto = 0;\n \tconst struct rte_flow_item *gre_item = NULL;\n+\tconst struct rte_flow_item *gtp_item = NULL;\n \tconst struct rte_flow_action_raw_decap *decap;\n \tconst struct rte_flow_action_raw_encap *encap;\n \tconst struct rte_flow_action_rss *rss;\n@@ -5551,8 +5612,17 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\t\t\t\terror);\n \t\t\tif (ret < 0)\n \t\t\t\treturn ret;\n+\t\t\tgtp_item = items;\n \t\t\tlast_item = MLX5_FLOW_LAYER_GTP;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n+\t\t\tret = flow_dv_validate_item_gtp_psc(items, last_item,\n+\t\t\t\t\t\t\t gtp_item, attr,\n+\t\t\t\t\t\t\t error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\tlast_item = MLX5_FLOW_LAYER_GTP_PSC;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_ECPRI:\n \t\t\t/* Capacity will be checked in the translate stage. */\n \t\t\tret = mlx5_flow_validate_item_ecpri(items, item_flags,\n", "prefixes": [ "RFC", "4/6" ] }