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GET /api/patches/84105/?format=api
{ "id": 84105, "url": "https://patches.dpdk.org/api/patches/84105/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1605265789-12932-5-git-send-email-juraj.linkes@pantheon.tech/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1605265789-12932-5-git-send-email-juraj.linkes@pantheon.tech>", "list_archive_url": "https://inbox.dpdk.org/dev/1605265789-12932-5-git-send-email-juraj.linkes@pantheon.tech", "date": "2020-11-13T11:09:38", "name": "[v10,04/15] build: reformat and move Arm config and comments", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c2c0da5dbe067ec3aa2a411647526b57868bc87f", "submitter": { "id": 1626, "url": "https://patches.dpdk.org/api/people/1626/?format=api", "name": "Juraj Linkeš", "email": "juraj.linkes@pantheon.tech" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1605265789-12932-5-git-send-email-juraj.linkes@pantheon.tech/mbox/", "series": [ { "id": 13869, "url": "https://patches.dpdk.org/api/series/13869/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13869", "date": "2020-11-13T11:09:35", "name": "Arm build options rework", "version": 10, "mbox": "https://patches.dpdk.org/series/13869/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/84105/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/84105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BAF7A09DE;\n\tFri, 13 Nov 2020 12:11:41 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F41BAC8E4;\n\tFri, 13 Nov 2020 12:10:14 +0100 (CET)", "from lb.pantheon.sk (lb.pantheon.sk [46.229.239.20])\n by dpdk.org (Postfix) with ESMTP id B77A1C876\n for <dev@dpdk.org>; Fri, 13 Nov 2020 12:10:02 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n by lb.pantheon.sk (Postfix) with ESMTP id 9C8A2B9982;\n Fri, 13 Nov 2020 12:10:00 +0100 (CET)", "from lb.pantheon.sk ([127.0.0.1])\n by localhost (lb.pantheon.sk [127.0.0.1]) (amavisd-new, port 10024)\n with ESMTP id gOqGnU0QRyPq; Fri, 13 Nov 2020 12:09:59 +0100 (CET)", "from service-node1.lab.pantheon.local (unknown [46.229.239.141])\n by lb.pantheon.sk (Postfix) with ESMTP id 34397B9311;\n Fri, 13 Nov 2020 12:09:53 +0100 (CET)" ], "X-Virus-Scanned": "amavisd-new at siecit.sk", "From": "=?utf-8?q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech>", "To": "bruce.richardson@intel.com, Ruifeng.Wang@arm.com,\n Honnappa.Nagarahalli@arm.com, Phil.Yang@arm.com, vcchunga@amazon.com,\n Dharmik.Thakkar@arm.com, jerinjacobk@gmail.com, hemant.agrawal@nxp.com,\n ajit.khaparde@broadcom.com, ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, =?utf-8?q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech>", "Date": "Fri, 13 Nov 2020 12:09:38 +0100", "Message-Id": "<1605265789-12932-5-git-send-email-juraj.linkes@pantheon.tech>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1605265789-12932-1-git-send-email-juraj.linkes@pantheon.tech>", "References": "<1605100718-7991-1-git-send-email-juraj.linkes@pantheon.tech>\n <1605265789-12932-1-git-send-email-juraj.linkes@pantheon.tech>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v10 04/15] build: reformat and move Arm config\n\tand comments", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Change formatting so that it's more consistent and readable, add/modify\ncomments/stdout messages, move configuration options to more appropriate\nplaces and make the order consistent according to these rules:\n1. First list generic configuration options, then list options that may\n be overwritten. List SoC-specific options last.\n2. For SoC-specific options, list number of cores before the number of\n NUMA nodes, to make it consistent with config/meson.build.\n\nSigned-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n config/arm/arm64_armv8_linux_gcc | 12 +--\n config/arm/meson.build | 96 +++++++++++--------\n .../linux_gsg/cross_build_dpdk_for_arm64.rst | 34 +++++++\n 3 files changed, 93 insertions(+), 49 deletions(-)", "diff": "diff --git a/config/arm/arm64_armv8_linux_gcc b/config/arm/arm64_armv8_linux_gcc\nindex 13ee8b223..0099f5ca2 100644\n--- a/config/arm/arm64_armv8_linux_gcc\n+++ b/config/arm/arm64_armv8_linux_gcc\n@@ -13,16 +13,6 @@ cpu = 'armv8-a'\n endian = 'little'\n \n [properties]\n+# Generate binaries that are portable across all Armv8 machines\n implementer_id = 'generic'\n-\n-# Valid options for Arm's part_number:\n-# 'generic': valid for all armv8-a architectures (default value)\n-# '0xd03': cortex-a53\n-# '0xd04': cortex-a35\n-# '0xd05': cortex-a55\n-# '0xd07': cortex-a57\n-# '0xd08': cortex-a72\n-# '0xd09': cortex-a73\n-# '0xd0a': cortex-a75\n-# '0xd0b': cortex-a76\n part_number = 'generic'\ndiff --git a/config/arm/meson.build b/config/arm/meson.build\nindex ee9277b5d..7ab856143 100644\n--- a/config/arm/meson.build\n+++ b/config/arm/meson.build\n@@ -5,15 +5,16 @@\n \n arm_force_native_march = false\n \n+# common flags to all aarch64 builds, with lowest priority\n flags_common = [\n-\t# Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)\n+\t# Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)\n \t# to determine the best threshold in code. Refer to notes in source file\n \t# (lib/librte_eal/arm/include/rte_memcpy_64.h) for more info.\n \t['RTE_ARCH_ARM64_MEMCPY', false],\n \t#\t['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048],\n \t#\t['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512],\n-\t# Leave below RTE_ARM64_MEMCPY_xxx options commented out, unless there're\n-\t# strong reasons.\n+\t# Leave below RTE_ARM64_MEMCPY_xxx options commented out,\n+\t# unless there are strong reasons.\n \t#\t['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false],\n \t#\t['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF],\n \t#\t['RTE_ARM64_MEMCPY_STRICT_ALIGN', false],\n@@ -23,69 +24,86 @@ flags_common = [\n \n \t['RTE_SCHED_VECTOR', false],\n \t['RTE_ARM_USE_WFE', false],\n+\t['RTE_ARCH_ARM64', true],\n+\t['RTE_CACHE_LINE_SIZE', 128]\n ]\n \n+# implementer specific aarch64 flags, with middle priority\n+# (will overwrite common flags)\n flags_implementer_generic = [\n \t['RTE_MACHINE', '\"armv8a\"'],\n-\t['RTE_MAX_LCORE', 256],\n \t['RTE_USE_C11_MEM_MODEL', true],\n-\t['RTE_CACHE_LINE_SIZE', 128]]\n+\t['RTE_CACHE_LINE_SIZE', 128],\n+\t['RTE_MAX_LCORE', 256]\n+]\n flags_implementer_arm = [\n \t['RTE_MACHINE', '\"armv8a\"'],\n-\t['RTE_MAX_LCORE', 16],\n \t['RTE_USE_C11_MEM_MODEL', true],\n-\t['RTE_CACHE_LINE_SIZE', 64]]\n+\t['RTE_CACHE_LINE_SIZE', 64],\n+\t['RTE_MAX_LCORE', 16]\n+]\n flags_implementer_cavium = [\n+\t['RTE_MAX_VFIO_GROUPS', 128],\n \t['RTE_CACHE_LINE_SIZE', 128],\n-\t['RTE_MAX_NUMA_NODES', 2],\n \t['RTE_MAX_LCORE', 96],\n-\t['RTE_MAX_VFIO_GROUPS', 128]]\n+\t['RTE_MAX_NUMA_NODES', 2]\n+]\n flags_implementer_dpaa = [\n \t['RTE_MACHINE', '\"dpaa\"'],\n+\t['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],\n \t['RTE_USE_C11_MEM_MODEL', true],\n \t['RTE_CACHE_LINE_SIZE', 64],\n-\t['RTE_MAX_NUMA_NODES', 1],\n \t['RTE_MAX_LCORE', 16],\n-\t['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]\n+\t['RTE_MAX_NUMA_NODES', 1]\n+]\n flags_implementer_emag = [\n \t['RTE_MACHINE', '\"emag\"'],\n \t['RTE_CACHE_LINE_SIZE', 64],\n-\t['RTE_MAX_NUMA_NODES', 1],\n-\t['RTE_MAX_LCORE', 32]]\n+\t['RTE_MAX_LCORE', 32],\n+\t['RTE_MAX_NUMA_NODES', 1]\n+]\n flags_implementer_armada = [\n \t['RTE_MACHINE', '\"armv8a\"'],\n \t['RTE_CACHE_LINE_SIZE', 64],\n-\t['RTE_MAX_NUMA_NODES', 1],\n-\t['RTE_MAX_LCORE', 16]]\n+\t['RTE_MAX_LCORE', 16],\n+\t['RTE_MAX_NUMA_NODES', 1]\n+]\n \n+# part number specific aarch64 flags, with highest priority\n+# (will overwrite both common and implementer specific flags)\n flags_part_number_thunderx = [\n \t['RTE_MACHINE', '\"thunderx\"'],\n-\t['RTE_USE_C11_MEM_MODEL', false]]\n+\t['RTE_USE_C11_MEM_MODEL', false]\n+]\n flags_part_number_thunderx2 = [\n \t['RTE_MACHINE', '\"thunderx2\"'],\n+\t['RTE_ARM_FEATURE_ATOMICS', true],\n+\t['RTE_USE_C11_MEM_MODEL', true],\n \t['RTE_CACHE_LINE_SIZE', 64],\n-\t['RTE_MAX_NUMA_NODES', 2],\n \t['RTE_MAX_LCORE', 256],\n-\t['RTE_ARM_FEATURE_ATOMICS', true],\n-\t['RTE_USE_C11_MEM_MODEL', true]]\n+\t['RTE_MAX_NUMA_NODES', 2]\n+]\n flags_part_number_octeontx2 = [\n \t['RTE_MACHINE', '\"octeontx2\"'],\n-\t['RTE_MAX_NUMA_NODES', 1],\n-\t['RTE_MAX_LCORE', 36],\n \t['RTE_ARM_FEATURE_ATOMICS', true],\n+\t['RTE_USE_C11_MEM_MODEL', true],\n \t['RTE_EAL_IGB_UIO', false],\n-\t['RTE_USE_C11_MEM_MODEL', true]]\n+\t['RTE_MAX_LCORE', 36],\n+\t['RTE_MAX_NUMA_NODES', 1]\n+]\n flags_part_number_n1generic = [\n \t['RTE_MACHINE', '\"neoverse-n1\"'],\n-\t['RTE_MAX_LCORE', 64],\n-\t['RTE_CACHE_LINE_SIZE', 64],\n \t['RTE_ARM_FEATURE_ATOMICS', true],\n \t['RTE_USE_C11_MEM_MODEL', true],\n-\t['RTE_MAX_MEM_MB', 1048576],\n-\t['RTE_MAX_NUMA_NODES', 1],\n \t['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],\n-\t['RTE_LIBRTE_VHOST_NUMA', false]]\n+\t['RTE_LIBRTE_VHOST_NUMA', false],\n+\t['RTE_MAX_MEM_MB', 1048576],\n+\t['RTE_CACHE_LINE_SIZE', 64],\n+\t['RTE_MAX_LCORE', 64],\n+\t['RTE_MAX_NUMA_NODES', 1]\n+]\n \n+# arm config (implementer 0x41) is the default config\n part_number_config_arm = [\n \t['generic', ['-march=armv8-a+crc', '-moutline-atomics']],\n \t['native', ['-march=native']],\n@@ -96,8 +114,8 @@ part_number_config_arm = [\n \t['0xd09', ['-mcpu=cortex-a73']],\n \t['0xd0a', ['-mcpu=cortex-a75']],\n \t['0xd0b', ['-mcpu=cortex-a76']],\n-\t['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic]]\n-\n+\t['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_part_number_n1generic]\n+]\n part_number_config_cavium = [\n \t['generic', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],\n \t['native', ['-march=native']],\n@@ -105,13 +123,14 @@ part_number_config_cavium = [\n \t['0xa2', ['-mcpu=thunderxt81'], flags_part_number_thunderx],\n \t['0xa3', ['-mcpu=thunderxt83'], flags_part_number_thunderx],\n \t['0xaf', ['-march=armv8.1-a+crc+crypto','-mcpu=thunderx2t99'], flags_part_number_thunderx2],\n-\t['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]]\n-\n+\t['0xb2', ['-march=armv8.2-a+crc+crypto+lse','-mcpu=octeontx2'], flags_part_number_octeontx2]\n+]\n part_number_config_emag = [\n \t['generic', ['-march=armv8-a+crc+crypto', '-mtune=emag']],\n-\t['native', ['-march=native']]]\n+\t['native', ['-march=native']]\n+]\n \n-## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321)\n+## Arm implementer ID (MIDR in Arm Architecture Reference Manual)\n implementer_generic = ['Generic armv8', flags_implementer_generic, part_number_config_arm]\n implementer_0x41 = ['Arm', flags_implementer_arm, part_number_config_arm]\n implementer_0x43 = ['Cavium', flags_implementer_cavium, part_number_config_cavium]\n@@ -123,21 +142,21 @@ dpdk_conf.set('RTE_ARCH_ARM', 1)\n dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)\n \n if dpdk_conf.get('RTE_ARCH_32')\n+\t# armv7 build\n \tdpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)\n \tdpdk_conf.set('RTE_ARCH_ARMv7', 1)\n \t# the minimum architecture supported, armv7-a, needs the following,\n-\t# mk/machine/armv7a/rte.vars.mk sets it too\n \tmachine_args += '-mfpu=neon'\n else\n-\tdpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)\n-\tdpdk_conf.set('RTE_ARCH_ARM64', 1)\n-\n+\t# aarch64 build\n \timplementer_id = 'generic'\n \tmachine_args = [] # Clear previous machine args\n \tif machine == 'generic' and not meson.is_cross_build()\n+\t\t# generic build\n \t\timplementer_config = implementer_generic\n \t\tpart_number = 'generic'\n \telif not meson.is_cross_build()\n+\t\t# native build\n \t\t# The script returns ['Implementer', 'Variant', 'Architecture',\n \t\t# 'Primary Part number', 'Revision']\n \t\tdetect_vendor = find_program(join_paths(\n@@ -158,6 +177,7 @@ else\n \t\t\tpart_number = 'native'\n \t\tendif\n \telse\n+\t\t# cross build\n \t\timplementer_id = meson.get_cross_property('implementer_id', 'generic')\n \t\tpart_number = meson.get_cross_property('part_number', 'generic')\n \t\timplementer_config = get_variable('implementer_' + implementer_id)\n@@ -194,7 +214,7 @@ else\n \t\tendif\n \tendforeach\n endif\n-message(machine_args)\n+message('Using machine args: @0@'.format(machine_args))\n \n if (cc.get_define('__ARM_NEON', args: machine_args) != '' or\n cc.get_define('__aarch64__', args: machine_args) != '')\ndiff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_arm64.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_arm64.rst\nindex 8a1d0e88b..972598835 100644\n--- a/doc/guides/linux_gsg/cross_build_dpdk_for_arm64.rst\n+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_arm64.rst\n@@ -99,3 +99,37 @@ command::\n \n \tmeson arm64-build --cross-file config/arm/arm64_armv8_linux_gcc\n \tninja -C arm64-build\n+\n+Supported cross-compilation targets\n+-----------------------------------\n+\n+If you wish to build for a target which is not among the current cross-files,\n+you may use various combinations of implementer/part number::\n+\n+ Supported implementers:\n+ 'generic': Generic armv8\n+ '0x41': Arm\n+ '0x43': Cavium\n+ '0x50': Ampere Computing\n+ '0x56': Marvell ARMADA\n+ 'dpaa': NXP DPAA\n+\n+ Supported part_numbers for generic, 0x41, 0x56, dpaa:\n+ 'generic': valid for all armv8-a architectures (default value)\n+ '0xd03': cortex-a53\n+ '0xd04': cortex-a35\n+ '0xd09': cortex-a73\n+ '0xd0a': cortex-a75\n+ '0xd0b': cortex-a76\n+ '0xd0c': neoverse-n1\n+\n+ Supported part_numbers for 0x43:\n+ 'generic': valid for all Cavium builds\n+ '0xa1': thunderxt88\n+ '0xa2': thunderxt81\n+ '0xa3': thunderxt83\n+ '0xaf': thunderx2t99\n+ '0xb2': octeontx2\n+\n+ Supported part_numbers for 0x50:\n+ 'generic': valid for all Ampere builds\n", "prefixes": [ "v10", "04/15" ] }