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GET /api/patches/83436/?format=api
{ "id": 83436, "url": "https://patches.dpdk.org/api/patches/83436/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201102183527.69209-4-aboyer@pensando.io/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201102183527.69209-4-aboyer@pensando.io>", "list_archive_url": "https://inbox.dpdk.org/dev/20201102183527.69209-4-aboyer@pensando.io", "date": "2020-11-02T18:35:22", "name": "[3/8] ionic: update ionic_if.h to the latest version", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "1e17258f10ea341b4ea43425bc308a6fe9958980", "submitter": { "id": 2036, "url": "https://patches.dpdk.org/api/people/2036/?format=api", "name": "Andrew Boyer", "email": "aboyer@pensando.io" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201102183527.69209-4-aboyer@pensando.io/mbox/", "series": [ { "id": 13579, "url": "https://patches.dpdk.org/api/series/13579/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13579", "date": "2020-11-02T18:35:19", "name": "net/ionic: minor updates and documentation", "version": 1, "mbox": "https://patches.dpdk.org/series/13579/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/83436/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/83436/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 699BEA04E7;\n\tMon, 2 Nov 2020 19:36:50 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 00FAA2BFA;\n\tMon, 2 Nov 2020 19:36:05 +0100 (CET)", "from mail-pg1-f195.google.com (mail-pg1-f195.google.com\n [209.85.215.195]) by dpdk.org (Postfix) with ESMTP id AF3832BFA\n for <dev@dpdk.org>; Mon, 2 Nov 2020 19:36:02 +0100 (CET)", "by mail-pg1-f195.google.com with SMTP id x13so11516977pgp.7\n for <dev@dpdk.org>; Mon, 02 Nov 2020 10:36:02 -0800 (PST)", "from driver-dev1.pensando.io ([12.226.153.42])\n by smtp.gmail.com with ESMTPSA id s4sm178186pjp.17.2020.11.02.10.35.58\n (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);\n Mon, 02 Nov 2020 10:35:59 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=s617pKhqq5FT489EtAzG8JHcTixOY6bXB718Ad3BZWA=;\n b=rACcpN/tCpMVccPIPfxikgVuZRx9NDmWbQmjHHex8s1HEfEBiCIqY/tL0FIww+30f+\n cBRDpHcVKAqPiPqFYSxdmGiTuZyUQK5bahv4FAJCvIPc3KTjuylXmAgFhVDNMKNFc7s+\n qpoBxTF8938sD8Sa8/OO1C0JRBttlcwUnDE79Aa68K3lM74xXd1XWIPRrH4FzZptv4dS\n rol/rFvpNP6JMT1oJ0Mj5YoiaTwmMb+dXrsqcL+ZM0kBDGulEDAqzOUN0U2W57wkTUYT\n pOt6vUEqRX6hSvsh3B515kO9AzfM8f73ia473MLZdliosDhg0Vwm9v2dL5fyrNyUuz8n\n QzpQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=s617pKhqq5FT489EtAzG8JHcTixOY6bXB718Ad3BZWA=;\n b=IJbdcrU5dZic+S5p12vt+jFm+PIO2eBHu3F96I+BUxDMuTfQXv9YpoF29X1RvKPu4Y\n q2qqkCZibJNMxNoWPJSKjP2I71UkYsfFdESTOB2R9DJvInme+K0HxeVRpqtZDG/UVYHG\n lrjsSx5bjaV4f6k/eHu5YQSVY8I8pAN6QjESjziBTIFm2BgpvxPNbbwVohNQCiFAgCfq\n 4B/Z5q1MdRtiheGBOkjiXtiLGfA4S1CoE03JcAngtJngFM6uopg5YWbOV+k5d+FX0AmD\n WW78yVDb2kxz/lA2xu9sP56XT5+KA3eOTuM1s0z242jYphN5moG0muZJ7LsMioQ/m54i\n jjmA==", "X-Gm-Message-State": "AOAM532QOIvuQD3s0KCNxJQYs/gItiUlFzgijdoj5FInOiS2s/QvgAtR\n pMc9r0iJs49goar3KvciIdOteN0/UvOe0JoW", "X-Google-Smtp-Source": "\n ABdhPJwMOUrXJ6Xbzj3P68hPhXQClW6LKSdgO0JXZ28xqWzpp/r07YcFwguI/yzWZdaEWyzjsWRhFA==", "X-Received": "by 2002:a17:90b:378c:: with SMTP id\n mz12mr19323323pjb.137.1604342160014;\n Mon, 02 Nov 2020 10:36:00 -0800 (PST)", "From": "Andrew Boyer <aboyer@pensando.io>", "To": "dev@dpdk.org", "Cc": "cardigliano@ntop.org,\n\tAndrew Boyer <aboyer@pensando.io>", "Date": "Mon, 2 Nov 2020 10:35:22 -0800", "Message-Id": "<20201102183527.69209-4-aboyer@pensando.io>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20201102183527.69209-1-aboyer@pensando.io>", "References": "<20201102183527.69209-1-aboyer@pensando.io>", "Subject": "[dpdk-dev] [PATCH 3/8] ionic: update ionic_if.h to the latest\n\tversion", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This file contains the firmware interface definitions.\n\nSigned-off-by: Andrew Boyer <aboyer@pensando.io>\n---\n drivers/net/ionic/ionic_if.h | 1349 ++++++++++++++++++++++----------\n drivers/net/ionic/ionic_regs.h | 3 -\n 2 files changed, 933 insertions(+), 419 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_if.h b/drivers/net/ionic/ionic_if.h\nindex f83c8711b..fe6b52b17 100644\n--- a/drivers/net/ionic/ionic_if.h\n+++ b/drivers/net/ionic/ionic_if.h\n@@ -1,17 +1,15 @@\n-/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-3-Clause */\n-/* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */\n+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */\n+/* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */\n \n #ifndef _IONIC_IF_H_\n #define _IONIC_IF_H_\n \n-#pragma pack(push, 1)\n-\n #define IONIC_DEV_INFO_SIGNATURE\t\t0x44455649 /* 'DEVI' */\n #define IONIC_DEV_INFO_VERSION\t\t\t1\n #define IONIC_IFNAMSIZ\t\t\t\t16\n \n /**\n- * Commands\n+ * enum ionic_cmd_opcode - Device commands\n */\n enum ionic_cmd_opcode {\n \tIONIC_CMD_NOP\t\t\t\t= 0,\n@@ -42,6 +40,7 @@ enum ionic_cmd_opcode {\n \tIONIC_CMD_RX_FILTER_DEL\t\t\t= 32,\n \n \t/* Queue commands */\n+\tIONIC_CMD_Q_IDENTIFY\t\t\t= 39,\n \tIONIC_CMD_Q_INIT\t\t\t= 40,\n \tIONIC_CMD_Q_CONTROL\t\t\t= 41,\n \n@@ -51,10 +50,17 @@ enum ionic_cmd_opcode {\n \tIONIC_CMD_RDMA_CREATE_CQ\t\t= 52,\n \tIONIC_CMD_RDMA_CREATE_ADMINQ\t\t= 53,\n \n+\t/* SR/IOV commands */\n+\tIONIC_CMD_VF_GETATTR\t\t\t= 60,\n+\tIONIC_CMD_VF_SETATTR\t\t\t= 61,\n+\n \t/* QoS commands */\n \tIONIC_CMD_QOS_CLASS_IDENTIFY\t\t= 240,\n \tIONIC_CMD_QOS_CLASS_INIT\t\t= 241,\n \tIONIC_CMD_QOS_CLASS_RESET\t\t= 242,\n+\tIONIC_CMD_QOS_CLASS_UPDATE\t\t= 243,\n+\tIONIC_CMD_QOS_CLEAR_STATS\t\t= 244,\n+\tIONIC_CMD_QOS_RESET\t\t\t= 245,\n \n \t/* Firmware commands */\n \tIONIC_CMD_FW_DOWNLOAD\t\t\t= 254,\n@@ -62,7 +68,7 @@ enum ionic_cmd_opcode {\n };\n \n /**\n- * Command Return codes\n+ * enum ionic_status_code - Device command return codes\n */\n enum ionic_status_code {\n \tIONIC_RC_SUCCESS\t= 0,\t/* Success */\n@@ -86,8 +92,8 @@ enum ionic_status_code {\n \tIONIC_RC_DEV_CMD\t= 18,\t/* Device cmd attempted on AdminQ */\n \tIONIC_RC_ENOSUPP\t= 19,\t/* Operation not supported */\n \tIONIC_RC_ERROR\t\t= 29,\t/* Generic error */\n-\n \tIONIC_RC_ERDMA\t\t= 30,\t/* Generic RDMA error */\n+\tIONIC_RC_EVFID\t\t= 31,\t/* VF ID does not exist */\n };\n \n enum ionic_notifyq_opcode {\n@@ -95,10 +101,11 @@ enum ionic_notifyq_opcode {\n \tIONIC_EVENT_RESET\t\t= 2,\n \tIONIC_EVENT_HEARTBEAT\t\t= 3,\n \tIONIC_EVENT_LOG\t\t\t= 4,\n+\tIONIC_EVENT_XCVR\t\t= 5,\n };\n \n /**\n- * struct cmd - General admin command format\n+ * struct ionic_admin_cmd - General admin command format\n * @opcode: Opcode for the command\n * @lif_index: LIF index\n * @cmd_data: Opcode-specific command bytes\n@@ -112,12 +119,11 @@ struct ionic_admin_cmd {\n \n /**\n * struct ionic_admin_comp - General admin command completion format\n- * @status: The status of the command (enum status_code)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n- * @cmd_data: Command-specific bytes.\n- * @color: Color bit. (Always 0 for commands issued to the\n- * Device Cmd Registers.)\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @cmd_data: Command-specific bytes\n+ * @color: Color bit (Always 0 for commands issued to the\n+ * Device Cmd Registers)\n */\n struct ionic_admin_comp {\n \tu8 status;\n@@ -144,7 +150,7 @@ struct ionic_nop_cmd {\n \n /**\n * struct ionic_nop_comp - NOP command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n */\n struct ionic_nop_comp {\n \tu8 status;\n@@ -154,7 +160,7 @@ struct ionic_nop_comp {\n /**\n * struct ionic_dev_init_cmd - Device init command\n * @opcode: opcode\n- * @type: device type\n+ * @type: Device type\n */\n struct ionic_dev_init_cmd {\n \tu8 opcode;\n@@ -163,8 +169,8 @@ struct ionic_dev_init_cmd {\n };\n \n /**\n- * struct init_comp - Device init command completion\n- * @status: The status of the command (enum status_code)\n+ * struct ionic_dev_init_comp - Device init command completion\n+ * @status: Status of the command (enum ionic_status_code)\n */\n struct ionic_dev_init_comp {\n \tu8 status;\n@@ -181,8 +187,8 @@ struct ionic_dev_reset_cmd {\n };\n \n /**\n- * struct reset_comp - Reset command completion\n- * @status: The status of the command (enum status_code)\n+ * struct ionic_dev_reset_comp - Reset command completion\n+ * @status: Status of the command (enum ionic_status_code)\n */\n struct ionic_dev_reset_comp {\n \tu8 status;\n@@ -203,8 +209,8 @@ struct ionic_dev_identify_cmd {\n };\n \n /**\n- * struct dev_identify_comp - Driver/device identify command completion\n- * @status: The status of the command (enum status_code)\n+ * struct ionic_dev_identify_comp - Driver/device identify command completion\n+ * @status: Status of the command (enum ionic_status_code)\n * @ver: Version of identify returned by device\n */\n struct ionic_dev_identify_comp {\n@@ -223,8 +229,8 @@ enum ionic_os_type {\n };\n \n /**\n- * union drv_identity - driver identity information\n- * @os_type: OS type (see enum os_type)\n+ * union ionic_drv_identity - driver identity information\n+ * @os_type: OS type (see enum ionic_os_type)\n * @os_dist: OS distribution, numeric format\n * @os_dist_str: OS distribution, string format\n * @kernel_ver: Kernel version, numeric format\n@@ -240,26 +246,26 @@ union ionic_drv_identity {\n \t\tchar kernel_ver_str[32];\n \t\tchar driver_ver_str[32];\n \t};\n-\t__le32 words[512];\n+\t__le32 words[478];\n };\n \n /**\n- * union dev_identity - device identity information\n+ * union ionic_dev_identity - device identity information\n * @version: Version of device identify\n * @type: Identify type (0 for now)\n * @nports: Number of ports provisioned\n * @nlifs: Number of LIFs provisioned\n * @nintrs: Number of interrupts provisioned\n * @ndbpgs_per_lif: Number of doorbell pages per LIF\n- * @intr_coal_mult: Interrupt coalescing multiplication factor.\n+ * @intr_coal_mult: Interrupt coalescing multiplication factor\n * Scale user-supplied interrupt coalescing\n * value in usecs to device units using:\n * device units = usecs * mult / div\n- * @intr_coal_div: Interrupt coalescing division factor.\n+ * @intr_coal_div: Interrupt coalescing division factor\n * Scale user-supplied interrupt coalescing\n * value in usecs to device units using:\n * device units = usecs * mult / div\n- *\n+ * @eq_count: Number of shared event queues\n */\n union ionic_dev_identity {\n \tstruct {\n@@ -273,8 +279,9 @@ union ionic_dev_identity {\n \t\t__le32 ndbpgs_per_lif;\n \t\t__le32 intr_coal_mult;\n \t\t__le32 intr_coal_div;\n+\t\t__le32 eq_count;\n \t};\n-\t__le32 words[512];\n+\t__le32 words[478];\n };\n \n enum ionic_lif_type {\n@@ -284,10 +291,10 @@ enum ionic_lif_type {\n };\n \n /**\n- * struct ionic_lif_identify_cmd - lif identify command\n+ * struct ionic_lif_identify_cmd - LIF identify command\n * @opcode: opcode\n- * @type: lif type (enum lif_type)\n- * @ver: version of identify returned by device\n+ * @type: LIF type (enum ionic_lif_type)\n+ * @ver: Version of identify returned by device\n */\n struct ionic_lif_identify_cmd {\n \tu8 opcode;\n@@ -297,9 +304,9 @@ struct ionic_lif_identify_cmd {\n };\n \n /**\n- * struct ionic_lif_identify_comp - lif identify command completion\n- * @status: status of the command (enum status_code)\n- * @ver: version of identify returned by device\n+ * struct ionic_lif_identify_comp - LIF identify command completion\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @ver: Version of identify returned by device\n */\n struct ionic_lif_identify_comp {\n \tu8 status;\n@@ -307,13 +314,24 @@ struct ionic_lif_identify_comp {\n \tu8 rsvd2[14];\n };\n \n+/**\n+ * enum ionic_lif_capability - LIF capabilities\n+ * @IONIC_LIF_CAP_ETH: LIF supports Ethernet\n+ * @IONIC_LIF_CAP_RDMA: LIF support RDMA\n+ */\n enum ionic_lif_capability {\n \tIONIC_LIF_CAP_ETH = BIT(0),\n \tIONIC_LIF_CAP_RDMA = BIT(1),\n };\n \n /**\n- * Logical Queue Types\n+ * enum ionic_logical_qtype - Logical Queue Types\n+ * @IONIC_QTYPE_ADMINQ: Administrative Queue\n+ * @IONIC_QTYPE_NOTIFYQ: Notify Queue\n+ * @IONIC_QTYPE_RXQ: Receive Queue\n+ * @IONIC_QTYPE_TXQ: Transmit Queue\n+ * @IONIC_QTYPE_EQ: Event Queue\n+ * @IONIC_QTYPE_MAX: Max queue type supported\n */\n enum ionic_logical_qtype {\n \tIONIC_QTYPE_ADMINQ = 0,\n@@ -325,11 +343,10 @@ enum ionic_logical_qtype {\n };\n \n /**\n- * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue\n- * type.\n- * @qtype: Hardware Queue Type.\n- * @qid_count: Number of Queue IDs of the logical type.\n- * @qid_base: Minimum Queue ID of the logical type.\n+ * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type\n+ * @qtype: Hardware Queue Type\n+ * @qid_count: Number of Queue IDs of the logical type\n+ * @qid_base: Minimum Queue ID of the logical type\n */\n struct ionic_lif_logical_qtype {\n \tu8 qtype;\n@@ -338,20 +355,27 @@ struct ionic_lif_logical_qtype {\n \t__le32 qid_base;\n };\n \n+/**\n+ * enum ionic_lif_state - LIF state\n+ * @IONIC_LIF_DISABLE: LIF disabled\n+ * @IONIC_LIF_ENABLE: LIF enabled\n+ * @IONIC_LIF_QUIESCE: LIF Quiesced\n+ */\n enum ionic_lif_state {\n-\tIONIC_LIF_DISABLE\t= 0,\n+\tIONIC_LIF_QUIESCE\t= 0,\n \tIONIC_LIF_ENABLE\t= 1,\n-\tIONIC_LIF_HANG_RESET\t= 2,\n+\tIONIC_LIF_DISABLE\t= 2,\n };\n \n /**\n- * LIF configuration\n- * @state: lif state (enum lif_state)\n- * @name: lif name\n- * @mtu: mtu\n- * @mac: station mac address\n- * @features: features (enum ionic_eth_hw_features)\n- * @queue_count: queue counts per queue-type\n+ * union ionic_lif_config - LIF configuration\n+ * @state: LIF state (enum ionic_lif_state)\n+ * @name: LIF name\n+ * @mtu: MTU\n+ * @mac: Station MAC address\n+ * @vlan: Default Vlan ID\n+ * @features: Features (enum ionic_eth_hw_features)\n+ * @queue_count: Queue counts per queue-type\n */\n union ionic_lif_config {\n \tstruct {\n@@ -360,45 +384,44 @@ union ionic_lif_config {\n \t\tchar name[IONIC_IFNAMSIZ];\n \t\t__le32 mtu;\n \t\tu8 mac[6];\n-\t\tu8 rsvd2[2];\n+\t\t__le16 vlan;\n \t\t__le64 features;\n \t\t__le32 queue_count[IONIC_QTYPE_MAX];\n-\t};\n+\t} __rte_packed;\n \t__le32 words[64];\n };\n \n /**\n- * struct ionic_lif_identity - lif identity information (type-specific)\n+ * struct ionic_lif_identity - LIF identity information (type-specific)\n *\n- * @capabilities LIF capabilities\n+ * @capabilities: LIF capabilities\n *\n- * Ethernet:\n- * @version: Ethernet identify structure version.\n- * @features: Ethernet features supported on this lif type.\n- * @max_ucast_filters: Number of perfect unicast addresses supported.\n- * @max_mcast_filters: Number of perfect multicast addresses supported.\n- * @min_frame_size: Minimum size of frames to be sent\n- * @max_frame_size: Maximum size of frames to be sent\n- * @config: LIF config struct with features, mtu, mac, q counts\n+ * @eth: Ethernet identify structure\n+ * @version: Ethernet identify structure version\n+ * @max_ucast_filters: Number of perfect unicast addresses supported\n+ * @max_mcast_filters: Number of perfect multicast addresses supported\n+ * @min_frame_size: Minimum size of frames to be sent\n+ * @max_frame_size: Maximim size of frames to be sent\n+ * @config: LIF config struct with features, mtu, mac, q counts\n *\n- * RDMA:\n- * @version: RDMA version of opcodes and queue descriptors.\n- * @qp_opcodes: Number of rdma queue pair opcodes supported.\n- * @admin_opcodes: Number of rdma admin opcodes supported.\n- * @npts_per_lif: Page table size per lif\n- * @nmrs_per_lif: Number of memory regions per lif\n- * @nahs_per_lif: Number of address handles per lif\n- * @max_stride: Max work request stride.\n- * @cl_stride: Cache line stride.\n- * @pte_stride: Page table entry stride.\n- * @rrq_stride: Remote RQ work request stride.\n- * @rsq_stride: Remote SQ work request stride.\n+ * @rdma: RDMA identify structure\n+ * @version: RDMA version of opcodes and queue descriptors\n+ * @qp_opcodes: Number of RDMA queue pair opcodes supported\n+ * @admin_opcodes: Number of RDMA admin opcodes supported\n+ * @npts_per_lif: Page table size per LIF\n+ * @nmrs_per_lif: Number of memory regions per LIF\n+ * @nahs_per_lif: Number of address handles per LIF\n+ * @max_stride: Max work request stride\n+ * @cl_stride: Cache line stride\n+ * @pte_stride: Page table entry stride\n+ * @rrq_stride: Remote RQ work request stride\n+ * @rsq_stride: Remote SQ work request stride\n * @dcqcn_profiles: Number of DCQCN profiles\n- * @aq_qtype: RDMA Admin Qtype.\n- * @sq_qtype: RDMA Send Qtype.\n- * @rq_qtype: RDMA Receive Qtype.\n- * @cq_qtype: RDMA Completion Qtype.\n- * @eq_qtype: RDMA Event Qtype.\n+ * @aq_qtype: RDMA Admin Qtype\n+ * @sq_qtype: RDMA Send Qtype\n+ * @rq_qtype: RDMA Receive Qtype\n+ * @cq_qtype: RDMA Completion Qtype\n+ * @eq_qtype: RDMA Event Qtype\n */\n union ionic_lif_identity {\n \tstruct {\n@@ -414,7 +437,7 @@ union ionic_lif_identity {\n \t\t\t__le32 max_frame_size;\n \t\t\tu8 rsvd2[106];\n \t\t\tunion ionic_lif_config config;\n-\t\t} eth;\n+\t\t} __rte_packed eth;\n \n \t\tstruct {\n \t\t\tu8 version;\n@@ -436,17 +459,17 @@ union ionic_lif_identity {\n \t\t\tstruct ionic_lif_logical_qtype rq_qtype;\n \t\t\tstruct ionic_lif_logical_qtype cq_qtype;\n \t\t\tstruct ionic_lif_logical_qtype eq_qtype;\n-\t\t} rdma;\n-\t};\n-\t__le32 words[512];\n+\t\t} __rte_packed rdma;\n+\t} __rte_packed;\n+\t__le32 words[478];\n };\n \n /**\n * struct ionic_lif_init_cmd - LIF init command\n- * @opcode: opcode\n- * @type: LIF type (enum lif_type)\n+ * @opcode: Opcode\n+ * @type: LIF type (enum ionic_lif_type)\n * @index: LIF index\n- * @info_pa: destination address for lif info (struct ionic_lif_info)\n+ * @info_pa: Destination address for LIF info (struct ionic_lif_info)\n */\n struct ionic_lif_init_cmd {\n \tu8 opcode;\n@@ -459,7 +482,8 @@ struct ionic_lif_init_cmd {\n \n /**\n * struct ionic_lif_init_comp - LIF init command completion\n- * @status: The status of the command (enum status_code)\n+ * @status:\tStatus of the command (enum ionic_status_code)\n+ * @hw_index:\tHardware index of the initialized LIF\n */\n struct ionic_lif_init_comp {\n \tu8 status;\n@@ -468,14 +492,74 @@ struct ionic_lif_init_comp {\n \tu8 rsvd2[12];\n };\n \n+/**\n+ * struct ionic_q_identify_cmd - queue identify command\n+ * @opcode: opcode\n+ * @lif_type: LIF type (enum ionic_lif_type)\n+ * @type: Logical queue type (enum ionic_logical_qtype)\n+ * @ver: Highest queue type version that the driver supports\n+ */\n+struct ionic_q_identify_cmd {\n+\tu8 opcode;\n+\tu8 rsvd;\n+\t__le16 lif_type;\n+\tu8 type;\n+\tu8 ver;\n+\tu8 rsvd2[58];\n+};\n+\n+/**\n+ * struct ionic_q_identify_comp - queue identify command completion\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @ver: Queue type version that can be used with FW\n+ */\n+struct ionic_q_identify_comp {\n+\tu8 status;\n+\tu8 rsvd;\n+\t__le16 comp_index;\n+\tu8 ver;\n+\tu8 rsvd2[11];\n+};\n+\n+/**\n+ * union ionic_q_identity - queue identity information\n+ * @version: Queue type version that can be used with FW\n+ * @supported: Bitfield of queue versions, first bit = ver 0\n+ * @features: Queue features\n+ * @desc_sz: Descriptor size\n+ * @comp_sz: Completion descriptor size\n+ * @sg_desc_sz: Scatter/Gather descriptor size\n+ * @max_sg_elems: Maximum number of Scatter/Gather elements\n+ * @sg_desc_stride: Number of Scatter/Gather elements per descriptor\n+ */\n+union ionic_q_identity {\n+\tstruct {\n+\t\tu8 version;\n+\t\tu8 supported;\n+\t\tu8 rsvd[6];\n+#define IONIC_QIDENT_F_CQ\t0x01\t/* queue has completion ring */\n+#define IONIC_QIDENT_F_SG\t0x02\t/* queue has scatter/gather ring */\n+#define IONIC_QIDENT_F_EQ\t0x04\t/* queue can use event queue */\n+#define IONIC_QIDENT_F_CMB\t0x08\t/* queue is in cmb bar */\n+\t\t__le64 features;\n+\t\t__le16 desc_sz;\n+\t\t__le16 comp_sz;\n+\t\t__le16 sg_desc_sz;\n+\t\t__le16 max_sg_elems;\n+\t\t__le16 sg_desc_stride;\n+\t};\n+\t__le32 words[478];\n+};\n+\n /**\n * struct ionic_q_init_cmd - Queue init command\n * @opcode: opcode\n * @type: Logical queue type\n- * @ver: Queue version (defines opcode/descriptor scope)\n+ * @ver: Queue type version\n * @lif_index: LIF index\n- * @index: (lif, qtype) relative admin queue index\n- * @intr_index: Interrupt control register index\n+ * @index: (LIF, qtype) relative admin queue index\n+ * @intr_index: Interrupt control register index, or Event queue index\n * @pid: Process ID\n * @flags:\n * IRQ: Interrupt requested on completion\n@@ -493,12 +577,11 @@ struct ionic_lif_init_comp {\n * descriptors. Values of ring_size <2 and >16 are\n * reserved.\n * EQ: Enable the Event Queue\n- * @cos: Class of service for this queue.\n+ * @cos: Class of service for this queue\n * @ring_size: Queue ring size, encoded as a log2(size)\n * @ring_base: Queue ring base address\n * @cq_ring_base: Completion queue ring base address\n * @sg_ring_base: Scatter/Gather ring base address\n- * @eq_index:\t Event queue index\n */\n struct ionic_q_init_cmd {\n \tu8 opcode;\n@@ -515,29 +598,27 @@ struct ionic_q_init_cmd {\n #define IONIC_QINIT_F_ENA\t0x02\t/* Enable the queue */\n #define IONIC_QINIT_F_SG\t0x04\t/* Enable scatter/gather on the queue */\n #define IONIC_QINIT_F_EQ\t0x08\t/* Enable event queue */\n-#define IONIC_QINIT_F_DEBUG 0x80\t/* Enable queue debugging */\n+#define IONIC_QINIT_F_CMB\t0x10\t/* Enable cmb-based queue */\n+#define IONIC_QINIT_F_DEBUG\t0x80\t/* Enable queue debugging */\n \tu8 cos;\n \tu8 ring_size;\n \t__le64 ring_base;\n \t__le64 cq_ring_base;\n \t__le64 sg_ring_base;\n-\t__le32 eq_index;\n-\tu8 rsvd2[16];\n-};\n+\tu8 rsvd2[20];\n+} __rte_packed;\n \n /**\n * struct ionic_q_init_comp - Queue init command completion\n- * @status: The status of the command (enum status_code)\n- * @ver: Queue version (defines opcode/descriptor scope)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n * @hw_index: Hardware Queue ID\n * @hw_type: Hardware Queue type\n * @color: Color\n */\n struct ionic_q_init_comp {\n \tu8 status;\n-\tu8 ver;\n+\tu8 rsvd;\n \t__le16 comp_index;\n \t__le32 hw_index;\n \tu8 hw_type;\n@@ -558,10 +639,9 @@ enum ionic_txq_desc_opcode {\n \n /**\n * struct ionic_txq_desc - Ethernet Tx queue descriptor format\n- * @opcode: Tx operation, see TXQ_DESC_OPCODE_*:\n+ * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:\n *\n * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:\n- *\n * Non-offload send. No segmentation,\n * fragmentation or checksum calc/insertion is\n * performed by device; packet is prepared\n@@ -569,7 +649,6 @@ enum ionic_txq_desc_opcode {\n * no further manipulation from device.\n *\n * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:\n- *\n * Offload 16-bit L4 checksum\n * calculation/insertion. The device will\n * calculate the L4 checksum value and\n@@ -578,14 +657,16 @@ enum ionic_txq_desc_opcode {\n * is calculated starting at @csum_start bytes\n * into the packet to the end of the packet.\n * The checksum insertion position is given\n- * in @csum_offset. This feature is only\n- * applicable to protocols such as TCP, UDP\n- * and ICMP where a standard (i.e. the\n- * 'IP-style' checksum) one's complement\n- * 16-bit checksum is used, using an IP\n- * pseudo-header to seed the calculation.\n- * Software will preload the L4 checksum\n- * field with the IP pseudo-header checksum.\n+ * in @csum_offset, which is the offset from\n+ * @csum_start to the checksum field in the L4\n+ * header. This feature is only applicable to\n+ * protocols such as TCP, UDP and ICMP where a\n+ * standard (i.e. the 'IP-style' checksum)\n+ * one's complement 16-bit checksum is used,\n+ * using an IP pseudo-header to seed the\n+ * calculation. Software will preload the L4\n+ * checksum field with the IP pseudo-header\n+ * checksum.\n *\n * For tunnel encapsulation, @csum_start and\n * @csum_offset refer to the inner L4\n@@ -597,11 +678,10 @@ enum ionic_txq_desc_opcode {\n * the @encap is set, the device will\n * offload the outer header checksums using\n * LCO (local checksum offload) (see\n- * Documentation/networking/checksum-\n- * offloads.txt for more info).\n+ * Documentation/networking/checksum-offloads.rst\n+ * for more info).\n *\n * IONIC_TXQ_DESC_OPCODE_CSUM_HW:\n- *\n * Offload 16-bit checksum computation to hardware.\n * If @csum_l3 is set then the packet's L3 checksum is\n * updated. Similarly, if @csum_l4 is set the the L4\n@@ -609,8 +689,7 @@ enum ionic_txq_desc_opcode {\n * checksums are also updated.\n *\n * IONIC_TXQ_DESC_OPCODE_TSO:\n- *\n- * Device performs TCP segmentation offload\n+ * Device preforms TCP segmentation offload\n * (TSO). @hdr_len is the number of bytes\n * to the end of TCP header (the offset to\n * the TCP payload). @mss is the desired\n@@ -636,40 +715,41 @@ enum ionic_txq_desc_opcode {\n * clear CWR in remaining segments.\n * @flags:\n * vlan:\n- * Insert an L2 VLAN header using @vlan_tci.\n+ * Insert an L2 VLAN header using @vlan_tci\n * encap:\n- * Calculate encap header checksum.\n+ * Calculate encap header checksum\n * csum_l3:\n- * Compute L3 header checksum.\n+ * Compute L3 header checksum\n * csum_l4:\n- * Compute L4 header checksum.\n+ * Compute L4 header checksum\n * tso_sot:\n * TSO start\n * tso_eot:\n * TSO end\n * @num_sg_elems: Number of scatter-gather elements in SG\n * descriptor\n- * @addr: First data buffer's DMA address.\n- * (Subsequent data buffers are on txq_sg_desc).\n+ * @addr: First data buffer's DMA address\n+ * (Subsequent data buffers are on txq_sg_desc)\n * @len: First data buffer's length, in bytes\n * @vlan_tci: VLAN tag to insert in the packet (if requested\n * by @V-bit). Includes .1p and .1q tags\n * @hdr_len: Length of packet headers, including\n- * encapsulating outer header, if applicable.\n- * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and\n- * TXQ_DESC_OPCODE_TSO. Should be set to zero for\n+ * encapsulating outer header, if applicable\n+ * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and\n+ * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for\n * all other modes. For\n- * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length\n+ * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length\n * of headers up to inner-most L4 header. For\n- * TXQ_DESC_OPCODE_TSO, @hdr_len is up to\n+ * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to\n * inner-most L4 payload, so inclusive of\n * inner-most L4 header.\n- * @mss: Desired MSS value for TSO. Only applicable for\n- * TXQ_DESC_OPCODE_TSO.\n- * @csum_start: Offset into inner-most L3 header of checksum\n- * @csum_offset: Offset into inner-most L4 header of checksum\n+ * @mss: Desired MSS value for TSO; only applicable for\n+ * IONIC_TXQ_DESC_OPCODE_TSO\n+ * @csum_start: Offset from packet to first byte checked in L4 checksum\n+ * @csum_offset: Offset from csum_start to L4 checksum field\n */\n-\n+struct ionic_txq_desc {\n+\t__le64 cmd;\n #define IONIC_TXQ_DESC_OPCODE_MASK\t\t0xf\n #define IONIC_TXQ_DESC_OPCODE_SHIFT\t\t4\n #define IONIC_TXQ_DESC_FLAGS_MASK\t\t0xf\n@@ -691,8 +771,6 @@ enum ionic_txq_desc_opcode {\n #define IONIC_TXQ_DESC_FLAG_TSO_SOT\t\t0x4\n #define IONIC_TXQ_DESC_FLAG_TSO_EOT\t\t0x8\n \n-struct ionic_txq_desc {\n-\t__le64 cmd;\n \t__le16 len;\n \tunion {\n \t\t__le16 vlan_tci;\n@@ -719,45 +797,60 @@ static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,\n \t\tIONIC_TXQ_DESC_OPCODE_SHIFT;\n \tcmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) <<\n \t\tIONIC_TXQ_DESC_FLAGS_SHIFT;\n-\tcmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;\n-\tcmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;\n+\tcmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) <<\n+\t\tIONIC_TXQ_DESC_NSGE_SHIFT;\n+\tcmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) <<\n+\t\tIONIC_TXQ_DESC_ADDR_SHIFT;\n \n \treturn cmd;\n };\n \n-static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,\n+static inline void\n+decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,\n \t\t\t\t u8 *nsge, u64 *addr)\n {\n \t*opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) &\n \t\tIONIC_TXQ_DESC_OPCODE_MASK;\n \t*flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) &\n \t\tIONIC_TXQ_DESC_FLAGS_MASK;\n-\t*nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;\n-\t*addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;\n+\t*nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) &\n+\t\tIONIC_TXQ_DESC_NSGE_MASK;\n+\t*addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) &\n+\t\tIONIC_TXQ_DESC_ADDR_MASK;\n };\n \n-#define IONIC_TX_MAX_SG_ELEMS\t8\n-#define IONIC_RX_MAX_SG_ELEMS\t8\n-\n /**\n- * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list\n+ * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element\n * @addr: DMA address of SG element data buffer\n * @len: Length of SG element data buffer, in bytes\n */\n+struct ionic_txq_sg_elem {\n+\t__le64 addr;\n+\t__le16 len;\n+\t__le16 rsvd[3];\n+};\n+\n+/**\n+ * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list\n+ * @elems: Scatter-gather elements\n+ */\n struct ionic_txq_sg_desc {\n-\tstruct ionic_txq_sg_elem {\n-\t\t__le64 addr;\n-\t\t__le16 len;\n-\t\t__le16 rsvd[3];\n-\t} elems[IONIC_TX_MAX_SG_ELEMS];\n+#define IONIC_TX_MAX_SG_ELEMS\t\t8\n+#define IONIC_TX_SG_DESC_STRIDE\t\t8\n+\tstruct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];\n+};\n+\n+struct ionic_txq_sg_desc_v1 {\n+#define IONIC_TX_MAX_SG_ELEMS_V1\t\t15\n+#define IONIC_TX_SG_DESC_STRIDE_V1\t\t16\n+\tstruct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];\n };\n \n /**\n * struct ionic_txq_comp - Ethernet transmit queue completion descriptor\n- * @status: The status of the command (enum status_code)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n- * @color: Color bit.\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @color: Color bit\n */\n struct ionic_txq_comp {\n \tu8 status;\n@@ -774,16 +867,15 @@ enum ionic_rxq_desc_opcode {\n \n /**\n * struct ionic_rxq_desc - Ethernet Rx queue descriptor format\n- * @opcode: Rx operation, see RXQ_DESC_OPCODE_*:\n- *\n- * RXQ_DESC_OPCODE_SIMPLE:\n+ * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:\n *\n+ * IONIC_RXQ_DESC_OPCODE_SIMPLE:\n * Receive full packet into data buffer\n * starting at @addr. Results of\n * receive, including actual bytes received,\n * are recorded in Rx completion descriptor.\n *\n- * @len: Data buffer's length, in bytes.\n+ * @len: Data buffer's length, in bytes\n * @addr: Data buffer's DMA address\n */\n struct ionic_rxq_desc {\n@@ -794,26 +886,33 @@ struct ionic_rxq_desc {\n };\n \n /**\n- * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list\n+ * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element\n * @addr: DMA address of SG element data buffer\n * @len: Length of SG element data buffer, in bytes\n */\n+struct ionic_rxq_sg_elem {\n+\t__le64 addr;\n+\t__le16 len;\n+\t__le16 rsvd[3];\n+};\n+\n+/**\n+ * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list\n+ * @elems: Scatter-gather elements\n+ */\n struct ionic_rxq_sg_desc {\n-\tstruct ionic_rxq_sg_elem {\n-\t\t__le64 addr;\n-\t\t__le16 len;\n-\t\t__le16 rsvd[3];\n-\t} elems[IONIC_RX_MAX_SG_ELEMS];\n+#define IONIC_RX_MAX_SG_ELEMS\t\t8\n+#define IONIC_RX_SG_DESC_STRIDE\t\t8\n+\tstruct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];\n };\n \n /**\n * struct ionic_rxq_comp - Ethernet receive queue completion descriptor\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @num_sg_elems: Number of SG elements used by this descriptor\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n * @rss_hash: 32-bit RSS hash\n- * @csum: 16-bit sum of the packet's L2 payload.\n+ * @csum: 16-bit sum of the packet's L2 payload\n * If the packet's L2 payload is odd length, an extra\n * zero-value byte is included in the @csum calculation but\n * not included in @len.\n@@ -821,33 +920,51 @@ struct ionic_rxq_sg_desc {\n * set. Includes .1p and .1q tags.\n * @len: Received packet length, in bytes. Excludes FCS.\n * @csum_calc L2 payload checksum is computed or not\n- * @csum_tcp_ok: The TCP checksum calculated by the device\n- * matched the checksum in the receive packet's\n- * TCP header\n- * @csum_tcp_bad: The TCP checksum calculated by the device did\n- * not match the checksum in the receive packet's\n- * TCP header.\n- * @csum_udp_ok: The UDP checksum calculated by the device\n- * matched the checksum in the receive packet's\n- * UDP header\n- * @csum_udp_bad: The UDP checksum calculated by the device did\n- * not match the checksum in the receive packet's\n- * UDP header.\n- * @csum_ip_ok: The IPv4 checksum calculated by the device\n- * matched the checksum in the receive packet's\n- * first IPv4 header. If the receive packet\n- * contains both a tunnel IPv4 header and a\n- * transport IPv4 header, the device validates the\n- * checksum for the both IPv4 headers.\n- * @csum_ip_bad: The IPv4 checksum calculated by the device did\n- * not match the checksum in the receive packet's\n- * first IPv4 header. If the receive packet\n- * contains both a tunnel IPv4 header and a\n- * transport IPv4 header, the device validates the\n- * checksum for both IP headers.\n- * @VLAN: VLAN header was stripped and placed in @vlan_tci.\n- * @pkt_type: Packet type\n- * @color: Color bit.\n+ * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_TCP_OK:\n+ * The TCP checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * TCP header.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:\n+ * The TCP checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * TCP header.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_UDP_OK:\n+ * The UDP checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * UDP header\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:\n+ * The UDP checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * UDP header.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_IP_OK:\n+ * The IPv4 checksum calculated by the device\n+ * matched the checksum in the receive packet's\n+ * first IPv4 header. If the receive packet\n+ * contains both a tunnel IPv4 header and a\n+ * transport IPv4 header, the device validates the\n+ * checksum for the both IPv4 headers.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_IP_BAD:\n+ * The IPv4 checksum calculated by the device did\n+ * not match the checksum in the receive packet's\n+ * first IPv4 header. If the receive packet\n+ * contains both a tunnel IPv4 header and a\n+ * transport IPv4 header, the device validates the\n+ * checksum for both IP headers.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_VLAN:\n+ * The VLAN header was stripped and placed in @vlan_tci.\n+ *\n+ * IONIC_RXQ_COMP_CSUM_F_CALC:\n+ * The checksum was calculated by the device.\n+ *\n+ * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK\n */\n struct ionic_rxq_comp {\n \tu8 status;\n@@ -871,13 +988,21 @@ struct ionic_rxq_comp {\n };\n \n enum ionic_pkt_type {\n-\tIONIC_PKT_TYPE_NON_IP = 0x000,\n-\tIONIC_PKT_TYPE_IPV4 = 0x001,\n-\tIONIC_PKT_TYPE_IPV4_TCP = 0x003,\n-\tIONIC_PKT_TYPE_IPV4_UDP = 0x005,\n-\tIONIC_PKT_TYPE_IPV6 = 0x008,\n-\tIONIC_PKT_TYPE_IPV6_TCP = 0x018,\n-\tIONIC_PKT_TYPE_IPV6_UDP = 0x028,\n+\tIONIC_PKT_TYPE_NON_IP\t\t= 0x00,\n+\tIONIC_PKT_TYPE_IPV4\t\t= 0x01,\n+\tIONIC_PKT_TYPE_IPV4_TCP\t\t= 0x03,\n+\tIONIC_PKT_TYPE_IPV4_UDP\t\t= 0x05,\n+\tIONIC_PKT_TYPE_IPV6\t\t= 0x08,\n+\tIONIC_PKT_TYPE_IPV6_TCP\t\t= 0x18,\n+\tIONIC_PKT_TYPE_IPV6_UDP\t\t= 0x28,\n+\t/* below types are only used if encap offloads are enabled on lif */\n+\tIONIC_PKT_TYPE_ENCAP_NON_IP\t= 0x40,\n+\tIONIC_PKT_TYPE_ENCAP_IPV4\t= 0x41,\n+\tIONIC_PKT_TYPE_ENCAP_IPV4_TCP\t= 0x43,\n+\tIONIC_PKT_TYPE_ENCAP_IPV4_UDP\t= 0x45,\n+\tIONIC_PKT_TYPE_ENCAP_IPV6\t= 0x48,\n+\tIONIC_PKT_TYPE_ENCAP_IPV6_TCP\t= 0x58,\n+\tIONIC_PKT_TYPE_ENCAP_IPV6_UDP\t= 0x68,\n };\n \n enum ionic_eth_hw_features {\n@@ -894,10 +1019,13 @@ enum ionic_eth_hw_features {\n \tIONIC_ETH_HW_TSO_ECN\t\t= BIT(10),\n \tIONIC_ETH_HW_TSO_GRE\t\t= BIT(11),\n \tIONIC_ETH_HW_TSO_GRE_CSUM\t= BIT(12),\n-\tIONIC_ETH_HW_TSO_IPXIP4\t= BIT(13),\n-\tIONIC_ETH_HW_TSO_IPXIP6\t= BIT(14),\n+\tIONIC_ETH_HW_TSO_IPXIP4\t\t= BIT(13),\n+\tIONIC_ETH_HW_TSO_IPXIP6\t\t= BIT(14),\n \tIONIC_ETH_HW_TSO_UDP\t\t= BIT(15),\n \tIONIC_ETH_HW_TSO_UDP_CSUM\t= BIT(16),\n+\tIONIC_ETH_HW_RX_CSUM_GENEVE\t= BIT(17),\n+\tIONIC_ETH_HW_TX_CSUM_GENEVE\t= BIT(18),\n+\tIONIC_ETH_HW_TSO_GENEVE\t\t= BIT(19)\n };\n \n /**\n@@ -906,7 +1034,7 @@ enum ionic_eth_hw_features {\n * @type: Queue type\n * @lif_index: LIF index\n * @index: Queue index\n- * @oper: Operation (enum q_control_oper)\n+ * @oper: Operation (enum ionic_q_control_oper)\n */\n struct ionic_q_control_cmd {\n \tu8 opcode;\n@@ -919,14 +1047,17 @@ struct ionic_q_control_cmd {\n \n typedef struct ionic_admin_comp ionic_q_control_comp;\n \n-enum q_control_oper {\n+enum ionic_q_control_oper {\n \tIONIC_Q_DISABLE\t\t= 0,\n \tIONIC_Q_ENABLE\t\t= 1,\n \tIONIC_Q_HANG_RESET\t= 2,\n };\n \n /**\n- * Physical connection type\n+ * enum ionic_phy_type - Physical connection type\n+ * @IONIC_PHY_TYPE_NONE: No PHY installed\n+ * @IONIC_PHY_TYPE_COPPER: Copper PHY\n+ * @IONIC_PHY_TYPE_FIBER: Fiber PHY\n */\n enum ionic_phy_type {\n \tIONIC_PHY_TYPE_NONE\t= 0,\n@@ -935,18 +1066,23 @@ enum ionic_phy_type {\n };\n \n /**\n- * Transceiver status\n+ * enum ionic_xcvr_state - Transceiver status\n+ * @IONIC_XCVR_STATE_REMOVED: Transceiver removed\n+ * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted\n+ * @IONIC_XCVR_STATE_PENDING: Transceiver pending\n+ * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read\n+ * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error\n */\n enum ionic_xcvr_state {\n \tIONIC_XCVR_STATE_REMOVED\t = 0,\n \tIONIC_XCVR_STATE_INSERTED\t = 1,\n \tIONIC_XCVR_STATE_PENDING\t = 2,\n \tIONIC_XCVR_STATE_SPROM_READ\t = 3,\n-\tIONIC_XCVR_STATE_SPROM_READ_ERR = 4,\n+\tIONIC_XCVR_STATE_SPROM_READ_ERR\t = 4,\n };\n \n /**\n- * Supported link modes\n+ * enum ionic_xcvr_pid - Supported link modes\n */\n enum ionic_xcvr_pid {\n \tIONIC_XCVR_PID_UNKNOWN = 0,\n@@ -980,67 +1116,74 @@ enum ionic_xcvr_pid {\n \tIONIC_XCVR_PID_SFP_10GBASE_CU = 68,\n \tIONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,\n \tIONIC_XCVR_PID_QSFP_100G_PSM4 = 70,\n+\tIONIC_XCVR_PID_SFP_25GBASE_ACC = 71,\n };\n \n /**\n- * Port types\n- */\n-enum ionic_port_type {\n-\tIONIC_PORT_TYPE_NONE = 0, /* port type not configured */\n-\tIONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */\n-\tIONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */\n-};\n-\n-/**\n- * Port config state\n+ * enum ionic_port_admin_state - Port config state\n+ * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured\n+ * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled\n+ * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled\n */\n enum ionic_port_admin_state {\n-\tIONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */\n-\tIONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */\n-\tIONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */\n+\tIONIC_PORT_ADMIN_STATE_NONE = 0,\n+\tIONIC_PORT_ADMIN_STATE_DOWN = 1,\n+\tIONIC_PORT_ADMIN_STATE_UP = 2,\n };\n \n /**\n- * Port operational status\n+ * enum ionic_port_oper_status - Port operational status\n+ * @IONIC_PORT_OPER_STATUS_NONE: Port disabled\n+ * @IONIC_PORT_OPER_STATUS_UP: Port link status up\n+ * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down\n */\n enum ionic_port_oper_status {\n-\tIONIC_PORT_OPER_STATUS_NONE = 0,\t/* port is disabled */\n-\tIONIC_PORT_OPER_STATUS_UP = 1,\t/* port is linked up */\n-\tIONIC_PORT_OPER_STATUS_DOWN = 2,\t/* port link status is down */\n+\tIONIC_PORT_OPER_STATUS_NONE = 0,\n+\tIONIC_PORT_OPER_STATUS_UP = 1,\n+\tIONIC_PORT_OPER_STATUS_DOWN = 2,\n };\n \n /**\n- * Ethernet Forward error correction (fec) modes\n+ * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes\n+ * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled\n+ * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC\n+ * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC\n */\n enum ionic_port_fec_type {\n-\tIONIC_PORT_FEC_TYPE_NONE = 0,\t\t/* Disabled */\n-\tIONIC_PORT_FEC_TYPE_FC = 1,\t\t/* FireCode */\n-\tIONIC_PORT_FEC_TYPE_RS = 2,\t\t/* ReedSolomon */\n+\tIONIC_PORT_FEC_TYPE_NONE = 0,\n+\tIONIC_PORT_FEC_TYPE_FC = 1,\n+\tIONIC_PORT_FEC_TYPE_RS = 2,\n };\n \n /**\n- * Ethernet pause (flow control) modes\n+ * enum ionic_port_pause_type - Ethernet pause (flow control) modes\n+ * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause\n+ * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause\n+ * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control\n */\n enum ionic_port_pause_type {\n-\tIONIC_PORT_PAUSE_TYPE_NONE = 0,\t/* Disable Pause */\n-\tIONIC_PORT_PAUSE_TYPE_LINK = 1,\t/* Link level pause */\n-\tIONIC_PORT_PAUSE_TYPE_PFC = 2,\t/* Priority-Flow control */\n+\tIONIC_PORT_PAUSE_TYPE_NONE = 0,\n+\tIONIC_PORT_PAUSE_TYPE_LINK = 1,\n+\tIONIC_PORT_PAUSE_TYPE_PFC = 2,\n };\n \n /**\n- * Loopback modes\n+ * enum ionic_port_loopback_mode - Loopback modes\n+ * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback\n+ * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback\n+ * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback\n */\n enum ionic_port_loopback_mode {\n-\tIONIC_PORT_LOOPBACK_MODE_NONE = 0,\t/* Disable loopback */\n-\tIONIC_PORT_LOOPBACK_MODE_MAC = 1,\t/* MAC loopback */\n-\tIONIC_PORT_LOOPBACK_MODE_PHY = 2,\t/* PHY/Serdes loopback */\n+\tIONIC_PORT_LOOPBACK_MODE_NONE = 0,\n+\tIONIC_PORT_LOOPBACK_MODE_MAC = 1,\n+\tIONIC_PORT_LOOPBACK_MODE_PHY = 2,\n };\n \n /**\n- * Transceiver Status information\n+ * struct ionic_xcvr_status - Transceiver Status information\n * @state: Transceiver status (enum ionic_xcvr_state)\n * @phy: Physical connection type (enum ionic_phy_type)\n- * @pid: Transceiver link mode (enum pid)\n+ * @pid: Transceiver link mode (enum ionic_xcvr_pid)\n * @sprom: Transceiver sprom contents\n */\n struct ionic_xcvr_status {\n@@ -1051,10 +1194,10 @@ struct ionic_xcvr_status {\n };\n \n /**\n- * Port configuration\n+ * union ionic_port_config - Port configuration\n * @speed: port speed (in Mbps)\n * @mtu: mtu\n- * @state: port admin state (enum port_admin_state)\n+ * @state: port admin state (enum ionic_port_admin_state)\n * @an_enable: autoneg enable\n * @fec_type: fec type (enum ionic_port_fec_type)\n * @pause_type: pause type (enum ionic_port_pause_type)\n@@ -1084,19 +1227,23 @@ union ionic_port_config {\n };\n \n /**\n- * Port Status information\n+ * struct ionic_port_status - Port Status information\n * @status: link status (enum ionic_port_oper_status)\n * @id: port id\n * @speed: link speed (in Mbps)\n- * @xcvr: transceiver status\n+ * @link_down_count: number of times link went from up to down\n+ * @fec_type: fec type (enum ionic_port_fec_type)\n+ * @xcvr: tranceiver status\n */\n struct ionic_port_status {\n \t__le32 id;\n \t__le32 speed;\n \tu8 status;\n-\tu8 rsvd[51];\n+\t__le16 link_down_count;\n+\tu8 fec_type;\n+\tu8 rsvd[48];\n \tstruct ionic_xcvr_status xcvr;\n-};\n+} __rte_packed;\n \n /**\n * struct ionic_port_identify_cmd - Port identify command\n@@ -1113,7 +1260,7 @@ struct ionic_port_identify_cmd {\n \n /**\n * struct ionic_port_identify_comp - Port identify command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @ver: Version of identify returned by device\n */\n struct ionic_port_identify_comp {\n@@ -1138,7 +1285,7 @@ struct ionic_port_init_cmd {\n \n /**\n * struct ionic_port_init_comp - Port initialization command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n */\n struct ionic_port_init_comp {\n \tu8 status;\n@@ -1158,7 +1305,7 @@ struct ionic_port_reset_cmd {\n \n /**\n * struct ionic_port_reset_comp - Port reset command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n */\n struct ionic_port_reset_comp {\n \tu8 status;\n@@ -1166,15 +1313,23 @@ struct ionic_port_reset_comp {\n };\n \n /**\n- * enum stats_ctl_cmd - List of commands for stats control\n+ * enum ionic_stats_ctl_cmd - List of commands for stats control\n+ * @IONIC_STATS_CTL_RESET: Reset statistics\n */\n enum ionic_stats_ctl_cmd {\n \tIONIC_STATS_CTL_RESET\t\t= 0,\n };\n \n-\n /**\n * enum ionic_port_attr - List of device attributes\n+ * @IONIC_PORT_ATTR_STATE: Port state attribute\n+ * @IONIC_PORT_ATTR_SPEED: Port speed attribute\n+ * @IONIC_PORT_ATTR_MTU: Port MTU attribute\n+ * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute\n+ * @IONIC_PORT_ATTR_FEC: Port FEC attribute\n+ * @IONIC_PORT_ATTR_PAUSE: Port pause attribute\n+ * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute\n+ * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute\n */\n enum ionic_port_attr {\n \tIONIC_PORT_ATTR_STATE\t\t= 0,\n@@ -1189,9 +1344,17 @@ enum ionic_port_attr {\n \n /**\n * struct ionic_port_setattr_cmd - Set port attributes on the NIC\n- * @opcode: Opcode\n- * @index: port index\n- * @attr: Attribute type (enum ionic_port_attr)\n+ * @opcode: Opcode\n+ * @index: Port index\n+ * @attr: Attribute type (enum ionic_port_attr)\n+ * @state: Port state\n+ * @speed: Port speed\n+ * @mtu: Port MTU\n+ * @an_enable: Port autonegotiation setting\n+ * @fec_type: Port FEC type setting\n+ * @pause_type: Port pause type setting\n+ * @loopback_mode: Port loopback mode\n+ * @stats_ctl: Port stats setting\n */\n struct ionic_port_setattr_cmd {\n \tu8 opcode;\n@@ -1206,14 +1369,14 @@ struct ionic_port_setattr_cmd {\n \t\tu8 fec_type;\n \t\tu8 pause_type;\n \t\tu8 loopback_mode;\n-\t\tu8\tstats_ctl;\n+\t\tu8 stats_ctl;\n \t\tu8 rsvd2[60];\n \t};\n };\n \n /**\n * struct ionic_port_setattr_comp - Port set attr command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @color: Color bit\n */\n struct ionic_port_setattr_comp {\n@@ -1237,8 +1400,15 @@ struct ionic_port_getattr_cmd {\n \n /**\n * struct ionic_port_getattr_comp - Port get attr command completion\n- * @status: The status of the command (enum status_code)\n- * @color: Color bit\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @state: Port state\n+ * @speed: Port speed\n+ * @mtu: Port MTU\n+ * @an_enable: Port autonegotiation setting\n+ * @fec_type: Port FEC type setting\n+ * @pause_type: Port pause type setting\n+ * @loopback_mode: Port loopback mode\n+ * @color: Color bit\n */\n struct ionic_port_getattr_comp {\n \tu8 status;\n@@ -1252,17 +1422,17 @@ struct ionic_port_getattr_comp {\n \t\tu8 pause_type;\n \t\tu8 loopback_mode;\n \t\tu8 rsvd2[11];\n-\t};\n+\t} __rte_packed;\n \tu8 color;\n };\n \n /**\n- * struct ionic_lif_status - Lif status register\n+ * struct ionic_lif_status - LIF status register\n * @eid: most recent NotifyQ event id\n- * @port_num: port the lif is connected to\n+ * @port_num: port the LIF is connected to\n * @link_status: port status (enum ionic_port_oper_status)\n * @link_speed: speed of link in Mbps\n- * @link_down_count: number of times link status changes\n+ * @link_down_count: number of times link went from up to down\n */\n struct ionic_lif_status {\n \t__le64 eid;\n@@ -1296,6 +1466,9 @@ enum ionic_dev_state {\n \n /**\n * enum ionic_dev_attr - List of device attributes\n+ * @IONIC_DEV_ATTR_STATE: Device state attribute\n+ * @IONIC_DEV_ATTR_NAME: Device name attribute\n+ * @IONIC_DEV_ATTR_FEATURES: Device feature attributes\n */\n enum ionic_dev_attr {\n \tIONIC_DEV_ATTR_STATE = 0,\n@@ -1320,12 +1493,12 @@ struct ionic_dev_setattr_cmd {\n \t\tchar name[IONIC_IFNAMSIZ];\n \t\t__le64 features;\n \t\tu8 rsvd2[60];\n-\t};\n+\t} __rte_packed;\n };\n \n /**\n * struct ionic_dev_setattr_comp - Device set attr command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @features: Device features\n * @color: Color bit\n */\n@@ -1335,7 +1508,7 @@ struct ionic_dev_setattr_comp {\n \tunion {\n \t\t__le64 features;\n \t\tu8 rsvd2[11];\n-\t};\n+\t} __rte_packed;\n \tu8 color;\n };\n \n@@ -1352,7 +1525,7 @@ struct ionic_dev_getattr_cmd {\n \n /**\n * struct ionic_dev_setattr_comp - Device set attr command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @features: Device features\n * @color: Color bit\n */\n@@ -1362,7 +1535,7 @@ struct ionic_dev_getattr_comp {\n \tunion {\n \t\t__le64 features;\n \t\tu8 rsvd2[11];\n-\t};\n+\t} __rte_packed;\n \tu8 color;\n };\n \n@@ -1382,6 +1555,13 @@ enum ionic_rss_hash_types {\n \n /**\n * enum ionic_lif_attr - List of LIF attributes\n+ * @IONIC_LIF_ATTR_STATE: LIF state attribute\n+ * @IONIC_LIF_ATTR_NAME: LIF name attribute\n+ * @IONIC_LIF_ATTR_MTU: LIF MTU attribute\n+ * @IONIC_LIF_ATTR_MAC: LIF MAC attribute\n+ * @IONIC_LIF_ATTR_FEATURES: LIF features attribute\n+ * @IONIC_LIF_ATTR_RSS: LIF RSS attribute\n+ * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute\n */\n enum ionic_lif_attr {\n \tIONIC_LIF_ATTR_STATE = 0,\n@@ -1396,18 +1576,18 @@ enum ionic_lif_attr {\n /**\n * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC\n * @opcode: Opcode\n- * @type: Attribute type (enum ionic_lif_attr)\n+ * @attr: Attribute type (enum ionic_lif_attr)\n * @index: LIF index\n- * @state: lif state (enum lif_state)\n+ * @state: LIF state (enum ionic_lif_state)\n * @name: The netdev name string, 0 terminated\n * @mtu: Mtu\n * @mac: Station mac\n * @features: Features (enum ionic_eth_hw_features)\n * @rss: RSS properties\n- * @types: The hash types to enable (see rss_hash_types).\n- * @key: The hash secret key.\n- * @addr: Address for the indirection table shared memory.\n- * @stats_ctl: stats control commands (enum stats_ctl_cmd)\n+ * @types: The hash types to enable (see rss_hash_types)\n+ * @key: The hash secret key\n+ * @addr: Address for the indirection table shared memory\n+ * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)\n */\n struct ionic_lif_setattr_cmd {\n \tu8 opcode;\n@@ -1425,16 +1605,15 @@ struct ionic_lif_setattr_cmd {\n \t\t\tu8 rsvd[6];\n \t\t\t__le64 addr;\n \t\t} rss;\n-\t\tu8\tstats_ctl;\n+\t\tu8 stats_ctl;\n \t\tu8 rsvd[60];\n-\t};\n+\t} __rte_packed;\n };\n \n /**\n * struct ionic_lif_setattr_comp - LIF set attr command completion\n- * @status: The status of the command (enum status_code)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n * @features: features (enum ionic_eth_hw_features)\n * @color: Color bit\n */\n@@ -1445,7 +1624,7 @@ struct ionic_lif_setattr_comp {\n \tunion {\n \t\t__le64 features;\n \t\tu8 rsvd2[11];\n-\t};\n+\t} __rte_packed;\n \tu8 color;\n };\n \n@@ -1464,10 +1643,9 @@ struct ionic_lif_getattr_cmd {\n \n /**\n * struct ionic_lif_getattr_comp - LIF get attr command completion\n- * @status: The status of the command (enum status_code)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n- * @state: lif state (enum lif_state)\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @state: LIF state (enum ionic_lif_state)\n * @name: The netdev name string, 0 terminated\n * @mtu: Mtu\n * @mac: Station mac\n@@ -1484,16 +1662,17 @@ struct ionic_lif_getattr_comp {\n \t\tu8 mac[6];\n \t\t__le64 features;\n \t\tu8 rsvd2[11];\n-\t};\n+\t} __rte_packed;\n \tu8 color;\n };\n \n enum ionic_rx_mode {\n-\tIONIC_RX_MODE_F_UNICAST = BIT(0),\n-\tIONIC_RX_MODE_F_MULTICAST = BIT(1),\n-\tIONIC_RX_MODE_F_BROADCAST = BIT(2),\n-\tIONIC_RX_MODE_F_PROMISC = BIT(3),\n-\tIONIC_RX_MODE_F_ALLMULTI = BIT(4),\n+\tIONIC_RX_MODE_F_UNICAST\t\t= BIT(0),\n+\tIONIC_RX_MODE_F_MULTICAST\t= BIT(1),\n+\tIONIC_RX_MODE_F_BROADCAST\t= BIT(2),\n+\tIONIC_RX_MODE_F_PROMISC\t\t= BIT(3),\n+\tIONIC_RX_MODE_F_ALLMULTI\t= BIT(4),\n+\tIONIC_RX_MODE_F_RDMA_SNIFFER\t= BIT(5),\n };\n \n /**\n@@ -1501,11 +1680,12 @@ enum ionic_rx_mode {\n * @opcode: opcode\n * @lif_index: LIF index\n * @rx_mode: Rx mode flags:\n- * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets.\n- * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets.\n- * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets.\n- * IONIC_RX_MODE_F_PROMISC: Accept any packets.\n- * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets.\n+ * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets\n+ * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets\n+ * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets\n+ * IONIC_RX_MODE_F_PROMISC: Accept any packets\n+ * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets\n+ * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets\n */\n struct ionic_rx_mode_set_cmd {\n \tu8 opcode;\n@@ -1529,9 +1709,14 @@ enum ionic_rx_filter_match_type {\n * @qtype: Queue type\n * @lif_index: LIF index\n * @qid: Queue ID\n- * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx)\n- * @vlan: VLAN ID\n- * @addr: MAC address (network-byte order)\n+ * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)\n+ * @vlan: VLAN filter\n+ * @vlan: VLAN ID\n+ * @mac: MAC filter\n+ * @addr: MAC address (network-byte order)\n+ * @mac_vlan: MACVLAN filter\n+ * @vlan: VLAN ID\n+ * @addr: MAC address (network-byte order)\n */\n struct ionic_rx_filter_add_cmd {\n \tu8 opcode;\n@@ -1556,11 +1741,10 @@ struct ionic_rx_filter_add_cmd {\n \n /**\n * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion\n- * @status: The status of the command (enum status_code)\n- * @comp_index: The index in the descriptor ring for which this\n- * is the completion.\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n * @filter_id: Filter ID\n- * @color: Color bit.\n+ * @color: Color bit\n */\n struct ionic_rx_filter_add_comp {\n \tu8 status;\n@@ -1587,9 +1771,99 @@ struct ionic_rx_filter_del_cmd {\n \n typedef struct ionic_admin_comp ionic_rx_filter_del_comp;\n \n+enum ionic_vf_attr {\n+\tIONIC_VF_ATTR_SPOOFCHK\t= 1,\n+\tIONIC_VF_ATTR_TRUST\t= 2,\n+\tIONIC_VF_ATTR_MAC\t= 3,\n+\tIONIC_VF_ATTR_LINKSTATE\t= 4,\n+\tIONIC_VF_ATTR_VLAN\t= 5,\n+\tIONIC_VF_ATTR_RATE\t= 6,\n+\tIONIC_VF_ATTR_STATSADDR\t= 7,\n+};\n+\n+/**\n+ * enum ionic_vf_link_status - Virtual Function link status\n+ * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink\n+ * @IONIC_VF_LINK_STATUS_UP: Link always up\n+ * @IONIC_VF_LINK_STATUS_DOWN: Link always down\n+ */\n+enum ionic_vf_link_status {\n+\tIONIC_VF_LINK_STATUS_AUTO = 0,\n+\tIONIC_VF_LINK_STATUS_UP = 1,\n+\tIONIC_VF_LINK_STATUS_DOWN = 2,\n+};\n+\n+/**\n+ * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC\n+ * @opcode: Opcode\n+ * @attr: Attribute type (enum ionic_vf_attr)\n+ * @vf_index: VF index\n+ *\t@macaddr:\tmac address\n+ *\t@vlanid:\tvlan ID\n+ *\t@maxrate:\tmax Tx rate in Mbps\n+ *\t@spoofchk:\tenable address spoof checking\n+ *\t@trust:\t\tenable VF trust\n+ *\t@linkstate:\tset link up or down\n+ *\t@stats_pa:\tset DMA address for VF stats\n+ */\n+struct ionic_vf_setattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 vf_index;\n+\tunion {\n+\t\tu8 macaddr[6];\n+\t\t__le16 vlanid;\n+\t\t__le32 maxrate;\n+\t\tu8 spoofchk;\n+\t\tu8 trust;\n+\t\tu8 linkstate;\n+\t\t__le64 stats_pa;\n+\t\tu8 pad[60];\n+\t} __rte_packed;\n+};\n+\n+struct ionic_vf_setattr_comp {\n+\tu8 status;\n+\tu8 attr;\n+\t__le16 vf_index;\n+\t__le16 comp_index;\n+\tu8 rsvd[9];\n+\tu8 color;\n+};\n+\n+/**\n+ * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC\n+ * @opcode: Opcode\n+ * @attr: Attribute type (enum ionic_vf_attr)\n+ * @vf_index: VF index\n+ */\n+struct ionic_vf_getattr_cmd {\n+\tu8 opcode;\n+\tu8 attr;\n+\t__le16 vf_index;\n+\tu8 rsvd[60];\n+};\n+\n+struct ionic_vf_getattr_comp {\n+\tu8 status;\n+\tu8 attr;\n+\t__le16 vf_index;\n+\tunion {\n+\t\tu8 macaddr[6];\n+\t\t__le16 vlanid;\n+\t\t__le32 maxrate;\n+\t\tu8 spoofchk;\n+\t\tu8 trust;\n+\t\tu8 linkstate;\n+\t\t__le64 stats_pa;\n+\t\tu8 pad[11];\n+\t} __rte_packed;\n+\tu8 color;\n+};\n+\n /**\n * struct ionic_qos_identify_cmd - QoS identify command\n- * @opcode: opcode\n+ * @opcode: opcode\n * @ver: Highest version of identify supported by driver\n *\n */\n@@ -1601,7 +1875,7 @@ struct ionic_qos_identify_cmd {\n \n /**\n * struct ionic_qos_identify_comp - QoS identify command completion\n- * @status: The status of the command (enum status_code)\n+ * @status: Status of the command (enum ionic_status_code)\n * @ver: Version of identify returned by device\n */\n struct ionic_qos_identify_comp {\n@@ -1610,9 +1884,15 @@ struct ionic_qos_identify_comp {\n \tu8 rsvd[14];\n };\n \n+#define IONIC_QOS_TC_MAX\t\t8\n+#define IONIC_QOS_ALL_TC\t\t0xFF\n+/* Capri max supported, should be renamed. */\n #define IONIC_QOS_CLASS_MAX\t\t7\n-#define IONIC_QOS_CLASS_NAME_SZ\t\t32\n-#define IONIC_QOS_DSCP_MAX_VALUES\t64\n+#define IONIC_QOS_PCP_MAX\t\t8\n+#define IONIC_QOS_CLASS_NAME_SZ\t32\n+#define IONIC_QOS_DSCP_MAX\t\t64\n+#define IONIC_QOS_ALL_PCP\t\t0xFF\n+#define IONIC_DSCP_BLOCK_SIZE\t\t8\n \n /**\n * enum ionic_qos_class\n@@ -1629,42 +1909,44 @@ enum ionic_qos_class {\n \n /**\n * enum ionic_qos_class_type - Traffic classification criteria\n+ * @IONIC_QOS_CLASS_TYPE_NONE: No QoS\n+ * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP\n+ * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP\n */\n enum ionic_qos_class_type {\n \tIONIC_QOS_CLASS_TYPE_NONE\t= 0,\n-\tIONIC_QOS_CLASS_TYPE_PCP\t= 1,\t/* Dot1Q pcp */\n-\tIONIC_QOS_CLASS_TYPE_DSCP\t= 2,\t/* IP dscp */\n+\tIONIC_QOS_CLASS_TYPE_PCP\t= 1,\n+\tIONIC_QOS_CLASS_TYPE_DSCP\t= 2,\n };\n \n /**\n- * enum ionic_qos_sched_type - Qos class scheduling type\n+ * enum ionic_qos_sched_type - QoS class scheduling type\n+ * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority\n+ * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin\n */\n enum ionic_qos_sched_type {\n-\t/* Strict priority */\n \tIONIC_QOS_SCHED_TYPE_STRICT\t= 0,\n-\t/* Deficit weighted round-robin */\n \tIONIC_QOS_SCHED_TYPE_DWRR\t= 1,\n };\n \n /**\n- * union ionic_qos_config - Qos configuration structure\n+ * union ionic_qos_config - QoS configuration structure\n * @flags:\t\tConfiguration flags\n *\tIONIC_QOS_CONFIG_F_ENABLE\t\tenable\n- *\tIONIC_QOS_CONFIG_F_DROP\t\t\tdrop/nodrop\n+ *\tIONIC_QOS_CONFIG_F_NO_DROP\t\tdrop/nodrop\n *\tIONIC_QOS_CONFIG_F_RW_DOT1Q_PCP\t\tenable dot1q pcp rewrite\n *\tIONIC_QOS_CONFIG_F_RW_IP_DSCP\t\tenable ip dscp rewrite\n- * @sched_type:\t\tQos class scheduling type (enum ionic_qos_sched_type)\n- * @class_type:\t\tQos class type (enum ionic_qos_class_type)\n- * @pause_type:\t\tQos pause type (enum qos_pause_type)\n- * @name:\t\tQos class name\n+ *\tIONIC_QOS_CONFIG_F_NON_DISRUPTIVE\tNon-disruptive TC update\n+ * @sched_type:\t\tQoS class scheduling type (enum ionic_qos_sched_type)\n+ * @class_type:\t\tQoS class type (enum ionic_qos_class_type)\n+ * @pause_type:\t\tQoS pause type (enum ionic_qos_pause_type)\n+ * @name:\t\tQoS class name\n * @mtu:\t\tMTU of the class\n- * @pfc_dot1q_pcp:\tPcp value for pause frames (valid iff F_NODROP)\n- * @dwrr_weight:\tQos class scheduling weight\n+ * @pfc_cos:\t\tPriority-Flow Control class of service\n+ * @dwrr_weight:\tQoS class scheduling weight\n * @strict_rlmt:\tRate limit for strict priority scheduling\n- * @rw_dot1q_pcp:\tRewrite dot1q pcp to this value\n- *\t\t\t(valid iff F_RW_DOT1Q_PCP)\n- * @rw_ip_dscp:\t\tRewrite ip dscp to this value\n- *\t\t\t(valid iff F_RW_IP_DSCP)\n+ * @rw_dot1q_pcp:\tRewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP)\n+ * @rw_ip_dscp:\t\tRewrite ip dscp to value (valid iff F_RW_IP_DSCP)\n * @dot1q_pcp:\t\tDot1q pcp value\n * @ndscp:\t\tNumber of valid dscp values in the ip_dscp field\n * @ip_dscp:\t\tIP dscp values\n@@ -1672,9 +1954,12 @@ enum ionic_qos_sched_type {\n union ionic_qos_config {\n \tstruct {\n #define IONIC_QOS_CONFIG_F_ENABLE\t\tBIT(0)\n-#define IONIC_QOS_CONFIG_F_DROP\t\t\tBIT(1)\n+#define IONIC_QOS_CONFIG_F_NO_DROP\t\tBIT(1)\n+/* Used to rewrite PCP or DSCP value. */\n #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP\t\tBIT(2)\n #define IONIC_QOS_CONFIG_F_RW_IP_DSCP\t\tBIT(3)\n+/* Non-disruptive TC update */\n+#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE\tBIT(4)\n \t\tu8 flags;\n \t\tu8 sched_type;\n \t\tu8 class_type;\n@@ -1689,6 +1974,7 @@ union ionic_qos_config {\n \t\t\t__le64 strict_rlmt;\n \t\t};\n \t\t/* marking */\n+\t\t/* Used to rewrite PCP or DSCP value. */\n \t\tunion {\n \t\t\tu8 rw_dot1q_pcp;\n \t\t\tu8 rw_ip_dscp;\n@@ -1698,10 +1984,10 @@ union ionic_qos_config {\n \t\t\tu8 dot1q_pcp;\n \t\t\tstruct {\n \t\t\t\tu8 ndscp;\n-\t\t\t\tu8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES];\n+\t\t\t\tu8 ip_dscp[IONIC_QOS_DSCP_MAX];\n \t\t\t};\n \t\t};\n-\t};\n+\t} __rte_packed;\n \t__le32 words[64];\n };\n \n@@ -1717,15 +2003,15 @@ union ionic_qos_identity {\n \t\tu8 version;\n \t\tu8 type;\n \t\tu8 rsvd[62];\n-\t\tunion ionic_qos_config config[IONIC_QOS_CLASS_MAX];\n+\t\tunion ionic_qos_config config[IONIC_QOS_CLASS_MAX];\n \t};\n-\t__le32 words[512];\n+\t__le32 words[478];\n };\n \n /**\n- * struct qos_init_cmd - QoS config init command\n+ * struct ionic_qos_init_cmd - QoS config init command\n * @opcode:\tOpcode\n- * @group:\tQos class id\n+ * @group:\tQoS class id\n * @info_pa:\tdestination address for qos info\n */\n struct ionic_qos_init_cmd {\n@@ -1739,8 +2025,9 @@ struct ionic_qos_init_cmd {\n typedef struct ionic_admin_comp ionic_qos_init_comp;\n \n /**\n- * struct ionic_qos_reset_cmd - Qos config reset command\n+ * struct ionic_qos_reset_cmd - QoS config reset command\n * @opcode:\tOpcode\n+ * @group:\tQoS class id\n */\n struct ionic_qos_reset_cmd {\n \tu8 opcode;\n@@ -1748,6 +2035,16 @@ struct ionic_qos_reset_cmd {\n \tu8 rsvd[62];\n };\n \n+/**\n+ * struct ionic_qos_clear_port_stats_cmd - Qos config reset command\n+ * @opcode:\tOpcode\n+ */\n+struct ionic_qos_clear_stats_cmd {\n+\tu8 opcode;\n+\tu8 group_bitmap;\n+\tu8 rsvd[62];\n+};\n+\n typedef struct ionic_admin_comp ionic_qos_reset_comp;\n \n /**\n@@ -1767,10 +2064,16 @@ struct ionic_fw_download_cmd {\n \n typedef struct ionic_admin_comp ionic_fw_download_comp;\n \n+/**\n+ * enum ionic_fw_control_oper - FW control operations\n+ * @IONIC_FW_RESET: Reset firmware\n+ * @IONIC_FW_INSTALL: Install firmware\n+ * @IONIC_FW_ACTIVATE: Acticate firmware\n+ */\n enum ionic_fw_control_oper {\n-\tIONIC_FW_RESET\t\t= 0,\t/* Reset firmware */\n-\tIONIC_FW_INSTALL\t= 1,\t/* Install firmware */\n-\tIONIC_FW_ACTIVATE\t= 2,\t/* Activate firmware */\n+\tIONIC_FW_RESET\t\t= 0,\n+\tIONIC_FW_INSTALL\t= 1,\n+\tIONIC_FW_ACTIVATE\t= 2,\n };\n \n /**\n@@ -1789,8 +2092,10 @@ struct ionic_fw_control_cmd {\n \n /**\n * struct ionic_fw_control_comp - Firmware control copletion\n- * @opcode: opcode\n- * @slot: slot where the firmware was installed\n+ * @status: Status of the command (enum ionic_status_code)\n+ * @comp_index: Index in the descriptor ring for which this is the completion\n+ * @slot: Slot where the firmware was installed\n+ * @color: Color bit\n */\n struct ionic_fw_control_comp {\n \tu8 status;\n@@ -1808,11 +2113,11 @@ struct ionic_fw_control_comp {\n /**\n * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd\n * @opcode: opcode\n- * @lif_index: lif index\n+ * @lif_index: LIF index\n *\n- * There is no rdma specific dev command completion struct. Completion uses\n+ * There is no RDMA specific dev command completion struct. Completion uses\n * the common struct ionic_admin_comp. Only the status is indicated.\n- * Nonzero status means the LIF does not support rdma.\n+ * Nonzero status means the LIF does not support RDMA.\n **/\n struct ionic_rdma_reset_cmd {\n \tu8 opcode;\n@@ -1824,30 +2129,29 @@ struct ionic_rdma_reset_cmd {\n /**\n * struct ionic_rdma_queue_cmd - Create RDMA Queue command\n * @opcode: opcode, 52, 53\n- * @lif_index lif index\n- * @qid_ver: (qid | (rdma version << 24))\n+ * @lif_index: LIF index\n+ * @qid_ver: (qid | (RDMA version << 24))\n * @cid: intr, eq_id, or cq_id\n * @dbid: doorbell page id\n * @depth_log2: log base two of queue depth\n * @stride_log2: log base two of queue stride\n * @dma_addr: address of the queue memory\n- * @xxx_table_index: temporary, but should not need pgtbl for contig. queues.\n *\n- * The same command struct is used to create an rdma event queue, completion\n- * queue, or rdma admin queue. The cid is an interrupt number for an event\n+ * The same command struct is used to create an RDMA event queue, completion\n+ * queue, or RDMA admin queue. The cid is an interrupt number for an event\n * queue, an event queue id for a completion queue, or a completion queue id\n- * for an rdma admin queue.\n+ * for an RDMA admin queue.\n *\n * The queue created via a dev command must be contiguous in dma space.\n *\n * The dev commands are intended only to be used during driver initialization,\n- * to create queues supporting the rdma admin queue. Other queues, and other\n- * types of rdma resources like memory regions, will be created and registered\n- * via the rdma admin queue, and will support a more complete interface\n+ * to create queues supporting the RDMA admin queue. Other queues, and other\n+ * types of RDMA resources like memory regions, will be created and registered\n+ * via the RDMA admin queue, and will support a more complete interface\n * providing scatter gather lists for larger, scattered queue buffers and\n * memory registration.\n *\n- * There is no rdma specific dev command completion struct. Completion uses\n+ * There is no RDMA specific dev command completion struct. Completion uses\n * the common struct ionic_admin_comp. Only the status is indicated.\n **/\n struct ionic_rdma_queue_cmd {\n@@ -1860,8 +2164,7 @@ struct ionic_rdma_queue_cmd {\n \tu8 depth_log2;\n \tu8 stride_log2;\n \t__le64 dma_addr;\n-\tu8 rsvd2[36];\n-\t__le32 xxx_table_index;\n+\tu8 rsvd2[40];\n };\n \n /******************************************************************\n@@ -1869,7 +2172,7 @@ struct ionic_rdma_queue_cmd {\n ******************************************************************/\n \n /**\n- * struct ionic_notifyq_event\n+ * struct ionic_notifyq_event - Generic event reporting structure\n * @eid: event number\n * @ecode: event code\n * @data: unspecified data about the event\n@@ -1884,10 +2187,10 @@ struct ionic_notifyq_event {\n };\n \n /**\n- * struct ionic_link_change_event\n+ * struct ionic_link_change_event - Link change event notification\n * @eid:\t\tevent number\n- * @ecode:\t\tevent code = EVENT_OPCODE_LINK_CHANGE\n- * @link_status:\tlink up or down, with error bits (enum port_status)\n+ * @ecode:\t\tevent code = IONIC_EVENT_LINK_CHANGE\n+ * @link_status:\tlink up/down, with error bits (enum ionic_port_status)\n * @link_speed:\t\tspeed of the network link\n *\n * Sent when the network link state changes between UP and DOWN\n@@ -1901,9 +2204,9 @@ struct ionic_link_change_event {\n };\n \n /**\n- * struct ionic_reset_event\n+ * struct ionic_reset_event - Reset event notification\n * @eid:\t\tevent number\n- * @ecode:\t\tevent code = EVENT_OPCODE_RESET\n+ * @ecode:\t\tevent code = IONIC_EVENT_RESET\n * @reset_code:\t\treset type\n * @state:\t\t0=pending, 1=complete, 2=error\n *\n@@ -1919,11 +2222,9 @@ struct ionic_reset_event {\n };\n \n /**\n- * struct ionic_heartbeat_event\n+ * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health\n * @eid:\tevent number\n- * @ecode:\tevent code = EVENT_OPCODE_HEARTBEAT\n- *\n- * Sent periodically by the NIC to indicate continued health\n+ * @ecode:\tevent code = IONIC_EVENT_HEARTBEAT\n */\n struct ionic_heartbeat_event {\n \t__le64 eid;\n@@ -1932,12 +2233,10 @@ struct ionic_heartbeat_event {\n };\n \n /**\n- * struct ionic_log_event\n+ * struct ionic_log_event - Sent to notify the driver of an internal error\n * @eid:\tevent number\n- * @ecode:\tevent code = EVENT_OPCODE_LOG\n+ * @ecode:\tevent code = IONIC_EVENT_LOG\n * @data:\tlog data\n- *\n- * Sent to notify the driver of an internal error.\n */\n struct ionic_log_event {\n \t__le64 eid;\n@@ -1946,7 +2245,18 @@ struct ionic_log_event {\n };\n \n /**\n- * struct ionic_port_stats\n+ * struct ionic_xcvr_event - Transceiver change event\n+ * @eid:\tevent number\n+ * @ecode:\tevent code = IONIC_EVENT_XCVR\n+ */\n+struct ionic_xcvr_event {\n+\t__le64 eid;\n+\t__le16 ecode;\n+\tu8 rsvd[54];\n+};\n+\n+/**\n+ * struct ionic_port_stats - Port statistics structure\n */\n struct ionic_port_stats {\n \t__le64 frames_rx_ok;\n@@ -2051,34 +2361,109 @@ struct ionic_mgmt_port_stats {\n \t__le64 frames_rx_multicast;\n \t__le64 frames_rx_broadcast;\n \t__le64 frames_rx_pause;\n-\t__le64 frames_rx_bad_length0;\n-\t__le64 frames_rx_undersized1;\n-\t__le64 frames_rx_oversized2;\n-\t__le64 frames_rx_fragments3;\n-\t__le64 frames_rx_jabber4;\n-\t__le64 frames_rx_64b5;\n-\t__le64 frames_rx_65b_127b6;\n-\t__le64 frames_rx_128b_255b7;\n-\t__le64 frames_rx_256b_511b8;\n-\t__le64 frames_rx_512b_1023b9;\n-\t__le64 frames_rx_1024b_1518b0;\n-\t__le64 frames_rx_gt_1518b1;\n-\t__le64 frames_rx_fifo_full2;\n-\t__le64 frames_tx_ok3;\n-\t__le64 frames_tx_all4;\n-\t__le64 frames_tx_bad5;\n-\t__le64 octets_tx_ok6;\n-\t__le64 octets_tx_total7;\n-\t__le64 frames_tx_unicast8;\n-\t__le64 frames_tx_multicast9;\n-\t__le64 frames_tx_broadcast0;\n-\t__le64 frames_tx_pause1;\n+\t__le64 frames_rx_bad_length;\n+\t__le64 frames_rx_undersized;\n+\t__le64 frames_rx_oversized;\n+\t__le64 frames_rx_fragments;\n+\t__le64 frames_rx_jabber;\n+\t__le64 frames_rx_64b;\n+\t__le64 frames_rx_65b_127b;\n+\t__le64 frames_rx_128b_255b;\n+\t__le64 frames_rx_256b_511b;\n+\t__le64 frames_rx_512b_1023b;\n+\t__le64 frames_rx_1024b_1518b;\n+\t__le64 frames_rx_gt_1518b;\n+\t__le64 frames_rx_fifo_full;\n+\t__le64 frames_tx_ok;\n+\t__le64 frames_tx_all;\n+\t__le64 frames_tx_bad;\n+\t__le64 octets_tx_ok;\n+\t__le64 octets_tx_total;\n+\t__le64 frames_tx_unicast;\n+\t__le64 frames_tx_multicast;\n+\t__le64 frames_tx_broadcast;\n+\t__le64 frames_tx_pause;\n+};\n+\n+enum ionic_pb_buffer_drop_stats {\n+\tIONIC_BUFFER_INTRINSIC_DROP = 0,\n+\tIONIC_BUFFER_DISCARDED,\n+\tIONIC_BUFFER_ADMITTED,\n+\tIONIC_BUFFER_OUT_OF_CELLS_DROP,\n+\tIONIC_BUFFER_OUT_OF_CELLS_DROP_2,\n+\tIONIC_BUFFER_OUT_OF_CREDIT_DROP,\n+\tIONIC_BUFFER_TRUNCATION_DROP,\n+\tIONIC_BUFFER_PORT_DISABLED_DROP,\n+\tIONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,\n+\tIONIC_BUFFER_SPAN_TAIL_DROP,\n+\tIONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,\n+\tIONIC_BUFFER_ENQUEUE_ERROR_DROP,\n+\tIONIC_BUFFER_INVALID_PORT_DROP,\n+\tIONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,\n+\tIONIC_BUFFER_DROP_MAX,\n+};\n+\n+enum ionic_oflow_drop_stats {\n+\tIONIC_OFLOW_OCCUPANCY_DROP,\n+\tIONIC_OFLOW_EMERGENCY_STOP_DROP,\n+\tIONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,\n+\tIONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,\n+\tIONIC_OFLOW_WRITE_BUFFER_FULL_DROP,\n+\tIONIC_OFLOW_CONTROL_FIFO_FULL_DROP,\n+\tIONIC_OFLOW_DROP_MAX,\n+};\n+\n+/**\n+ * struct port_pb_stats - packet buffers system stats\n+ * uses ionic_pb_buffer_drop_stats for drop_counts[]\n+ */\n+struct ionic_port_pb_stats {\n+\t__le64 sop_count_in;\n+\t__le64 eop_count_in;\n+\t__le64 sop_count_out;\n+\t__le64 eop_count_out;\n+\t__le64 drop_counts[IONIC_BUFFER_DROP_MAX];\n+\t__le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];\n+\t__le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];\n+\t__le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];\n+\t__le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];\n+\t__le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];\n+\t__le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];\n+};\n+\n+/**\n+ * enum ionic_port_type - Port types\n+ * @IONIC_ETH_UNKNOWN: Port type not configured\n+ * @IONIC_ETH_HOST: Port carries ethernet traffic (inband)\n+ * @IONIC_ETH_HOST_MGMT: Port carries mgmt traffic (out-of-band)\n+ * @IONIC_ETH_MNIC_OOB_MGMT:\n+ * @IONIC_ETH_MNIC_INTERNAL_MGMT:\n+ * @IONIC_ETH_MNIC_INBAND_MGMT:\n+ * @IONIC_ETH_MNIC_CPU:\n+ * @IONIC_ETH_MNIC_LEARN:\n+ * @IONIC_ETH_MNIC_CONTROL:\n+ */\n+enum ionic_port_type {\n+\tIONIC_ETH_UNKNOWN,\n+\tIONIC_ETH_HOST,\n+\tIONIC_ETH_HOST_MGMT,\n+\tIONIC_ETH_MNIC_OOB_MGMT,\n+\tIONIC_ETH_MNIC_INTERNAL_MGMT,\n+\tIONIC_ETH_MNIC_INBAND_MGMT,\n+\tIONIC_ETH_MNIC_CPU,\n+\tIONIC_ETH_MNIC_LEARN,\n+\tIONIC_ETH_MNIC_CONTROL,\n };\n \n /**\n * struct ionic_port_identity - port identity structure\n * @version: identity structure version\n- * @type: type of port (enum port_type)\n+ * @type: type of port (enum ionic_port_type)\n * @num_lanes: number of lanes for the port\n * @autoneg: autoneg supported\n * @min_frame_size: minimum frame size supported\n@@ -2104,22 +2489,31 @@ union ionic_port_identity {\n \t\tu8 rsvd2[44];\n \t\tunion ionic_port_config config;\n \t};\n-\t__le32 words[512];\n+\t__le32 words[478];\n };\n \n /**\n * struct ionic_port_info - port info structure\n- * @port_status: port status\n- * @port_stats: port stats\n+ * @config: Port configuration data\n+ * @status: Port status data\n+ * @stats: Port statistics data\n+ * @mgmt_stats: Port management statistics data\n+ * @port_pb_drop_stats: uplink pb drop stats\n */\n struct ionic_port_info {\n \tunion ionic_port_config config;\n \tstruct ionic_port_status status;\n-\tstruct ionic_port_stats stats;\n+\tunion {\n+\t\tstruct ionic_port_stats stats;\n+\t\tstruct ionic_mgmt_port_stats mgmt_stats;\n+\t};\n+\t/* room for pb_stats to start at 2k offset */\n+\tu8 rsvd[760];\n+\tstruct ionic_port_pb_stats pb_stats;\n };\n \n /**\n- * struct ionic_lif_stats\n+ * struct ionic_lif_stats - LIF statistics structure\n */\n struct ionic_lif_stats {\n \t/* RX */\n@@ -2172,7 +2566,7 @@ struct ionic_lif_stats {\n \t__le64 tx_queue_error;\n \t__le64 tx_desc_fetch_error;\n \t__le64 tx_desc_data_error;\n-\t__le64 rsvd9;\n+\t__le64 tx_queue_empty;\n \t__le64 rsvd10;\n \t__le64 rsvd11;\n \t__le64 rsvd12;\n@@ -2273,7 +2667,10 @@ struct ionic_lif_stats {\n };\n \n /**\n- * struct ionic_lif_info - lif info structure\n+ * struct ionic_lif_info - LIF info structure\n+ * @config:\tLIF configuration structure\n+ * @status:\tLIF status structure\n+ * @stats:\tLIF statistics structure\n */\n struct ionic_lif_info {\n \tunion ionic_lif_config config;\n@@ -2298,6 +2695,9 @@ union ionic_dev_cmd {\n \tstruct ionic_port_getattr_cmd port_getattr;\n \tstruct ionic_port_setattr_cmd port_setattr;\n \n+\tstruct ionic_vf_setattr_cmd vf_setattr;\n+\tstruct ionic_vf_getattr_cmd vf_getattr;\n+\n \tstruct ionic_lif_identify_cmd lif_identify;\n \tstruct ionic_lif_init_cmd lif_init;\n \tstruct ionic_lif_reset_cmd lif_reset;\n@@ -2305,8 +2705,11 @@ union ionic_dev_cmd {\n \tstruct ionic_qos_identify_cmd qos_identify;\n \tstruct ionic_qos_init_cmd qos_init;\n \tstruct ionic_qos_reset_cmd qos_reset;\n+\tstruct ionic_qos_clear_stats_cmd qos_clear_stats;\n \n+\tstruct ionic_q_identify_cmd q_identify;\n \tstruct ionic_q_init_cmd q_init;\n+\tstruct ionic_q_control_cmd q_control;\n };\n \n union ionic_dev_cmd_comp {\n@@ -2327,6 +2730,9 @@ union ionic_dev_cmd_comp {\n \tstruct ionic_port_getattr_comp port_getattr;\n \tstruct ionic_port_setattr_comp port_setattr;\n \n+\tstruct ionic_vf_setattr_comp vf_setattr;\n+\tstruct ionic_vf_getattr_comp vf_getattr;\n+\n \tstruct ionic_lif_identify_comp lif_identify;\n \tstruct ionic_lif_init_comp lif_init;\n \tionic_lif_reset_comp lif_reset;\n@@ -2335,19 +2741,20 @@ union ionic_dev_cmd_comp {\n \tionic_qos_init_comp qos_init;\n \tionic_qos_reset_comp qos_reset;\n \n+\tstruct ionic_q_identify_comp q_identify;\n \tstruct ionic_q_init_comp q_init;\n };\n \n /**\n- * union dev_info - Device info register format (read-only)\n- * @signature: Signature value of 0x44455649 ('DEVI').\n- * @version: Current version of info.\n- * @asic_type: Asic type.\n- * @asic_rev: Asic revision.\n- * @fw_status: Firmware status.\n- * @fw_heartbeat: Firmware heartbeat counter.\n- * @serial_num: Serial number.\n- * @fw_version: Firmware version.\n+ * union ionic_dev_info_regs - Device info register format (read-only)\n+ * @signature: Signature value of 0x44455649 ('DEVI')\n+ * @version: Current version of info\n+ * @asic_type: Asic type\n+ * @asic_rev: Asic revision\n+ * @fw_status: Firmware status\n+ * @fw_heartbeat: Firmware heartbeat counter\n+ * @serial_num: Serial number\n+ * @fw_version: Firmware version\n */\n union ionic_dev_info_regs {\n #define IONIC_DEVINFO_FWVERS_BUFLEN 32\n@@ -2357,6 +2764,7 @@ union ionic_dev_info_regs {\n \t\tu8 version;\n \t\tu8 asic_type;\n \t\tu8 asic_rev;\n+#define IONIC_FW_STS_F_RUNNING\t0x1\n \t\tu8 fw_status;\n \t\tu32 fw_heartbeat;\n \t\tchar fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];\n@@ -2367,10 +2775,10 @@ union ionic_dev_info_regs {\n \n /**\n * union ionic_dev_cmd_regs - Device command register format (read-write)\n- * @doorbell: Device Cmd Doorbell, write-only.\n+ * @doorbell: Device Cmd Doorbell, write-only\n * Write a 1 to signal device to process cmd,\n * poll done for completion.\n- * @done: Done indicator, bit 0 == 1 when command is complete.\n+ * @done: Done indicator, bit 0 == 1 when command is complete\n * @cmd: Opcode-specific command bytes\n * @comp: Opcode-specific response bytes\n * @data: Opcode-specific side-data\n@@ -2383,12 +2791,12 @@ union ionic_dev_cmd_regs {\n \t\tunion ionic_dev_cmd_comp comp;\n \t\tu8 rsvd[48];\n \t\tu32 data[478];\n-\t};\n+\t} __rte_packed;\n \tu32 words[512];\n };\n \n /**\n- * union ionic_dev_regs - Device register format in for bar 0 page 0\n+ * union ionic_dev_regs - Device register format for bar 0 page 0\n * @info: Device info registers\n * @devcmd: Device command registers\n */\n@@ -2396,13 +2804,14 @@ union ionic_dev_regs {\n \tstruct {\n \t\tunion ionic_dev_info_regs info;\n \t\tunion ionic_dev_cmd_regs devcmd;\n-\t};\n+\t} __rte_packed;\n \t__le32 words[1024];\n };\n \n union ionic_adminq_cmd {\n \tstruct ionic_admin_cmd cmd;\n \tstruct ionic_nop_cmd nop;\n+\tstruct ionic_q_identify_cmd q_identify;\n \tstruct ionic_q_init_cmd q_init;\n \tstruct ionic_q_control_cmd q_control;\n \tstruct ionic_lif_setattr_cmd lif_setattr;\n@@ -2419,6 +2828,7 @@ union ionic_adminq_cmd {\n union ionic_adminq_comp {\n \tstruct ionic_admin_comp comp;\n \tstruct ionic_nop_comp nop;\n+\tstruct ionic_q_identify_comp q_identify;\n \tstruct ionic_q_init_comp q_init;\n \tstruct ionic_lif_setattr_comp lif_setattr;\n \tstruct ionic_lif_getattr_comp lif_getattr;\n@@ -2444,14 +2854,14 @@ union ionic_adminq_comp {\n /**\n * struct ionic_doorbell - Doorbell register layout\n * @p_index: Producer index\n- * @ring: Selects the specific ring of the queue to update.\n+ * @ring: Selects the specific ring of the queue to update\n * Type-specific meaning:\n- * ring=0: Default producer/consumer queue.\n+ * ring=0: Default producer/consumer queue\n * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs\n * send events to EQs when armed. EQs send\n * interrupts when armed.\n- * @qid: The queue id selects the queue destination for the\n- * producer index and flags.\n+ * @qid_lo: Queue destination for the producer index and flags (low bits)\n+ * @qid_hi: Queue destination for the producer index and flags (high bits)\n */\n struct ionic_doorbell {\n \t__le16 p_index;\n@@ -2461,6 +2871,92 @@ struct ionic_doorbell {\n \tu16 rsvd2;\n };\n \n+/**\n+ * struct ionic_intr_ctrl - Interrupt control register\n+ * @coalescing_init: Coalescing timer initial value, in\n+ * device units. Use @identity->intr_coal_mult\n+ * and @identity->intr_coal_div to convert from\n+ * usecs to device units:\n+ *\n+ * coal_init = coal_usecs * coal_mutl / coal_div\n+ *\n+ * When an interrupt is sent the interrupt\n+ * coalescing timer current value\n+ * (@coalescing_curr) is initialized with this\n+ * value and begins counting down. No more\n+ * interrupts are sent until the coalescing\n+ * timer reaches 0. When @coalescing_init=0\n+ * interrupt coalescing is effectively disabled\n+ * and every interrupt assert results in an\n+ * interrupt. Reset value: 0\n+ * @mask: Interrupt mask. When @mask=1 the interrupt\n+ * resource will not send an interrupt. When\n+ * @mask=0 the interrupt resource will send an\n+ * interrupt if an interrupt event is pending\n+ * or on the next interrupt assertion event.\n+ * Reset value: 1\n+ * @int_credits: Interrupt credits. This register indicates\n+ * how many interrupt events the hardware has\n+ * sent. When written by software this\n+ * register atomically decrements @int_credits\n+ * by the value written. When @int_credits\n+ * becomes 0 then the \"pending interrupt\" bit\n+ * in the Interrupt Status register is cleared\n+ * by the hardware and any pending but unsent\n+ * interrupts are cleared.\n+ * !!!IMPORTANT!!! This is a signed register.\n+ * @flags: Interrupt control flags\n+ * @unmask -- When this bit is written with a 1\n+ * the interrupt resource will set mask=0.\n+ * @coal_timer_reset -- When this\n+ * bit is written with a 1 the\n+ * @coalescing_curr will be reloaded with\n+ * @coalescing_init to reset the coalescing\n+ * timer.\n+ * @mask_on_assert: Automatically mask on assertion. When\n+ * @mask_on_assert=1 the interrupt resource\n+ * will set @mask=1 whenever an interrupt is\n+ * sent. When using interrupts in Legacy\n+ * Interrupt mode the driver must select\n+ * @mask_on_assert=0 for proper interrupt\n+ * operation.\n+ * @coalescing_curr: Coalescing timer current value, in\n+ * microseconds. When this value reaches 0\n+ * the interrupt resource is again eligible to\n+ * send an interrupt. If an interrupt event\n+ * is already pending when @coalescing_curr\n+ * reaches 0 the pending interrupt will be\n+ * sent, otherwise an interrupt will be sent\n+ * on the next interrupt assertion event.\n+ */\n+struct ionic_intr_ctrl {\n+\tu8 coalescing_init;\n+\tu8 rsvd[3];\n+\tu8 mask;\n+\tu8 rsvd2[3];\n+\tu16 int_credits;\n+\tu16 flags;\n+#define INTR_F_UNMASK\t\t0x0001\n+#define INTR_F_TIMER_RESET\t0x0002\n+\tu8 mask_on_assert;\n+\tu8 rsvd3[3];\n+\tu8 coalescing_curr;\n+\tu8 rsvd4[3];\n+\tu32 rsvd6[3];\n+};\n+\n+#define IONIC_INTR_CTRL_REGS_MAX\t2048\n+#define IONIC_INTR_CTRL_COAL_MAX\t0x3F\n+\n+#define intr_to_coal(intr_ctrl)\t\t\\\n+\t\t((void __iomem *)&(intr_ctrl)->coalescing_init)\n+#define intr_to_mask(intr_ctrl)\t\t\\\n+\t\t((void __iomem *)&(intr_ctrl)->mask)\n+#define intr_to_credits(intr_ctrl)\t\\\n+\t\t((void __iomem *)&(intr_ctrl)->int_credits)\n+#define intr_to_mask_on_assert(intr_ctrl)\\\n+\t\t((void __iomem *)&(intr_ctrl)->mask_on_assert)\n+\n struct ionic_intr_status {\n \tu32 status[2];\n };\n@@ -2477,6 +2973,28 @@ union ionic_notifyq_comp {\n \tstruct ionic_log_event log;\n };\n \n+/**\n+ * struct ionic_eq_comp - Event queue completion descriptor\n+ *\n+ * @code:\tEvent code, see enum ionic_eq_comp_code\n+ * @lif_index:\tTo which LIF the event pertains\n+ * @qid:\tTo which queue id the event pertains\n+ * @gen_color:\tEvent queue wrap counter, init 1, incr each wrap\n+ */\n+struct ionic_eq_comp {\n+\t__le16 code;\n+\t__le16 lif_index;\n+\t__le32 qid;\n+\tu8 rsvd[7];\n+\tu8 gen_color;\n+};\n+\n+enum ionic_eq_comp_code {\n+\tIONIC_EQ_COMP_CODE_NONE = 0,\n+\tIONIC_EQ_COMP_CODE_RX_COMP = 1,\n+\tIONIC_EQ_COMP_CODE_TX_COMP = 2,\n+};\n+\n /* Deprecate */\n struct ionic_identity {\n \tunion ionic_drv_identity drv;\n@@ -2484,8 +3002,7 @@ struct ionic_identity {\n \tunion ionic_lif_identity lif;\n \tunion ionic_port_identity port;\n \tunion ionic_qos_identity qos;\n+\tunion ionic_q_identity txq;\n };\n \n-#pragma pack(pop)\n-\n #endif /* _IONIC_IF_H_ */\ndiff --git a/drivers/net/ionic/ionic_regs.h b/drivers/net/ionic/ionic_regs.h\nindex 3adc2bc7c..6ebc48d04 100644\n--- a/drivers/net/ionic/ionic_regs.h\n+++ b/drivers/net/ionic/ionic_regs.h\n@@ -21,9 +21,6 @@ struct ionic_intr {\n \tuint32_t rsvd[3];\n };\n \n-#define IONIC_INTR_CTRL_REGS_MAX\t2048\n-#define IONIC_INTR_CTRL_COAL_MAX\t0x3F\n-\n /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.\n * @IONIC_INTR_MASK_CLEAR:\tunmask interrupt.\n * @IONIC_INTR_MASK_SET:\tmask interrupt.\n", "prefixes": [ "3/8" ] }