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GET /api/patches/83184/?format=api
{ "id": 83184, "url": "https://patches.dpdk.org/api/patches/83184/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1604165181-19929-9-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1604165181-19929-9-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1604165181-19929-9-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-10-31T17:26:06", "name": "[v9,08/23] event/dlb2: add probe-time hardware init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "44b270e57f12646ec42b7c68fb9834c668a58065", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1604165181-19929-9-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 13528, "url": "https://patches.dpdk.org/api/series/13528/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13528", "date": "2020-10-31T17:25:58", "name": "Add DLB2 PMD", "version": 9, "mbox": "https://patches.dpdk.org/series/13528/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/83184/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/83184/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D6234A04DC;\n\tSat, 31 Oct 2020 18:27:40 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C96E169A4;\n\tSat, 31 Oct 2020 18:25:09 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 67ECB593A\n for <dev@dpdk.org>; Sat, 31 Oct 2020 18:24:45 +0100 (CET)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 31 Oct 2020 10:24:43 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by orsmga006.jf.intel.com with ESMTP; 31 Oct 2020 10:24:43 -0700" ], "IronPort-SDR": [ "\n b47AYfWm2HfDuL+Zwhb8MHdk++sOoE5QoRE0wMCQMOGyuIIs0RlVq2aZJh0I4Fyyv837eQNvpW\n dOj28If7f3uA==", "\n s1XT65AWFr7kQ3GLWjGjqrKq4Z1m/oitaEgnfaalq4I/Oo9SSEB0B5a2JGUC/ux/TxA130ifNx\n URa8xgPD9D/w==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9791\"; a=\"148597790\"", "E=Sophos;i=\"5.77,438,1596524400\"; d=\"scan'208\";a=\"148597790\"", "E=Sophos;i=\"5.77,438,1596524400\"; d=\"scan'208\";a=\"324398014\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Sat, 31 Oct 2020 12:26:06 -0500", "Message-Id": "<1604165181-19929-9-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1604165181-19929-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<1602958879-8558-2-git-send-email-timothy.mcdaniel@intel.com>\n <1604165181-19929-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 08/23] event/dlb2: add probe-time hardware init", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds probe-time low level hardware\ninitialization. It also adds probe-time init for both\nprimary and secondary DPDK processes.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 188 +++++++++++++++++++-\n drivers/event/dlb2/meson.build | 3 +-\n drivers/event/dlb2/pf/base/dlb2_resource.c | 274 +++++++++++++++++++++++++++++\n drivers/event/dlb2/pf/dlb2_main.c | 23 +--\n drivers/event/dlb2/pf/dlb2_main.h | 1 -\n drivers/event/dlb2/pf/dlb2_pf.c | 78 ++++++--\n 6 files changed, 523 insertions(+), 44 deletions(-)\n create mode 100644 drivers/event/dlb2/pf/base/dlb2_resource.c", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 1b11979..16653db 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -31,6 +31,7 @@\n #include <rte_string_fns.h>\n \n #include \"dlb2_priv.h\"\n+#include \"dlb2_iface.h\"\n #include \"dlb2_inline_fns.h\"\n \n /*\n@@ -40,10 +41,108 @@\n #if (RTE_EVENT_MAX_QUEUES_PER_DEV > UINT8_MAX)\n #error \"RTE_EVENT_MAX_QUEUES_PER_DEV cannot fit in member max_event_queues\"\n #endif\n+static struct rte_event_dev_info evdev_dlb2_default_info = {\n+\t.driver_name = \"\", /* probe will set */\n+\t.min_dequeue_timeout_ns = DLB2_MIN_DEQUEUE_TIMEOUT_NS,\n+\t.max_dequeue_timeout_ns = DLB2_MAX_DEQUEUE_TIMEOUT_NS,\n+#if (RTE_EVENT_MAX_QUEUES_PER_DEV < DLB2_MAX_NUM_LDB_QUEUES)\n+\t.max_event_queues = RTE_EVENT_MAX_QUEUES_PER_DEV,\n+#else\n+\t.max_event_queues = DLB2_MAX_NUM_LDB_QUEUES,\n+#endif\n+\t.max_event_queue_flows = DLB2_MAX_NUM_FLOWS,\n+\t.max_event_queue_priority_levels = DLB2_QID_PRIORITIES,\n+\t.max_event_priority_levels = DLB2_QID_PRIORITIES,\n+\t.max_event_ports = DLB2_MAX_NUM_LDB_PORTS,\n+\t.max_event_port_dequeue_depth = DLB2_MAX_CQ_DEPTH,\n+\t.max_event_port_enqueue_depth = DLB2_MAX_ENQUEUE_DEPTH,\n+\t.max_event_port_links = DLB2_MAX_NUM_QIDS_PER_LDB_CQ,\n+\t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n+\t.max_single_link_event_port_queue_pairs = DLB2_MAX_NUM_DIR_PORTS,\n+\t.event_dev_cap = (RTE_EVENT_DEV_CAP_QUEUE_QOS |\n+\t\t\t RTE_EVENT_DEV_CAP_EVENT_QOS |\n+\t\t\t RTE_EVENT_DEV_CAP_BURST_MODE |\n+\t\t\t RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |\n+\t\t\t RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE |\n+\t\t\t RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES),\n+};\n \n struct process_local_port_data\n dlb2_port[DLB2_MAX_NUM_PORTS][DLB2_NUM_PORT_TYPES];\n \n+/* override defaults with value(s) provided on command line */\n+static void\n+dlb2_init_queue_depth_thresholds(struct dlb2_eventdev *dlb2,\n+\t\t\t\t int *qid_depth_thresholds)\n+{\n+\tint q;\n+\n+\tfor (q = 0; q < DLB2_MAX_NUM_QUEUES; q++) {\n+\t\tif (qid_depth_thresholds[q] != 0)\n+\t\t\tdlb2->ev_queues[q].depth_threshold =\n+\t\t\t\tqid_depth_thresholds[q];\n+\t}\n+}\n+\n+static int\n+dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)\n+{\n+\tstruct dlb2_hw_dev *handle = &dlb2->qm_instance;\n+\tstruct dlb2_hw_resource_info *dlb2_info = &handle->info;\n+\tint ret;\n+\n+\t/* Query driver resources provisioned for this device */\n+\n+\tret = dlb2_iface_get_num_resources(handle,\n+\t\t\t\t\t &dlb2->hw_rsrc_query_results);\n+\tif (ret) {\n+\t\tDLB2_LOG_ERR(\"ioctl get dlb2 num resources, err=%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Complete filling in device resource info returned to evdev app,\n+\t * overriding any default values.\n+\t * The capabilities (CAPs) were set at compile time.\n+\t */\n+\n+\tevdev_dlb2_default_info.max_event_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues;\n+\n+\tevdev_dlb2_default_info.max_event_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_ports;\n+\n+\tevdev_dlb2_default_info.max_num_events =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\n+\t/* Save off values used when creating the scheduling domain. */\n+\n+\thandle->info.num_sched_domains =\n+\t\tdlb2->hw_rsrc_query_results.num_sched_domains;\n+\n+\thandle->info.hw_rsrc_max.nb_events_limit =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_credits;\n+\n+\thandle->info.hw_rsrc_max.num_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues +\n+\t\tdlb2->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_queues =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_queues;\n+\n+\thandle->info.hw_rsrc_max.num_ldb_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_ldb_ports;\n+\n+\thandle->info.hw_rsrc_max.num_dir_ports =\n+\t\tdlb2->hw_rsrc_query_results.num_dir_ports;\n+\n+\thandle->info.hw_rsrc_max.reorder_window_size =\n+\t\tdlb2->hw_rsrc_query_results.num_hist_list_entries;\n+\n+\trte_memcpy(dlb2_info, &handle->info.hw_rsrc_max, sizeof(*dlb2_info));\n+\n+\treturn 0;\n+}\n+\n #define DLB2_BASE_10 10\n \n static int\n@@ -235,14 +334,71 @@ set_qid_depth_thresh(const char *key __rte_unused,\n \treturn 0;\n }\n \n+static void\n+dlb2_entry_points_init(struct rte_eventdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\t/* Eventdev PMD entry points */\n+}\n+\n int\n dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \t\t\t const char *name,\n \t\t\t struct dlb2_devargs *dlb2_args)\n {\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(name);\n-\tRTE_SET_USED(dlb2_args);\n+\tstruct dlb2_eventdev *dlb2;\n+\tint err;\n+\n+\tdlb2 = dev->data->dev_private;\n+\n+\tdlb2->event_dev = dev; /* backlink */\n+\n+\tevdev_dlb2_default_info.driver_name = name;\n+\n+\tdlb2->max_num_events_override = dlb2_args->max_num_events;\n+\tdlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;\n+\tdlb2->qm_instance.cos_id = dlb2_args->cos_id;\n+\n+\terr = dlb2_iface_open(&dlb2->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_iface_get_device_version(&dlb2->qm_instance,\n+\t\t\t\t\t &dlb2->revision);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2: failed to get the device version, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_hw_query_resources(dlb2);\n+\tif (err) {\n+\t\tDLB2_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb2_iface_hardware_init(&dlb2->qm_instance);\n+\n+\terr = dlb2_iface_get_cq_poll_mode(&dlb2->qm_instance, &dlb2->poll_mode);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"dlb2: failed to get the poll mode, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\trte_spinlock_init(&dlb2->qm_instance.resource_lock);\n+\n+\tdlb2_iface_low_level_io_init();\n+\n+\tdlb2_entry_points_init(dev);\n+\n+\tdlb2_init_queue_depth_thresholds(dlb2,\n+\t\t\t\t\t dlb2_args->qid_depth_thresholds.val);\n \n \treturn 0;\n }\n@@ -251,8 +407,30 @@ int\n dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,\n \t\t\t const char *name)\n {\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(name);\n+\tstruct dlb2_eventdev *dlb2;\n+\tint err;\n+\n+\tdlb2 = dev->data->dev_private;\n+\n+\tevdev_dlb2_default_info.driver_name = name;\n+\n+\terr = dlb2_iface_open(&dlb2->qm_instance, name);\n+\tif (err < 0) {\n+\t\tDLB2_LOG_ERR(\"could not open event hardware device, err=%d\\n\",\n+\t\t\t err);\n+\t\treturn err;\n+\t}\n+\n+\terr = dlb2_hw_query_resources(dlb2);\n+\tif (err) {\n+\t\tDLB2_LOG_ERR(\"get resources err=%d for %s\\n\",\n+\t\t\t err, name);\n+\t\treturn err;\n+\t}\n+\n+\tdlb2_iface_low_level_io_init();\n+\n+\tdlb2_entry_points_init(dev);\n \n \treturn 0;\n }\ndiff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build\nindex 491e76d..28fef3f 100644\n--- a/drivers/event/dlb2/meson.build\n+++ b/drivers/event/dlb2/meson.build\n@@ -10,7 +10,8 @@ endif\n sources = files('dlb2.c',\n \t\t'dlb2_iface.c',\n \t\t'pf/dlb2_main.c',\n-\t\t'pf/dlb2_pf.c'\n+\t\t'pf/dlb2_pf.c',\n+\t\t'pf/base/dlb2_resource.c'\n )\n \n deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nnew file mode 100644\nindex 0000000..6de8b95\n--- /dev/null\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -0,0 +1,274 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016-2020 Intel Corporation\n+ */\n+\n+#include \"dlb2_user.h\"\n+\n+#include \"dlb2_hw_types.h\"\n+#include \"dlb2_mbox.h\"\n+#include \"dlb2_osdep.h\"\n+#include \"dlb2_osdep_bitmap.h\"\n+#include \"dlb2_osdep_types.h\"\n+#include \"dlb2_regs.h\"\n+#include \"dlb2_resource.h\"\n+\n+static void dlb2_init_domain_rsrc_lists(struct dlb2_hw_domain *domain)\n+{\n+\tint i;\n+\n+\tdlb2_list_init_head(&domain->used_ldb_queues);\n+\tdlb2_list_init_head(&domain->used_dir_pq_pairs);\n+\tdlb2_list_init_head(&domain->avail_ldb_queues);\n+\tdlb2_list_init_head(&domain->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->used_ldb_ports[i]);\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&domain->avail_ldb_ports[i]);\n+}\n+\n+static void dlb2_init_fn_rsrc_lists(struct dlb2_function_resources *rsrc)\n+{\n+\tint i;\n+\n+\tdlb2_list_init_head(&rsrc->avail_domains);\n+\tdlb2_list_init_head(&rsrc->used_domains);\n+\tdlb2_list_init_head(&rsrc->avail_ldb_queues);\n+\tdlb2_list_init_head(&rsrc->avail_dir_pq_pairs);\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\tdlb2_list_init_head(&rsrc->avail_ldb_ports[i]);\n+}\n+\n+void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.field.cfg_64bytes_qe_dir_cq_mode = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n+\t\t\t struct dlb2_get_num_resources_args *arg,\n+\t\t\t bool vdev_req,\n+\t\t\t unsigned int vdev_id)\n+{\n+\tstruct dlb2_function_resources *rsrcs;\n+\tstruct dlb2_bitmap *map;\n+\tint i;\n+\n+\tif (vdev_req && vdev_id >= DLB2_MAX_NUM_VDEVS)\n+\t\treturn -EINVAL;\n+\n+\tif (vdev_req)\n+\t\trsrcs = &hw->vdev[vdev_id];\n+\telse\n+\t\trsrcs = &hw->pf;\n+\n+\targ->num_sched_domains = rsrcs->num_avail_domains;\n+\n+\targ->num_ldb_queues = rsrcs->num_avail_ldb_queues;\n+\n+\targ->num_ldb_ports = 0;\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\targ->num_ldb_ports += rsrcs->num_avail_ldb_ports[i];\n+\n+\targ->num_cos_ldb_ports[0] = rsrcs->num_avail_ldb_ports[0];\n+\targ->num_cos_ldb_ports[1] = rsrcs->num_avail_ldb_ports[1];\n+\targ->num_cos_ldb_ports[2] = rsrcs->num_avail_ldb_ports[2];\n+\targ->num_cos_ldb_ports[3] = rsrcs->num_avail_ldb_ports[3];\n+\n+\targ->num_dir_ports = rsrcs->num_avail_dir_pq_pairs;\n+\n+\targ->num_atomic_inflights = rsrcs->num_avail_aqed_entries;\n+\n+\tmap = rsrcs->avail_hist_list_entries;\n+\n+\targ->num_hist_list_entries = dlb2_bitmap_count(map);\n+\n+\targ->max_contiguous_hist_list_entries =\n+\t\tdlb2_bitmap_longest_set_range(map);\n+\n+\targ->num_ldb_credits = rsrcs->num_avail_qed_entries;\n+\n+\targ->num_dir_credits = rsrcs->num_avail_dqed_entries;\n+\n+\treturn 0;\n+}\n+\n+void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_chp_cfg_chp_csr_ctrl r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CHP_CFG_CHP_CSR_CTRL);\n+\n+\tr0.field.cfg_64bytes_qe_ldb_cq_mode = 1;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CHP_CFG_CHP_CSR_CTRL, r0.val);\n+}\n+\n+void dlb2_resource_free(struct dlb2_hw *hw)\n+{\n+\tint i;\n+\n+\tif (hw->pf.avail_hist_list_entries)\n+\t\tdlb2_bitmap_free(hw->pf.avail_hist_list_entries);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tif (hw->vdev[i].avail_hist_list_entries)\n+\t\t\tdlb2_bitmap_free(hw->vdev[i].avail_hist_list_entries);\n+\t}\n+}\n+\n+int dlb2_resource_init(struct dlb2_hw *hw)\n+{\n+\tstruct dlb2_list_entry *list;\n+\tunsigned int i;\n+\tint ret;\n+\n+\t/*\n+\t * For optimal load-balancing, ports that map to one or more QIDs in\n+\t * common should not be in numerical sequence. This is application\n+\t * dependent, but the driver interleaves port IDs as much as possible\n+\t * to reduce the likelihood of this. This initial allocation maximizes\n+\t * the average distance between an ID and its immediate neighbors (i.e.\n+\t * the distance from 1 to 0 and to 2, the distance from 2 to 1 and to\n+\t * 3, etc.).\n+\t */\n+\tu8 init_ldb_port_allocation[DLB2_MAX_NUM_LDB_PORTS] = {\n+\t\t0, 7, 14, 5, 12, 3, 10, 1, 8, 15, 6, 13, 4, 11, 2, 9,\n+\t\t16, 23, 30, 21, 28, 19, 26, 17, 24, 31, 22, 29, 20, 27, 18, 25,\n+\t\t32, 39, 46, 37, 44, 35, 42, 33, 40, 47, 38, 45, 36, 43, 34, 41,\n+\t\t48, 55, 62, 53, 60, 51, 58, 49, 56, 63, 54, 61, 52, 59, 50, 57,\n+\t};\n+\n+\t/* Zero-out resource tracking data structures */\n+\tmemset(&hw->rsrcs, 0, sizeof(hw->rsrcs));\n+\tmemset(&hw->pf, 0, sizeof(hw->pf));\n+\n+\tdlb2_init_fn_rsrc_lists(&hw->pf);\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tmemset(&hw->vdev[i], 0, sizeof(hw->vdev[i]));\n+\t\tdlb2_init_fn_rsrc_lists(&hw->vdev[i]);\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\tmemset(&hw->domains[i], 0, sizeof(hw->domains[i]));\n+\t\tdlb2_init_domain_rsrc_lists(&hw->domains[i]);\n+\t\thw->domains[i].parent_func = &hw->pf;\n+\t}\n+\n+\t/* Give all resources to the PF driver */\n+\thw->pf.num_avail_domains = DLB2_MAX_NUM_DOMAINS;\n+\tfor (i = 0; i < hw->pf.num_avail_domains; i++) {\n+\t\tlist = &hw->domains[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_domains, list);\n+\t}\n+\n+\thw->pf.num_avail_ldb_queues = DLB2_MAX_NUM_LDB_QUEUES;\n+\tfor (i = 0; i < hw->pf.num_avail_ldb_queues; i++) {\n+\t\tlist = &hw->rsrcs.ldb_queues[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_queues, list);\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->pf.num_avail_ldb_ports[i] =\n+\t\t\tDLB2_MAX_NUM_LDB_PORTS / DLB2_NUM_COS_DOMAINS;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\tint cos_id = i >> DLB2_NUM_COS_DOMAINS;\n+\t\tstruct dlb2_ldb_port *port;\n+\n+\t\tport = &hw->rsrcs.ldb_ports[init_ldb_port_allocation[i]];\n+\n+\t\tdlb2_list_add(&hw->pf.avail_ldb_ports[cos_id],\n+\t\t\t &port->func_list);\n+\t}\n+\n+\thw->pf.num_avail_dir_pq_pairs = DLB2_MAX_NUM_DIR_PORTS;\n+\tfor (i = 0; i < hw->pf.num_avail_dir_pq_pairs; i++) {\n+\t\tlist = &hw->rsrcs.dir_pq_pairs[i].func_list;\n+\n+\t\tdlb2_list_add(&hw->pf.avail_dir_pq_pairs, list);\n+\t}\n+\n+\thw->pf.num_avail_qed_entries = DLB2_MAX_NUM_LDB_CREDITS;\n+\thw->pf.num_avail_dqed_entries = DLB2_MAX_NUM_DIR_CREDITS;\n+\thw->pf.num_avail_aqed_entries = DLB2_MAX_NUM_AQED_ENTRIES;\n+\n+\tret = dlb2_bitmap_alloc(&hw->pf.avail_hist_list_entries,\n+\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tret = dlb2_bitmap_fill(hw->pf.avail_hist_list_entries);\n+\tif (ret)\n+\t\tgoto unwind;\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_VDEVS; i++) {\n+\t\tret = dlb2_bitmap_alloc(&hw->vdev[i].avail_hist_list_entries,\n+\t\t\t\t\tDLB2_MAX_NUM_HIST_LIST_ENTRIES);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\n+\t\tret = dlb2_bitmap_zero(hw->vdev[i].avail_hist_list_entries);\n+\t\tif (ret)\n+\t\t\tgoto unwind;\n+\t}\n+\n+\t/* Initialize the hardware resource IDs */\n+\tfor (i = 0; i < DLB2_MAX_NUM_DOMAINS; i++) {\n+\t\thw->domains[i].id.phys_id = i;\n+\t\thw->domains[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_QUEUES; i++) {\n+\t\thw->rsrcs.ldb_queues[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_queues[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_LDB_PORTS; i++) {\n+\t\thw->rsrcs.ldb_ports[i].id.phys_id = i;\n+\t\thw->rsrcs.ldb_ports[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_DIR_PORTS; i++) {\n+\t\thw->rsrcs.dir_pq_pairs[i].id.phys_id = i;\n+\t\thw->rsrcs.dir_pq_pairs[i].id.vdev_owned = false;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_MAX_NUM_SEQUENCE_NUMBER_GROUPS; i++) {\n+\t\thw->rsrcs.sn_groups[i].id = i;\n+\t\t/* Default mode (0) is 64 sequence numbers per queue */\n+\t\thw->rsrcs.sn_groups[i].mode = 0;\n+\t\thw->rsrcs.sn_groups[i].sequence_numbers_per_queue = 64;\n+\t\thw->rsrcs.sn_groups[i].slot_use_bitmap = 0;\n+\t}\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\thw->cos_reservation[i] = 100 / DLB2_NUM_COS_DOMAINS;\n+\n+\treturn 0;\n+\n+unwind:\n+\tdlb2_resource_free(hw);\n+\n+\treturn ret;\n+}\n+\n+void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw)\n+{\n+\tunion dlb2_cfg_mstr_cfg_pm_pmcsr_disable r0;\n+\n+\tr0.val = DLB2_CSR_RD(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE);\n+\n+\tr0.field.disable = 0;\n+\n+\tDLB2_CSR_WR(hw, DLB2_CFG_MSTR_CFG_PM_PMCSR_DISABLE, r0.val);\n+}\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c\nindex 3c51cab..210b3186 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.c\n+++ b/drivers/event/dlb2/pf/dlb2_main.c\n@@ -19,6 +19,7 @@\n #include \"dlb2_main.h\"\n #include \"../dlb2_user.h\"\n #include \"../dlb2_priv.h\"\n+#include \"../dlb2_iface.h\"\n #include \"../dlb2_inline_fns.h\"\n \n #define PF_ID_ZERO 0\t/* PF ONLY! */\n@@ -72,27 +73,6 @@\n #define DLB2_PCI_ACS_UF 0x10\n #define DLB2_PCI_ACS_EC 0x20\n \n-/* Stubs: Allow building partial probe patch */\n-void dlb2_resource_free(struct dlb2_hw *hw)\n-{\n-\tRTE_SET_USED(hw);\n-}\n-\n-int dlb2_resource_init(struct dlb2_hw *hw)\n-{\n-\tint ret = 0;\n-\tRTE_SET_USED(hw);\n-\n-\treturn ret;\n-}\n-\n-void dlb2_clr_pmcsr_disable(struct dlb2_hw *hw)\n-{\n-\tRTE_SET_USED(hw);\n-}\n-\n-/* End stubs */\n-\n static int\n dlb2_pci_find_ext_capability(struct rte_pci_device *pdev, uint32_t id)\n {\n@@ -149,7 +129,6 @@ static int\n dlb2_pf_init_driver_state(struct dlb2_dev *dlb2_dev)\n {\n \trte_spinlock_init(&dlb2_dev->resource_mutex);\n-\trte_spinlock_init(&dlb2_dev->measurement_lock);\n \n \treturn 0;\n }\ndiff --git a/drivers/event/dlb2/pf/dlb2_main.h b/drivers/event/dlb2/pf/dlb2_main.h\nindex f082a94..f3bee71 100644\n--- a/drivers/event/dlb2/pf/dlb2_main.h\n+++ b/drivers/event/dlb2/pf/dlb2_main.h\n@@ -38,7 +38,6 @@ struct dlb2_dev {\n \t * hardware registers.\n \t */\n \trte_spinlock_t resource_mutex;\n-\trte_spinlock_t measurement_lock;\n \tbool worker_launched;\n \tu8 revision;\n };\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex ae4d785..7d64309 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -32,6 +32,7 @@\n #include <rte_string_fns.h>\n \n #include \"../dlb2_priv.h\"\n+#include \"../dlb2_iface.h\"\n #include \"../dlb2_inline_fns.h\"\n #include \"dlb2_main.h\"\n #include \"base/dlb2_hw_types.h\"\n@@ -40,35 +41,82 @@\n \n static const char *event_dlb2_pf_name = RTE_STR(EVDEV_DLB2_NAME_PMD);\n \n-/* Stubs: Allow building partial probe patch */\n-int dlb2_hw_get_num_resources(struct dlb2_hw *hw,\n-\t\t\t struct dlb2_get_num_resources_args *arg,\n-\t\t\t bool vdev_req,\n-\t\t\t unsigned int vdev_id)\n+static void\n+dlb2_pf_low_level_io_init(void)\n+{\n+\tint i;\n+\t/* Addresses will be initialized at port create */\n+\tfor (i = 0; i < DLB2_MAX_NUM_PORTS; i++) {\n+\t\t/* First directed ports */\n+\t\tdlb2_port[i][DLB2_DIR_PORT].pp_addr = NULL;\n+\t\tdlb2_port[i][DLB2_DIR_PORT].cq_base = NULL;\n+\t\tdlb2_port[i][DLB2_DIR_PORT].mmaped = true;\n+\n+\t\t/* Now load balanced ports */\n+\t\tdlb2_port[i][DLB2_LDB_PORT].pp_addr = NULL;\n+\t\tdlb2_port[i][DLB2_LDB_PORT].cq_base = NULL;\n+\t\tdlb2_port[i][DLB2_LDB_PORT].mmaped = true;\n+\t}\n+}\n+\n+static int\n+dlb2_pf_open(struct dlb2_hw_dev *handle, const char *name)\n+{\n+\tRTE_SET_USED(handle);\n+\tRTE_SET_USED(name);\n+\n+\treturn 0;\n+}\n+\n+static int\n+dlb2_pf_get_device_version(struct dlb2_hw_dev *handle,\n+\t\t\t uint8_t *revision)\n {\n-\tRTE_SET_USED(hw);\n-\tRTE_SET_USED(arg);\n-\tRTE_SET_USED(vdev_req);\n-\tRTE_SET_USED(vdev_id);\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\t*revision = dlb2_dev->revision;\n \n \treturn 0;\n }\n \n-void dlb2_hw_enable_sparse_ldb_cq_mode(struct dlb2_hw *hw)\n+static void\n+dlb2_pf_hardware_init(struct dlb2_hw_dev *handle)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\tdlb2_hw_enable_sparse_ldb_cq_mode(&dlb2_dev->hw);\n+\tdlb2_hw_enable_sparse_dir_cq_mode(&dlb2_dev->hw);\n+}\n+\n+static int\n+dlb2_pf_get_num_resources(struct dlb2_hw_dev *handle,\n+\t\t\t struct dlb2_get_num_resources_args *rsrcs)\n {\n-\tRTE_SET_USED(hw);\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\n+\treturn dlb2_hw_get_num_resources(&dlb2_dev->hw, rsrcs, false, 0);\n }\n \n-void dlb2_hw_enable_sparse_dir_cq_mode(struct dlb2_hw *hw)\n+static int\n+dlb2_pf_get_cq_poll_mode(struct dlb2_hw_dev *handle,\n+\t\t\t enum dlb2_cq_poll_modes *mode)\n {\n-\tRTE_SET_USED(hw);\n+\tRTE_SET_USED(handle);\n+\n+\t*mode = DLB2_CQ_POLL_MODE_SPARSE;\n+\n+\treturn 0;\n }\n-/* End stubs */\n \n static void\n dlb2_pf_iface_fn_ptrs_init(void)\n {\n-/* flexible iface fn ptr assignments will go here */\n+\tdlb2_iface_low_level_io_init = dlb2_pf_low_level_io_init;\n+\tdlb2_iface_open = dlb2_pf_open;\n+\tdlb2_iface_get_device_version = dlb2_pf_get_device_version;\n+\tdlb2_iface_hardware_init = dlb2_pf_hardware_init;\n+\tdlb2_iface_get_num_resources = dlb2_pf_get_num_resources;\n+\tdlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;\n }\n \n /* PCI DEV HOOKS */\n", "prefixes": [ "v9", "08/23" ] }