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GET /api/patches/82950/?format=api
{ "id": 82950, "url": "https://patches.dpdk.org/api/patches/82950/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1604061740-2868-19-git-send-email-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1604061740-2868-19-git-send-email-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1604061740-2868-19-git-send-email-timothy.mcdaniel@intel.com", "date": "2020-10-30T12:42:14", "name": "[v9,18/23] event/dlb: add dequeue and its burst variants", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0260d6553da910529f9cff5a563a0785ba30ba1e", "submitter": { "id": 826, "url": "https://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1604061740-2868-19-git-send-email-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 13500, "url": "https://patches.dpdk.org/api/series/13500/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=13500", "date": "2020-10-30T12:41:57", "name": "Add DLB PMD", "version": 9, "mbox": "https://patches.dpdk.org/series/13500/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/82950/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/82950/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3F5C7A04DE;\n\tFri, 30 Oct 2020 13:49:14 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0AE50CA9D;\n\tFri, 30 Oct 2020 13:41:22 +0100 (CET)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 0433AC922\n for <dev@dpdk.org>; Fri, 30 Oct 2020 13:40:48 +0100 (CET)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Oct 2020 05:40:48 -0700", "from txasoft-yocto.an.intel.com ([10.123.72.192])\n by fmsmga004.fm.intel.com with ESMTP; 30 Oct 2020 05:40:47 -0700" ], "IronPort-SDR": [ "\n DH+5f1kLfZ06rMYJdxSS+saHcGDEghfZ9jB6whbM+lMLMI5kmrl5woZXjK+qlRoP29zMnqdWWv\n swv1Yty3WoBw==", "\n jjE5pZAha0ZpSIxbfBl1+aX+Vj0Lli/XPbM6HrIg/rkczzVBBVi/n/Dre2yzmiOFzVA8Ban6PT\n HdHtrbqNEbQQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9789\"; a=\"156373924\"", "E=Sophos;i=\"5.77,433,1596524400\"; d=\"scan'208\";a=\"156373924\"", "E=Sophos;i=\"5.77,433,1596524400\"; d=\"scan'208\";a=\"351849689\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "", "Cc": "dev@dpdk.org, erik.g.carrillo@intel.com, gage.eads@intel.com,\n harry.van.haaren@intel.com, jerinj@marvell.com, thomas@monjalon.net", "Date": "Fri, 30 Oct 2020 07:42:14 -0500", "Message-Id": "<1604061740-2868-19-git-send-email-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 1.7.10", "In-Reply-To": "<1604061740-2868-1-git-send-email-timothy.mcdaniel@intel.com>", "References": "<20200612212434.6852-2-timothy.mcdaniel@intel.com>\n <1604061740-2868-1-git-send-email-timothy.mcdaniel@intel.com>", "Subject": "[dpdk-dev] [PATCH v9 18/23] event/dlb: add dequeue and its burst\n\tvariants", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for dequeue, dequeue_burst, ...\n\nDLB does not currently support interrupts, but instead uses\numonitor/umwait if supported by the processor. This allows\nthe software to monitor and wait on writes to a cache-line.\n\nDLB supports normal and sparse cq mode. In normal mode the\nhardware will pack 4 QEs into each cache line. In sparse cq\nmode, the hardware will only populate one QE per cache line.\nSoftware must be aware of the cq mode, and take the appropriate\nactions, based on the mode.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n---\n doc/guides/eventdevs/dlb.rst | 21 ++\n drivers/event/dlb/dlb.c | 728 +++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 749 insertions(+)", "diff": "diff --git a/doc/guides/eventdevs/dlb.rst b/doc/guides/eventdevs/dlb.rst\nindex ae126c4..4c4f56b 100644\n--- a/doc/guides/eventdevs/dlb.rst\n+++ b/doc/guides/eventdevs/dlb.rst\n@@ -318,3 +318,24 @@ increase a vdev's per-queue atomic-inflight allocation to (for example) 64:\n \n --vdev=dlb1_event,atm_inflights=64\n \n+Deferred Scheduling\n+~~~~~~~~~~~~~~~~~~~\n+\n+The DLB PMD's default behavior for managing a CQ is to \"pop\" the CQ once per\n+dequeued event before returning from rte_event_dequeue_burst(). This frees the\n+corresponding entries in the CQ, which enables the DLB to schedule more events\n+to it.\n+\n+To support applications seeking finer-grained scheduling control -- for example\n+deferring scheduling to get the best possible priority scheduling and\n+load-balancing -- the PMD supports a deferred scheduling mode. In this mode,\n+the CQ entry is not popped until the *subsequent* rte_event_dequeue_burst()\n+call. This mode only applies to load-balanced event ports with dequeue depth of\n+1.\n+\n+To enable deferred scheduling, use the defer_sched vdev argument like so:\n+\n+ .. code-block:: console\n+\n+ --vdev=dlb1_event,defer_sched=on\n+\ndiff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nindex 4d65a7f..c022139 100644\n--- a/drivers/event/dlb/dlb.c\n+++ b/drivers/event/dlb/dlb.c\n@@ -2812,9 +2812,728 @@ dlb_event_enqueue_forward_burst_delayed(void *event_port,\n \treturn __dlb_event_enqueue_burst(event_port, events, num);\n }\n \n+static __rte_always_inline int\n+dlb_recv_qe(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe,\n+\t uint8_t *offset)\n+{\n+\tuint8_t xor_mask[2][4] = { {0x0F, 0x0E, 0x0C, 0x08},\n+\t\t\t\t {0x00, 0x01, 0x03, 0x07} };\n+\tuint8_t and_mask[4] = {0x0F, 0x0E, 0x0C, 0x08};\n+\tvolatile struct dlb_dequeue_qe *cq_addr;\n+\t__m128i *qes = (__m128i *)qe;\n+\tuint64_t *cache_line_base;\n+\tuint8_t gen_bits;\n+\n+\tcq_addr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base;\n+\tcq_addr = &cq_addr[qm_port->cq_idx];\n+\n+\tcache_line_base = (void *)(((uintptr_t)cq_addr) & ~0x3F);\n+\t*offset = ((uintptr_t)cq_addr & 0x30) >> 4;\n+\n+\t/* Load the next CQ cache line from memory. Pack these reads as tight\n+\t * as possible to reduce the chance that DLB invalidates the line while\n+\t * the CPU is reading it. Read the cache line backwards to ensure that\n+\t * if QE[N] (N > 0) is valid, then QEs[0:N-1] are too.\n+\t *\n+\t * (Valid QEs start at &qe[offset])\n+\t */\n+\tqes[3] = _mm_load_si128((__m128i *)&cache_line_base[6]);\n+\tqes[2] = _mm_load_si128((__m128i *)&cache_line_base[4]);\n+\tqes[1] = _mm_load_si128((__m128i *)&cache_line_base[2]);\n+\tqes[0] = _mm_load_si128((__m128i *)&cache_line_base[0]);\n+\n+\t/* Evict the cache line ASAP */\n+\tdlb_cldemote(cache_line_base);\n+\n+\t/* Extract and combine the gen bits */\n+\tgen_bits = ((_mm_extract_epi8(qes[0], 15) & 0x1) << 0) |\n+\t\t ((_mm_extract_epi8(qes[1], 15) & 0x1) << 1) |\n+\t\t ((_mm_extract_epi8(qes[2], 15) & 0x1) << 2) |\n+\t\t ((_mm_extract_epi8(qes[3], 15) & 0x1) << 3);\n+\n+\t/* XOR the combined bits such that a 1 represents a valid QE */\n+\tgen_bits ^= xor_mask[qm_port->gen_bit][*offset];\n+\n+\t/* Mask off gen bits we don't care about */\n+\tgen_bits &= and_mask[*offset];\n+\n+\treturn __builtin_popcount(gen_bits);\n+}\n+\n+static inline void\n+dlb_inc_cq_idx(struct dlb_port *qm_port, int cnt)\n+{\n+\tuint16_t idx = qm_port->cq_idx_unmasked + cnt;\n+\n+\tqm_port->cq_idx_unmasked = idx;\n+\tqm_port->cq_idx = idx & qm_port->cq_depth_mask;\n+\tqm_port->gen_bit = (~(idx >> qm_port->gen_bit_shift)) & 0x1;\n+}\n+\n+static inline int\n+dlb_process_dequeue_qes(struct dlb_eventdev_port *ev_port,\n+\t\t\tstruct dlb_port *qm_port,\n+\t\t\tstruct rte_event *events,\n+\t\t\tstruct dlb_dequeue_qe *qes,\n+\t\t\tint cnt)\n+{\n+\tuint8_t *qid_mappings = qm_port->qid_mappings;\n+\tint i, num;\n+\n+\tRTE_SET_USED(ev_port); /* avoids unused variable error */\n+\n+\tfor (i = 0, num = 0; i < cnt; i++) {\n+\t\tstruct dlb_dequeue_qe *qe = &qes[i];\n+\t\tint sched_type_map[4] = {\n+\t\t\t[DLB_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC,\n+\t\t\t[DLB_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL,\n+\t\t\t[DLB_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED,\n+\t\t\t[DLB_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC,\n+\t\t};\n+\n+\t\tDLB_LOG_DBG(\"dequeue success, data = 0x%llx, qid=%d, event_type=%d, subevent=%d\\npp_id = %d, sched_type = %d, qid = %d, err=%d\\n\",\n+\t\t\t (long long)qe->data, qe->qid,\n+\t\t\t qe->u.event_type.major,\n+\t\t\t qe->u.event_type.sub,\n+\t\t\t qe->pp_id, qe->sched_type, qe->qid, qe->error);\n+\n+\t\t/* Fill in event information.\n+\t\t * Note that flow_id must be embedded in the data by\n+\t\t * the app, such as the mbuf RSS hash field if the data\n+\t\t * buffer is a mbuf.\n+\t\t */\n+\t\tif (unlikely(qe->error)) {\n+\t\t\tDLB_LOG_ERR(\"QE error bit ON\\n\");\n+\t\t\tDLB_INC_STAT(ev_port->stats.traffic.rx_drop, 1);\n+\t\t\tdlb_consume_qe_immediate(qm_port, 1);\n+\t\t\tcontinue; /* Ignore */\n+\t\t}\n+\n+\t\tevents[num].u64 = qe->data;\n+\t\tevents[num].queue_id = qid_mappings[qe->qid];\n+\t\tevents[num].priority = DLB_TO_EV_PRIO((uint8_t)qe->priority);\n+\t\tevents[num].event_type = qe->u.event_type.major;\n+\t\tevents[num].sub_event_type = qe->u.event_type.sub;\n+\t\tevents[num].sched_type = sched_type_map[qe->sched_type];\n+\t\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qe->sched_type], 1);\n+\t\tnum++;\n+\t}\n+\tDLB_INC_STAT(ev_port->stats.traffic.rx_ok, num);\n+\n+\treturn num;\n+}\n+\n+static inline int\n+dlb_process_dequeue_four_qes(struct dlb_eventdev_port *ev_port,\n+\t\t\t struct dlb_port *qm_port,\n+\t\t\t struct rte_event *events,\n+\t\t\t struct dlb_dequeue_qe *qes)\n+{\n+\tint sched_type_map[] = {\n+\t\t[DLB_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC,\n+\t\t[DLB_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL,\n+\t\t[DLB_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED,\n+\t\t[DLB_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC,\n+\t};\n+\tconst int num_events = DLB_NUM_QES_PER_CACHE_LINE;\n+\tuint8_t *qid_mappings = qm_port->qid_mappings;\n+\t__m128i sse_evt[2];\n+\tint i;\n+\n+\t/* In the unlikely case that any of the QE error bits are set, process\n+\t * them one at a time.\n+\t */\n+\tif (unlikely(qes[0].error || qes[1].error ||\n+\t\t qes[2].error || qes[3].error))\n+\t\treturn dlb_process_dequeue_qes(ev_port, qm_port, events,\n+\t\t\t\t\t qes, num_events);\n+\n+\tfor (i = 0; i < DLB_NUM_QES_PER_CACHE_LINE; i++) {\n+\t\tDLB_LOG_DBG(\"dequeue success, data = 0x%llx, qid=%d, event_type=%d, subevent=%d\\npp_id = %d, sched_type = %d, qid = %d, err=%d\\n\",\n+\t\t\t (long long)qes[i].data, qes[i].qid,\n+\t\t\t qes[i].u.event_type.major,\n+\t\t\t qes[i].u.event_type.sub,\n+\t\t\t qes[i].pp_id, qes[i].sched_type, qes[i].qid,\n+\t\t\t qes[i].error);\n+\t}\n+\n+\tevents[0].u64 = qes[0].data;\n+\tevents[1].u64 = qes[1].data;\n+\tevents[2].u64 = qes[2].data;\n+\tevents[3].u64 = qes[3].data;\n+\n+\t/* Construct the metadata portion of two struct rte_events\n+\t * in one 128b SSE register. Event metadata is constructed in the SSE\n+\t * registers like so:\n+\t * sse_evt[0][63:0]: event[0]'s metadata\n+\t * sse_evt[0][127:64]: event[1]'s metadata\n+\t * sse_evt[1][63:0]: event[2]'s metadata\n+\t * sse_evt[1][127:64]: event[3]'s metadata\n+\t */\n+\tsse_evt[0] = _mm_setzero_si128();\n+\tsse_evt[1] = _mm_setzero_si128();\n+\n+\t/* Convert the hardware queue ID to an event queue ID and store it in\n+\t * the metadata:\n+\t * sse_evt[0][47:40] = qid_mappings[qes[0].qid]\n+\t * sse_evt[0][111:104] = qid_mappings[qes[1].qid]\n+\t * sse_evt[1][47:40] = qid_mappings[qes[2].qid]\n+\t * sse_evt[1][111:104] = qid_mappings[qes[3].qid]\n+\t */\n+#define DLB_EVENT_QUEUE_ID_BYTE 5\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\t\t\t qid_mappings[qes[0].qid],\n+\t\t\t\t DLB_EVENT_QUEUE_ID_BYTE);\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\t\t\t qid_mappings[qes[1].qid],\n+\t\t\t\t DLB_EVENT_QUEUE_ID_BYTE + 8);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\t\t\t qid_mappings[qes[2].qid],\n+\t\t\t\t DLB_EVENT_QUEUE_ID_BYTE);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\t\t\t qid_mappings[qes[3].qid],\n+\t\t\t\t DLB_EVENT_QUEUE_ID_BYTE + 8);\n+\n+\t/* Convert the hardware priority to an event priority and store it in\n+\t * the metadata:\n+\t * sse_evt[0][55:48] = DLB_TO_EV_PRIO(qes[0].priority)\n+\t * sse_evt[0][119:112] = DLB_TO_EV_PRIO(qes[1].priority)\n+\t * sse_evt[1][55:48] = DLB_TO_EV_PRIO(qes[2].priority)\n+\t * sse_evt[1][119:112] = DLB_TO_EV_PRIO(qes[3].priority)\n+\t */\n+#define DLB_EVENT_PRIO_BYTE 6\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\t\t\t DLB_TO_EV_PRIO((uint8_t)qes[0].priority),\n+\t\t\t\t DLB_EVENT_PRIO_BYTE);\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\t\t\t DLB_TO_EV_PRIO((uint8_t)qes[1].priority),\n+\t\t\t\t DLB_EVENT_PRIO_BYTE + 8);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\t\t\t DLB_TO_EV_PRIO((uint8_t)qes[2].priority),\n+\t\t\t\t DLB_EVENT_PRIO_BYTE);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\t\t\t DLB_TO_EV_PRIO((uint8_t)qes[3].priority),\n+\t\t\t\t DLB_EVENT_PRIO_BYTE + 8);\n+\n+\t/* Write the event type and sub event type to the event metadata. Leave\n+\t * flow ID unspecified, since the hardware does not maintain it during\n+\t * scheduling:\n+\t * sse_evt[0][31:0] = qes[0].u.event_type.major << 28 |\n+\t *\t\t\tqes[0].u.event_type.sub << 20;\n+\t * sse_evt[0][95:64] = qes[1].u.event_type.major << 28 |\n+\t *\t\t\tqes[1].u.event_type.sub << 20;\n+\t * sse_evt[1][31:0] = qes[2].u.event_type.major << 28 |\n+\t *\t\t\tqes[2].u.event_type.sub << 20;\n+\t * sse_evt[1][95:64] = qes[3].u.event_type.major << 28 |\n+\t *\t\t\tqes[3].u.event_type.sub << 20;\n+\t */\n+#define DLB_EVENT_EV_TYPE_DW 0\n+#define DLB_EVENT_EV_TYPE_SHIFT 28\n+#define DLB_EVENT_SUB_EV_TYPE_SHIFT 20\n+\tsse_evt[0] = _mm_insert_epi32(sse_evt[0],\n+\t\t\tqes[0].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |\n+\t\t\tqes[0].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,\n+\t\t\tDLB_EVENT_EV_TYPE_DW);\n+\tsse_evt[0] = _mm_insert_epi32(sse_evt[0],\n+\t\t\tqes[1].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |\n+\t\t\tqes[1].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,\n+\t\t\tDLB_EVENT_EV_TYPE_DW + 2);\n+\tsse_evt[1] = _mm_insert_epi32(sse_evt[1],\n+\t\t\tqes[2].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |\n+\t\t\tqes[2].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,\n+\t\t\tDLB_EVENT_EV_TYPE_DW);\n+\tsse_evt[1] = _mm_insert_epi32(sse_evt[1],\n+\t\t\tqes[3].u.event_type.major << DLB_EVENT_EV_TYPE_SHIFT |\n+\t\t\tqes[3].u.event_type.sub << DLB_EVENT_SUB_EV_TYPE_SHIFT,\n+\t\t\tDLB_EVENT_EV_TYPE_DW + 2);\n+\n+\t/* Write the sched type to the event metadata. 'op' and 'rsvd' are not\n+\t * set:\n+\t * sse_evt[0][39:32] = sched_type_map[qes[0].sched_type] << 6\n+\t * sse_evt[0][103:96] = sched_type_map[qes[1].sched_type] << 6\n+\t * sse_evt[1][39:32] = sched_type_map[qes[2].sched_type] << 6\n+\t * sse_evt[1][103:96] = sched_type_map[qes[3].sched_type] << 6\n+\t */\n+#define DLB_EVENT_SCHED_TYPE_BYTE 4\n+#define DLB_EVENT_SCHED_TYPE_SHIFT 6\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\tsched_type_map[qes[0].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,\n+\t\tDLB_EVENT_SCHED_TYPE_BYTE);\n+\tsse_evt[0] = _mm_insert_epi8(sse_evt[0],\n+\t\tsched_type_map[qes[1].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,\n+\t\tDLB_EVENT_SCHED_TYPE_BYTE + 8);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\tsched_type_map[qes[2].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,\n+\t\tDLB_EVENT_SCHED_TYPE_BYTE);\n+\tsse_evt[1] = _mm_insert_epi8(sse_evt[1],\n+\t\tsched_type_map[qes[3].sched_type] << DLB_EVENT_SCHED_TYPE_SHIFT,\n+\t\tDLB_EVENT_SCHED_TYPE_BYTE + 8);\n+\n+\t/* Store the metadata to the event (use the double-precision\n+\t * _mm_storeh_pd because there is no integer function for storing the\n+\t * upper 64b):\n+\t * events[0].event = sse_evt[0][63:0]\n+\t * events[1].event = sse_evt[0][127:64]\n+\t * events[2].event = sse_evt[1][63:0]\n+\t * events[3].event = sse_evt[1][127:64]\n+\t */\n+\t_mm_storel_epi64((__m128i *)&events[0].event, sse_evt[0]);\n+\t_mm_storeh_pd((double *)&events[1].event, (__m128d) sse_evt[0]);\n+\t_mm_storel_epi64((__m128i *)&events[2].event, sse_evt[1]);\n+\t_mm_storeh_pd((double *)&events[3].event, (__m128d) sse_evt[1]);\n+\n+\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[0].sched_type], 1);\n+\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[1].sched_type], 1);\n+\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[2].sched_type], 1);\n+\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qes[3].sched_type], 1);\n+\n+\tDLB_INC_STAT(ev_port->stats.traffic.rx_ok, num_events);\n+\n+\treturn num_events;\n+}\n+\n+static inline bool\n+dlb_cq_is_empty(struct dlb_port *qm_port)\n+{\n+\tvolatile struct dlb_dequeue_qe *qe_ptr;\n+\tstruct dlb_dequeue_qe qe;\n+\n+\tqe_ptr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base;\n+\tqe = qe_ptr[qm_port->cq_idx];\n+\n+\treturn (qe.cq_gen != qm_port->gen_bit);\n+}\n+\n+static inline int\n+dlb_dequeue_wait(struct dlb_eventdev *dlb,\n+\t\t struct dlb_eventdev_port *ev_port,\n+\t\t struct dlb_port *qm_port,\n+\t\t uint64_t timeout,\n+\t\t uint64_t start_ticks)\n+{\n+\tstruct process_local_port_data *port_data;\n+\tuint64_t elapsed_ticks;\n+\n+\tport_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];\n+\n+\telapsed_ticks = rte_get_timer_cycles() - start_ticks;\n+\n+\t/* Wait/poll time expired */\n+\tif (elapsed_ticks >= timeout) {\n+\t\t/* Interrupts not supported by PF PMD */\n+\t\treturn 1;\n+\t} else if (dlb->umwait_allowed) {\n+\t\tvolatile struct dlb_dequeue_qe *cq_base;\n+\n+\t\tcq_base = port_data->cq_base;\n+\n+\t\t/* Block on cache line write to CQ. Note: it's\n+\t\t * safe to access the per-process cq_base\n+\t\t * address here, since the PMD has already\n+\t\t * attempted at least one CQ dequeue.\n+\t\t */\n+\t\tdlb_umonitor(&cq_base[qm_port->cq_idx]);\n+\n+\t\t/* Avoid race condition. Check if still empty */\n+\t\tif (dlb_cq_is_empty(qm_port)) {\n+\t\t\tdlb_umwait(RTE_LIBRTE_PMD_DLB_UMWAIT_CTL_STATE,\n+\t\t\t\t timeout + start_ticks);\n+\t\t\tDLB_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait,\n+\t\t\t\t 1);\n+\t\t}\n+\t} else {\n+\t\tuint64_t poll_interval = RTE_LIBRTE_PMD_DLB_POLL_INTERVAL;\n+\t\tuint64_t curr_ticks = rte_get_timer_cycles();\n+\t\tuint64_t init_ticks = curr_ticks;\n+\n+\t\twhile ((curr_ticks - start_ticks < timeout) &&\n+\t\t (curr_ticks - init_ticks < poll_interval))\n+\t\t\tcurr_ticks = rte_get_timer_cycles();\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int16_t\n+dlb_hw_dequeue(struct dlb_eventdev *dlb,\n+\t struct dlb_eventdev_port *ev_port,\n+\t struct rte_event *events,\n+\t uint16_t max_num,\n+\t uint64_t dequeue_timeout_ticks)\n+{\n+\tuint64_t timeout;\n+\tuint64_t start_ticks = 0ULL;\n+\tstruct dlb_port *qm_port;\n+\tint num = 0;\n+\n+\tqm_port = &ev_port->qm_port;\n+\n+\t/* If configured for per dequeue wait, then use wait value provided\n+\t * to this API. Otherwise we must use the global\n+\t * value from eventdev config time.\n+\t */\n+\tif (!dlb->global_dequeue_wait)\n+\t\ttimeout = dequeue_timeout_ticks;\n+\telse\n+\t\ttimeout = dlb->global_dequeue_wait_ticks;\n+\n+\tif (timeout)\n+\t\tstart_ticks = rte_get_timer_cycles();\n+\n+\twhile (num < max_num) {\n+\t\tstruct dlb_dequeue_qe qes[DLB_NUM_QES_PER_CACHE_LINE];\n+\t\tuint8_t offset;\n+\t\tint num_avail;\n+\n+\t\t/* Copy up to 4 QEs from the current cache line into qes */\n+\t\tnum_avail = dlb_recv_qe(qm_port, qes, &offset);\n+\n+\t\t/* But don't process more than the user requested */\n+\t\tnum_avail = RTE_MIN(num_avail, max_num - num);\n+\n+\t\tdlb_inc_cq_idx(qm_port, num_avail);\n+\n+\t\tif (num_avail == DLB_NUM_QES_PER_CACHE_LINE)\n+\t\t\tnum += dlb_process_dequeue_four_qes(ev_port,\n+\t\t\t\t\t\t\t qm_port,\n+\t\t\t\t\t\t\t &events[num],\n+\t\t\t\t\t\t\t &qes[offset]);\n+\t\telse if (num_avail)\n+\t\t\tnum += dlb_process_dequeue_qes(ev_port,\n+\t\t\t\t\t\t\tqm_port,\n+\t\t\t\t\t\t\t&events[num],\n+\t\t\t\t\t\t\t&qes[offset],\n+\t\t\t\t\t\t\tnum_avail);\n+\t\telse if ((timeout == 0) || (num > 0))\n+\t\t\t/* Not waiting in any form, or 1+ events received? */\n+\t\t\tbreak;\n+\t\telse if (dlb_dequeue_wait(dlb, ev_port, qm_port,\n+\t\t\t\t\t timeout, start_ticks))\n+\t\t\tbreak;\n+\t}\n+\n+\tqm_port->owed_tokens += num;\n+\n+\tdlb_consume_qe_immediate(qm_port, num);\n+\n+\tev_port->outstanding_releases += num;\n+\n+\treturn num;\n+}\n+\n+static inline int\n+dlb_process_dequeue_qe(struct dlb_eventdev_port *ev_port __rte_unused,\n+\t\t struct dlb_port *qm_port,\n+\t\t struct rte_event *event,\n+\t\t struct dlb_dequeue_qe *qe)\n+{\n+\tint sched_type_map[4] = {\n+\t\t[DLB_SCHED_ATOMIC] = RTE_SCHED_TYPE_ATOMIC,\n+\t\t[DLB_SCHED_UNORDERED] = RTE_SCHED_TYPE_PARALLEL,\n+\t\t[DLB_SCHED_ORDERED] = RTE_SCHED_TYPE_ORDERED,\n+\t\t[DLB_SCHED_DIRECTED] = RTE_SCHED_TYPE_ATOMIC,\n+\t};\n+\tuint8_t *qid_mappings = qm_port->qid_mappings;\n+\n+\tDLB_LOG_DBG(\"dequeue success, data = 0x%llx, qid=%d, event_type=%d, subevent=%d\\npp_id = %d, sched_type = %d, qid = %d, err=%d\\n\",\n+\t\t (long long)qe->data, qe->qid,\n+\t\t qe->u.event_type.major,\n+\t\t qe->u.event_type.sub,\n+\t\t qe->pp_id, qe->sched_type, qe->qid, qe->error);\n+\n+\t/* Fill in event information.\n+\t * Note that flow_id must be embedded in the data by\n+\t * the app, such as the mbuf RSS hash field if the data\n+\t * buffer is a mbuf.\n+\t */\n+\tif (unlikely(qe->error)) {\n+\t\tDLB_LOG_ERR(\"QE error bit ON\\n\");\n+\t\tDLB_INC_STAT(ev_port->stats.traffic.rx_drop, 1);\n+\t\tdlb_consume_qe_immediate(qm_port, 1);\n+\t\treturn 0;\n+\t}\n+\n+\tevent->u64 = qe->data;\n+\tevent->queue_id = qid_mappings[qe->qid];\n+\tevent->priority = DLB_TO_EV_PRIO((uint8_t)qe->priority);\n+\tevent->event_type = qe->u.event_type.major;\n+\tevent->sub_event_type = qe->u.event_type.sub;\n+\tevent->sched_type = sched_type_map[qe->sched_type];\n+\tDLB_INC_STAT(ev_port->stats.rx_sched_cnt[qe->sched_type], 1);\n+\n+\tDLB_INC_STAT(ev_port->stats.traffic.rx_ok, 1);\n+\n+\treturn 1;\n+}\n+\n+static __rte_always_inline int\n+dlb_recv_qe_sparse(struct dlb_port *qm_port, struct dlb_dequeue_qe *qe)\n+{\n+\tvolatile struct dlb_dequeue_qe *cq_addr;\n+\tuint8_t xor_mask[2] = {0x0F, 0x00};\n+\tconst uint8_t and_mask = 0x0F;\n+\t__m128i *qes = (__m128i *)qe;\n+\tuint8_t gen_bits, gen_bit;\n+\tuintptr_t addr[4];\n+\tuint16_t idx;\n+\n+\tcq_addr = dlb_port[qm_port->id][PORT_TYPE(qm_port)].cq_base;\n+\n+\tidx = qm_port->cq_idx;\n+\n+\t/* Load the next 4 QEs */\n+\taddr[0] = (uintptr_t)&cq_addr[idx];\n+\taddr[1] = (uintptr_t)&cq_addr[(idx + 4) & qm_port->cq_depth_mask];\n+\taddr[2] = (uintptr_t)&cq_addr[(idx + 8) & qm_port->cq_depth_mask];\n+\taddr[3] = (uintptr_t)&cq_addr[(idx + 12) & qm_port->cq_depth_mask];\n+\n+\t/* Prefetch next batch of QEs (all CQs occupy minimum 8 cache lines) */\n+\trte_prefetch0(&cq_addr[(idx + 16) & qm_port->cq_depth_mask]);\n+\trte_prefetch0(&cq_addr[(idx + 20) & qm_port->cq_depth_mask]);\n+\trte_prefetch0(&cq_addr[(idx + 24) & qm_port->cq_depth_mask]);\n+\trte_prefetch0(&cq_addr[(idx + 28) & qm_port->cq_depth_mask]);\n+\n+\t/* Correct the xor_mask for wrap-around QEs */\n+\tgen_bit = qm_port->gen_bit;\n+\txor_mask[gen_bit] ^= !!((idx + 4) > qm_port->cq_depth_mask) << 1;\n+\txor_mask[gen_bit] ^= !!((idx + 8) > qm_port->cq_depth_mask) << 2;\n+\txor_mask[gen_bit] ^= !!((idx + 12) > qm_port->cq_depth_mask) << 3;\n+\n+\t/* Read the cache lines backwards to ensure that if QE[N] (N > 0) is\n+\t * valid, then QEs[0:N-1] are too.\n+\t */\n+\tqes[3] = _mm_load_si128((__m128i *)(void *)addr[3]);\n+\trte_compiler_barrier();\n+\tqes[2] = _mm_load_si128((__m128i *)(void *)addr[2]);\n+\trte_compiler_barrier();\n+\tqes[1] = _mm_load_si128((__m128i *)(void *)addr[1]);\n+\trte_compiler_barrier();\n+\tqes[0] = _mm_load_si128((__m128i *)(void *)addr[0]);\n+\n+\t/* Extract and combine the gen bits */\n+\tgen_bits = ((_mm_extract_epi8(qes[0], 15) & 0x1) << 0) |\n+\t\t ((_mm_extract_epi8(qes[1], 15) & 0x1) << 1) |\n+\t\t ((_mm_extract_epi8(qes[2], 15) & 0x1) << 2) |\n+\t\t ((_mm_extract_epi8(qes[3], 15) & 0x1) << 3);\n+\n+\t/* XOR the combined bits such that a 1 represents a valid QE */\n+\tgen_bits ^= xor_mask[gen_bit];\n+\n+\t/* Mask off gen bits we don't care about */\n+\tgen_bits &= and_mask;\n+\n+\treturn __builtin_popcount(gen_bits);\n+}\n+\n+static inline int16_t\n+dlb_hw_dequeue_sparse(struct dlb_eventdev *dlb,\n+\t\t struct dlb_eventdev_port *ev_port,\n+\t\t struct rte_event *events,\n+\t\t uint16_t max_num,\n+\t\t uint64_t dequeue_timeout_ticks)\n+{\n+\tuint64_t timeout;\n+\tuint64_t start_ticks = 0ULL;\n+\tstruct dlb_port *qm_port;\n+\tint num = 0;\n+\n+\tqm_port = &ev_port->qm_port;\n+\n+\t/* If configured for per dequeue wait, then use wait value provided\n+\t * to this API. Otherwise we must use the global\n+\t * value from eventdev config time.\n+\t */\n+\tif (!dlb->global_dequeue_wait)\n+\t\ttimeout = dequeue_timeout_ticks;\n+\telse\n+\t\ttimeout = dlb->global_dequeue_wait_ticks;\n+\n+\tif (timeout)\n+\t\tstart_ticks = rte_get_timer_cycles();\n+\n+\twhile (num < max_num) {\n+\t\tstruct dlb_dequeue_qe qes[DLB_NUM_QES_PER_CACHE_LINE];\n+\t\tint num_avail;\n+\n+\t\t/* Copy up to 4 QEs from the current cache line into qes */\n+\t\tnum_avail = dlb_recv_qe_sparse(qm_port, qes);\n+\n+\t\t/* But don't process more than the user requested */\n+\t\tnum_avail = RTE_MIN(num_avail, max_num - num);\n+\n+\t\tdlb_inc_cq_idx(qm_port, num_avail << 2);\n+\n+\t\tif (num_avail == DLB_NUM_QES_PER_CACHE_LINE)\n+\t\t\tnum += dlb_process_dequeue_four_qes(ev_port,\n+\t\t\t\t\t\t\t qm_port,\n+\t\t\t\t\t\t\t &events[num],\n+\t\t\t\t\t\t\t &qes[0]);\n+\t\telse if (num_avail)\n+\t\t\tnum += dlb_process_dequeue_qes(ev_port,\n+\t\t\t\t\t\t\tqm_port,\n+\t\t\t\t\t\t\t&events[num],\n+\t\t\t\t\t\t\t&qes[0],\n+\t\t\t\t\t\t\tnum_avail);\n+\t\telse if ((timeout == 0) || (num > 0))\n+\t\t\t/* Not waiting in any form, or 1+ events received? */\n+\t\t\tbreak;\n+\t\telse if (dlb_dequeue_wait(dlb, ev_port, qm_port,\n+\t\t\t\t\t timeout, start_ticks))\n+\t\t\tbreak;\n+\t}\n+\n+\tqm_port->owed_tokens += num;\n+\n+\tdlb_consume_qe_immediate(qm_port, num);\n+\n+\tev_port->outstanding_releases += num;\n+\n+\treturn num;\n+}\n+\n+static int\n+dlb_event_release(struct dlb_eventdev *dlb, uint8_t port_id, int n)\n+{\n+\tstruct process_local_port_data *port_data;\n+\tstruct dlb_eventdev_port *ev_port;\n+\tstruct dlb_port *qm_port;\n+\tint i;\n+\n+\tif (port_id > dlb->num_ports) {\n+\t\tDLB_LOG_ERR(\"Invalid port id %d in dlb-event_release\\n\",\n+\t\t\t port_id);\n+\t\trte_errno = -EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tev_port = &dlb->ev_ports[port_id];\n+\tqm_port = &ev_port->qm_port;\n+\tport_data = &dlb_port[qm_port->id][PORT_TYPE(qm_port)];\n+\n+\ti = 0;\n+\n+\tif (qm_port->is_directed) {\n+\t\ti = n;\n+\t\tgoto sw_credit_update;\n+\t}\n+\n+\twhile (i < n) {\n+\t\tint pop_offs = 0;\n+\t\tint j = 0;\n+\n+\t\t/* Zero-out QEs */\n+\t\tqm_port->qe4[0].cmd_byte = 0;\n+\t\tqm_port->qe4[1].cmd_byte = 0;\n+\t\tqm_port->qe4[2].cmd_byte = 0;\n+\t\tqm_port->qe4[3].cmd_byte = 0;\n+\n+\t\tfor (; j < DLB_NUM_QES_PER_CACHE_LINE && (i + j) < n; j++) {\n+\n+\t\t\tqm_port->qe4[j].cmd_byte = DLB_COMP_CMD_BYTE;\n+\t\t\tqm_port->issued_releases++;\n+\t\t}\n+\n+\t\tdlb_hw_do_enqueue(qm_port, i == 0, port_data);\n+\n+\t\t/* Don't include the token pop QE in the release count */\n+\t\ti += j - pop_offs;\n+\t}\n+\n+sw_credit_update:\n+\t/* each release returns one credit */\n+\tif (!ev_port->outstanding_releases) {\n+\t\tDLB_LOG_ERR(\"Unrecoverable application error. Outstanding releases underflowed.\\n\");\n+\t\trte_errno = -ENOTRECOVERABLE;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tev_port->outstanding_releases -= i;\n+\tev_port->inflight_credits += i;\n+\n+\t/* Replenish s/w credits if enough releases are performed */\n+\tdlb_replenish_sw_credits(dlb, ev_port);\n+\treturn 0;\n+}\n+\n+static uint16_t\n+dlb_event_dequeue_burst(void *event_port, struct rte_event *ev, uint16_t num,\n+\t\t\tuint64_t wait)\n+{\n+\tstruct dlb_eventdev_port *ev_port = event_port;\n+\tstruct dlb_eventdev *dlb = ev_port->dlb;\n+\tuint16_t cnt;\n+\tint ret;\n+\n+\trte_errno = 0;\n+\n+\tRTE_ASSERT(ev_port->setup_done);\n+\tRTE_ASSERT(ev != NULL);\n+\n+\tif (ev_port->implicit_release && ev_port->outstanding_releases > 0) {\n+\t\tuint16_t out_rels = ev_port->outstanding_releases;\n+\n+\t\tret = dlb_event_release(dlb, ev_port->id, out_rels);\n+\t\tif (ret)\n+\t\t\treturn(ret);\n+\n+\t\tDLB_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels);\n+\t}\n+\n+\tcnt = dlb_hw_dequeue(dlb, ev_port, ev, num, wait);\n+\n+\tDLB_INC_STAT(ev_port->stats.traffic.total_polls, 1);\n+\tDLB_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));\n+\treturn cnt;\n+}\n+\n+static uint16_t\n+dlb_event_dequeue(void *event_port, struct rte_event *ev, uint64_t wait)\n+{\n+\treturn dlb_event_dequeue_burst(event_port, ev, 1, wait);\n+}\n+\n+static uint16_t\n+dlb_event_dequeue_burst_sparse(void *event_port, struct rte_event *ev,\n+\t\t\t uint16_t num, uint64_t wait)\n+{\n+\tstruct dlb_eventdev_port *ev_port = event_port;\n+\tstruct dlb_eventdev *dlb = ev_port->dlb;\n+\tuint16_t cnt;\n+\tint ret;\n+\n+\trte_errno = 0;\n+\n+\tRTE_ASSERT(ev_port->setup_done);\n+\tRTE_ASSERT(ev != NULL);\n+\n+\tif (ev_port->implicit_release && ev_port->outstanding_releases > 0) {\n+\t\tuint16_t out_rels = ev_port->outstanding_releases;\n+\n+\t\tret = dlb_event_release(dlb, ev_port->id, out_rels);\n+\t\tif (ret)\n+\t\t\treturn(ret);\n+\n+\t\tDLB_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels);\n+\t}\n+\n+\tcnt = dlb_hw_dequeue_sparse(dlb, ev_port, ev, num, wait);\n+\n+\tDLB_INC_STAT(ev_port->stats.traffic.total_polls, 1);\n+\tDLB_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));\n+\treturn cnt;\n+}\n+\n+static uint16_t\n+dlb_event_dequeue_sparse(void *event_port, struct rte_event *ev, uint64_t wait)\n+{\n+\treturn dlb_event_dequeue_burst_sparse(event_port, ev, 1, wait);\n+}\n+\n void\n dlb_entry_points_init(struct rte_eventdev *dev)\n {\n+\tstruct dlb_eventdev *dlb;\n+\n \tstatic struct rte_eventdev_ops dlb_eventdev_entry_ops = {\n \t\t.dev_infos_get = dlb_eventdev_info_get,\n \t\t.dev_configure = dlb_eventdev_configure,\n@@ -2841,6 +3560,15 @@ dlb_entry_points_init(struct rte_eventdev *dev)\n \tdev->enqueue_burst = dlb_event_enqueue_burst;\n \tdev->enqueue_new_burst = dlb_event_enqueue_new_burst;\n \tdev->enqueue_forward_burst = dlb_event_enqueue_forward_burst;\n+\tdev->dequeue = dlb_event_dequeue;\n+\tdev->dequeue_burst = dlb_event_dequeue_burst;\n+\n+\tdlb = dev->data->dev_private;\n+\n+\tif (dlb->poll_mode == DLB_CQ_POLL_MODE_SPARSE) {\n+\t\tdev->dequeue = dlb_event_dequeue_sparse;\n+\t\tdev->dequeue_burst = dlb_event_dequeue_burst_sparse;\n+\t}\n }\n \n int\n", "prefixes": [ "v9", "18/23" ] }