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{
    "id": 8110,
    "url": "https://patches.dpdk.org/api/patches/8110/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/745DB4B8861F8E4B9849C970520ABBF14974C1FC@ORSMSX102.amr.corp.intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<745DB4B8861F8E4B9849C970520ABBF14974C1FC@ORSMSX102.amr.corp.intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/745DB4B8861F8E4B9849C970520ABBF14974C1FC@ORSMSX102.amr.corp.intel.com",
    "date": "2015-10-27T20:56:44",
    "name": "[dpdk-dev,1/2] i40e simple tx: Larger list size (33 to 128) throughput optimization",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "9f51f05eb65dc1c3181d7db4e9eb7da06017f584",
    "submitter": {
        "id": 363,
        "url": "https://patches.dpdk.org/api/people/363/?format=api",
        "name": "Mike A. Polehn",
        "email": "mike.a.polehn@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/745DB4B8861F8E4B9849C970520ABBF14974C1FC@ORSMSX102.amr.corp.intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/8110/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/8110/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B736F8DB1;\n\tTue, 27 Oct 2015 21:56:59 +0100 (CET)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 9A3FB8D9F\n\tfor <dev@dpdk.org>; Tue, 27 Oct 2015 21:56:56 +0100 (CET)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 27 Oct 2015 13:56:45 -0700",
            "from orsmsx101.amr.corp.intel.com ([10.22.225.128])\n\tby orsmga003.jf.intel.com with ESMTP; 27 Oct 2015 13:56:45 -0700",
            "from orsmsx153.amr.corp.intel.com (10.22.226.247) by\n\tORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP\n\tServer (TLS) id 14.3.248.2; Tue, 27 Oct 2015 13:56:45 -0700",
            "from orsmsx102.amr.corp.intel.com ([169.254.1.29]) by\n\tORSMSX153.amr.corp.intel.com ([169.254.12.164]) with mapi id\n\t14.03.0248.002; Tue, 27 Oct 2015 13:56:44 -0700"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,206,1444719600\"; d=\"scan'208\";a=\"673009142\"",
        "From": "\"Polehn, Mike A\" <mike.a.polehn@intel.com>",
        "To": "\"dev@dpdk.org\" <dev@dpdk.org>",
        "Thread-Topic": "[Patch 1/2] i40e simple tx: Larger list size (33 to 128)\n\tthroughput optimization",
        "Thread-Index": "AdEQ+XQ1HFsqOWmYQxyXLCGxHkWUfA==",
        "Date": "Tue, 27 Oct 2015 20:56:44 +0000",
        "Message-ID": "<745DB4B8861F8E4B9849C970520ABBF14974C1FC@ORSMSX102.amr.corp.intel.com>",
        "Accept-Language": "en-US",
        "Content-Language": "en-US",
        "X-MS-Has-Attach": "",
        "X-MS-TNEF-Correlator": "",
        "x-titus-metadata-40": "eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsIiwiaWQiOiIwNjk2NTdmZC1kYjRlLTRiODktOWRjMC1hMTQyNGQwZWI3YzciLCJwcm9wcyI6W3sibiI6IkludGVsRGF0YUNsYXNzaWZpY2F0aW9uIiwidmFscyI6W3sidmFsdWUiOiJDVFBfSUMifV19XX0sIlN1YmplY3RMYWJlbHMiOltdLCJUTUNWZXJzaW9uIjoiMTUuNC4xMC4xOSIsIlRydXN0ZWRMYWJlbEhhc2giOiJWTzRybldKUEQ2V2s5UmZ5VUEralNsamtFNHFJK2hUY1FiTFltNmZZcmwwPSJ9",
        "x-inteldataclassification": "CTP_IC",
        "x-originating-ip": "[10.22.254.139]",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "quoted-printable",
        "MIME-Version": "1.0",
        "Subject": "[dpdk-dev] [Patch 1/2] i40e simple tx: Larger list size (33 to 128)\n\tthroughput optimization",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Reduce the 32 packet list size focus for better packet list size range handling.\n\nChanged maximum new buffer loop process size to the NIC queue free buffer count per loop.\n\nRemoved redundant single call check to just one call with focused loop.\n\nRemove NIC register update write from per loop to one per write driver call to minimize CPU\nstalls waiting for multiple SMP synchronization points and for earlier NIC register writes that\noften take large cycle counts to complete. For example with an output list size of 64, the default \nloops size of 32, when 33 packets are queued on descriptor table, the second NIC register write will occur just after TX processing for 1 packet, resulting in a large CPU stall time.\n\nUsed some standard variables to help reduce overhead of non-standard variable sizes.\n\nReordered variable structure to put most active variables in first cache line, better utilize \nmemory bytes inside cache line, and reduced active cache line count during call.\n\nSigned-off-by: Mike A. Polehn <mike.a.polehn@intel.com>",
    "diff": "diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c\nindex ec62f75..2032e06 100644\n--- a/drivers/net/i40e/i40e_rxtx.c\n+++ b/drivers/net/i40e/i40e_rxtx.c\n@@ -64,6 +64,7 @@\n #define DEFAULT_TX_FREE_THRESH 32\n #define I40E_MAX_PKT_TYPE      256\n #define I40E_RX_INPUT_BUF_MAX  256\n+#define I40E_RX_FREE_THRESH_MIN  2\n \n #define I40E_TX_MAX_BURST  32\n \n@@ -942,6 +943,12 @@ check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)\n \t\t\t     \"rxq->rx_free_thresh=%d\",\n \t\t\t     rxq->nb_rx_desc, rxq->rx_free_thresh);\n \t\tret = -EINVAL;\n+\t} else if (rxq->rx_free_thresh < I40E_RX_FREE_THRESH_MIN) {\n+\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n+\t\t\t\t\"rxq->rx_free_thresh=%d, \"\n+\t\t\t\t\"I40E_RX_FREE_THRESH_MIN=%d\",\n+\t\t\t\trxq->rx_free_thresh, I40E_RX_FREE_THRESH_MIN);\n+\t\t\t\tret = -EINVAL;\n \t} else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -\n \t\t\t\tRTE_PMD_I40E_RX_MAX_BURST))) {\n \t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n@@ -1058,9 +1065,8 @@ i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)\n {\n \tvolatile union i40e_rx_desc *rxdp;\n \tstruct i40e_rx_entry *rxep;\n-\tstruct rte_mbuf *mb;\n-\tunsigned alloc_idx, i;\n-\tuint64_t dma_addr;\n+\tstruct rte_mbuf *pk, *npk;\n+\tunsigned alloc_idx, i, l;\n \tint diag;\n \n \t/* Allocate buffers in bulk */\n@@ -1076,22 +1082,36 @@ i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)\n \t\treturn -ENOMEM;\n \t}\n \n+\tpk = rxep->mbuf;\n+\trte_prefetch0(pk);\n+\trxep++;\n+\tnpk = rxep->mbuf;\n+\trte_prefetch0(npk);\n+\trxep++;\n+\tl = rxq->rx_free_thresh - 2;\n+\n \trxdp = &rxq->rx_ring[alloc_idx];\n \tfor (i = 0; i < rxq->rx_free_thresh; i++) {\n-\t\tif (likely(i < (rxq->rx_free_thresh - 1)))\n+\t\tstruct rte_mbuf *mb = pk;\n+\t\tpk = npk;\n+\t\tif (likely(i < l)) {\n \t\t\t/* Prefetch next mbuf */\n-\t\t\trte_prefetch0(rxep[i + 1].mbuf);\n-\n-\t\tmb = rxep[i].mbuf;\n-\t\trte_mbuf_refcnt_set(mb, 1);\n-\t\tmb->next = NULL;\n+\t\t\tnpk = rxep->mbuf;\n+\t\t\trte_prefetch0(npk);\n+\t\t\trxep++;\n+\t\t}\n \t\tmb->data_off = RTE_PKTMBUF_HEADROOM;\n+\t\trte_mbuf_refcnt_set(mb, 1);\n \t\tmb->nb_segs = 1;\n \t\tmb->port = rxq->port_id;\n-\t\tdma_addr = rte_cpu_to_le_64(\\\n-\t\t\tRTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\n-\t\trxdp[i].read.hdr_addr = 0;\n-\t\trxdp[i].read.pkt_addr = dma_addr;\n+\t\tmb->next = NULL;\n+\t\t{\n+\t\t\tuint64_t dma_addr = rte_cpu_to_le_64(\n+\t\t\t\tRTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\n+\t\t\trxdp->read.hdr_addr = dma_addr;\n+\t\t\trxdp->read.pkt_addr = dma_addr;\n+\t\t}\n+\t\trxdp++;\n \t}\n \n \trxq->rx_last_pos = alloc_idx + rxq->rx_free_thresh - 1;\n",
    "prefixes": [
        "dpdk-dev",
        "1/2"
    ]
}