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GET /api/patches/80711/?format=api
{ "id": 80711, "url": "https://patches.dpdk.org/api/patches/80711/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201014100114.26596-3-huwei013@chinasoftinc.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201014100114.26596-3-huwei013@chinasoftinc.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201014100114.26596-3-huwei013@chinasoftinc.com", "date": "2020-10-14T10:01:14", "name": "[2/2] net/hns3: support SVE Tx", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b152fd93c09beae5770070ed122890b1f8b85824", "submitter": { "id": 1537, "url": "https://patches.dpdk.org/api/people/1537/?format=api", "name": "Wei Hu (Xavier)", "email": "huwei013@chinasoftinc.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201014100114.26596-3-huwei013@chinasoftinc.com/mbox/", "series": [ { "id": 12950, "url": "https://patches.dpdk.org/api/series/12950/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12950", "date": "2020-10-14T10:01:12", "name": "net/hns3: support SVE Tx/Rx", "version": 1, "mbox": "https://patches.dpdk.org/series/12950/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/80711/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/80711/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3BB7BA04B7;\n\tWed, 14 Oct 2020 12:02:26 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 141271DDE6;\n\tWed, 14 Oct 2020 12:01:43 +0200 (CEST)", "from incedge.chinasoftinc.com (unknown [114.113.233.8])\n by dpdk.org (Postfix) with ESMTP id DDA101DDDD\n for <dev@dpdk.org>; Wed, 14 Oct 2020 12:01:38 +0200 (CEST)", "from mail.chinasoftinc.com (inccas001.ito.icss [10.168.0.51]) by\n incedge.chinasoftinc.com with ESMTP id OhuvVcbSHrW4VQ4R (version=TLSv1\n cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NO);\n Wed, 14 Oct 2020 18:01:37 +0800 (CST)", "from localhost.localdomain (65.49.108.226) by INCCAS001.ito.icss\n (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Wed, 14 Oct 2020\n 18:01:36 +0800" ], "X-ASG-Debug-ID": "1602669697-149d114cae25d490001-TfluYd", "X-Barracuda-Envelope-From": "huwei013@chinasoftinc.com", "X-Barracuda-RBL-Trusted-Forwarder": [ "10.168.0.51", "10.168.0.60" ], "X-ASG-Whitelist": "Client", "From": "\"Wei Hu (Xavier)\" <huwei013@chinasoftinc.com>", "To": "<dev@dpdk.org>", "CC": "<xavier.huwei@huawei.com>", "Date": "Wed, 14 Oct 2020 18:01:14 +0800", "X-ASG-Orig-Subj": "[PATCH 2/2] net/hns3: support SVE Tx", "Message-ID": "<20201014100114.26596-3-huwei013@chinasoftinc.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20201014100114.26596-1-huwei013@chinasoftinc.com>", "References": "<20201014100114.26596-1-huwei013@chinasoftinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[65.49.108.226]", "X-Barracuda-Connect": "inccas001.ito.icss[10.168.0.51]", "X-Barracuda-Start-Time": "1602669697", "X-Barracuda-Encrypted": "ECDHE-RSA-AES256-SHA", "X-Barracuda-URL": "https://incspam.chinasofti.com:443/cgi-mod/mark.cgi", "X-Virus-Scanned": "by bsmtpd at chinasoftinc.com", "X-Barracuda-Scan-Msg-Size": "10588", "Subject": "[dpdk-dev] [PATCH 2/2] net/hns3: support SVE Tx", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Chengwen Feng <fengchengwen@huawei.com>\n\nThis patch adds SVE vector instructions to optimize Tx burst process.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_rxtx.c | 17 +++-\n drivers/net/hns3/hns3_rxtx.h | 2 +\n drivers/net/hns3/hns3_rxtx_vec.h | 34 +++++---\n drivers/net/hns3/hns3_rxtx_vec_sve.c | 159 +++++++++++++++++++++++++++++++++++\n 4 files changed, 196 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c\nindex e1ff173..d511908 100644\n--- a/drivers/net/hns3/hns3_rxtx.c\n+++ b/drivers/net/hns3/hns3_rxtx.c\n@@ -2345,7 +2345,7 @@ hns3_rx_check_vec_support(__rte_unused struct rte_eth_dev *dev)\n \n uint16_t __rte_weak\n hns3_recv_pkts_vec(__rte_unused void *tx_queue,\n-\t\t __rte_unused struct rte_mbuf **tx_pkts,\n+\t\t __rte_unused struct rte_mbuf **rx_pkts,\n \t\t __rte_unused uint16_t nb_pkts)\n {\n \treturn 0;\n@@ -2353,7 +2353,7 @@ hns3_recv_pkts_vec(__rte_unused void *tx_queue,\n \n uint16_t __rte_weak\n hns3_recv_pkts_vec_sve(__rte_unused void *tx_queue,\n-\t\t __rte_unused struct rte_mbuf **tx_pkts,\n+\t\t __rte_unused struct rte_mbuf **rx_pkts,\n \t\t __rte_unused uint16_t nb_pkts)\n {\n \treturn 0;\n@@ -3615,6 +3615,14 @@ hns3_xmit_pkts_vec(__rte_unused void *tx_queue,\n \treturn 0;\n }\n \n+uint16_t __rte_weak\n+hns3_xmit_pkts_vec_sve(void __rte_unused * tx_queue,\n+\t\t struct rte_mbuf __rte_unused **tx_pkts,\n+\t\t uint16_t __rte_unused nb_pkts)\n+{\n+\treturn 0;\n+}\n+\n int\n hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,\n \t\t struct rte_eth_burst_mode *mode)\n@@ -3628,6 +3636,8 @@ hns3_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,\n \t\tinfo = \"Scalar\";\n \telse if (pkt_burst == hns3_xmit_pkts_vec)\n \t\tinfo = \"Vector Neon\";\n+\telse if (pkt_burst == hns3_xmit_pkts_vec_sve)\n+\t\tinfo = \"Vector Sve\";\n \n \tif (info == NULL)\n \t\treturn -EINVAL;\n@@ -3645,7 +3655,8 @@ hns3_get_tx_function(struct rte_eth_dev *dev, eth_tx_prep_t *prep)\n \n \tif (hns->tx_vec_allowed && hns3_tx_check_vec_support(dev) == 0) {\n \t\t*prep = NULL;\n-\t\treturn hns3_xmit_pkts_vec;\n+\t\treturn hns3_check_sve_support() ? hns3_xmit_pkts_vec_sve :\n+\t\t\thns3_xmit_pkts_vec;\n \t}\n \n \tif (hns->tx_simple_allowed &&\ndiff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h\nindex ba1b017..4be9c4a 100644\n--- a/drivers/net/hns3/hns3_rxtx.h\n+++ b/drivers/net/hns3/hns3_rxtx.h\n@@ -644,6 +644,8 @@ uint16_t hns3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\tuint16_t nb_pkts);\n uint16_t hns3_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t\t\t\tuint16_t nb_pkts);\n+uint16_t hns3_xmit_pkts_vec_sve(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\tuint16_t nb_pkts);\n int hns3_tx_burst_mode_get(struct rte_eth_dev *dev,\n \t\t\t __rte_unused uint16_t queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec.h b/drivers/net/hns3/hns3_rxtx_vec.h\nindex c6df36d..35d9903 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec.h\n+++ b/drivers/net/hns3/hns3_rxtx_vec.h\n@@ -9,26 +9,14 @@\n #include \"hns3_ethdev.h\"\n \n static inline void\n-hns3_tx_free_buffers(struct hns3_tx_queue *txq)\n+hns3_tx_bulk_free_buffers(struct hns3_tx_queue *txq)\n {\n \tstruct rte_mbuf **free = txq->free;\n \tstruct hns3_entry *tx_entry;\n-\tstruct hns3_desc *tx_desc;\n \tstruct rte_mbuf *m;\n \tint nb_free = 0;\n \tint i;\n \n-\t/*\n-\t * All mbufs can be released only when the VLD bits of all\n-\t * descriptors in a batch are cleared.\n-\t */\n-\ttx_desc = &txq->tx_ring[txq->next_to_clean];\n-\tfor (i = 0; i < txq->tx_rs_thresh; i++, tx_desc++) {\n-\t\tif (tx_desc->tx.tp_fe_sc_vld_ra_ri &\n-\t\t\t\trte_le_to_cpu_16(BIT(HNS3_TXD_VLD_B)))\n-\t\t\treturn;\n-\t}\n-\n \ttx_entry = &txq->sw_ring[txq->next_to_clean];\n \tfor (i = 0; i < txq->tx_rs_thresh; i++, tx_entry++) {\n \t\tm = rte_pktmbuf_prefree_seg(tx_entry->mbuf);\n@@ -55,6 +43,26 @@ hns3_tx_free_buffers(struct hns3_tx_queue *txq)\n \t\ttxq->next_to_clean = 0;\n }\n \n+static inline void\n+hns3_tx_free_buffers(struct hns3_tx_queue *txq)\n+{\n+\tstruct hns3_desc *tx_desc;\n+\tint i;\n+\n+\t/*\n+\t * All mbufs can be released only when the VLD bits of all\n+\t * descriptors in a batch are cleared.\n+\t */\n+\ttx_desc = &txq->tx_ring[txq->next_to_clean];\n+\tfor (i = 0; i < txq->tx_rs_thresh; i++, tx_desc++) {\n+\t\tif (tx_desc->tx.tp_fe_sc_vld_ra_ri &\n+\t\t\t\trte_le_to_cpu_16(BIT(HNS3_TXD_VLD_B)))\n+\t\t\treturn;\n+\t}\n+\n+\thns3_tx_bulk_free_buffers(txq);\n+}\n+\n static inline uint16_t\n hns3_rx_reassemble_pkts(struct rte_mbuf **rx_pkts,\n \t\t\tuint16_t nb_pkts,\ndiff --git a/drivers/net/hns3/hns3_rxtx_vec_sve.c b/drivers/net/hns3/hns3_rxtx_vec_sve.c\nindex 9a81cb0..8c2c8f6 100644\n--- a/drivers/net/hns3/hns3_rxtx_vec_sve.c\n+++ b/drivers/net/hns3/hns3_rxtx_vec_sve.c\n@@ -311,3 +311,162 @@ hns3_recv_pkts_vec_sve(void *__restrict rx_queue,\n \n \treturn nb_rx;\n }\n+\n+static inline void\n+hns3_tx_free_buffers_sve(struct hns3_tx_queue *txq)\n+{\n+#define HNS3_SVE_CHECK_DESCS_PER_LOOP\t8\n+#define TX_VLD_U8_ZIP_INDEX\t\tsvindex_u8(0, 4)\n+\tsvbool_t pg32 = svwhilelt_b32(0, HNS3_SVE_CHECK_DESCS_PER_LOOP);\n+\tsvuint32_t vld, vld2;\n+\tsvuint8_t vld_u8;\n+\tuint64_t vld_all;\n+\tstruct hns3_desc *tx_desc;\n+\tint i;\n+\n+\t/*\n+\t * All mbufs can be released only when the VLD bits of all\n+\t * descriptors in a batch are cleared.\n+\t */\n+\t/* do logical OR operation for all desc's valid field */\n+\tvld = svdup_n_u32(0);\n+\ttx_desc = &txq->tx_ring[txq->next_to_clean];\n+\tfor (i = 0; i < txq->tx_rs_thresh; i += HNS3_SVE_CHECK_DESCS_PER_LOOP,\n+\t\t\t\ttx_desc += HNS3_SVE_CHECK_DESCS_PER_LOOP) {\n+\t\tvld2 = svld1_gather_u32offset_u32(pg32, (uint32_t *)tx_desc,\n+\t\t\t\tsvindex_u32(BD_FIELD_VALID_OFFSET, BD_SIZE));\n+\t\tvld = svorr_u32_z(pg32, vld, vld2);\n+\t}\n+\t/* shift left and then right to get all valid bit */\n+\tvld = svlsl_n_u32_z(pg32, vld,\n+\t\t\t HNS3_UINT32_BIT - 1 - HNS3_TXD_VLD_B);\n+\tvld = svreinterpret_u32_s32(svasr_n_s32_z(pg32,\n+\t\tsvreinterpret_s32_u32(vld), HNS3_UINT32_BIT - 1));\n+\t/* use tbl to compress 32bit-lane to 8bit-lane */\n+\tvld_u8 = svtbl_u8(svreinterpret_u8_u32(vld), TX_VLD_U8_ZIP_INDEX);\n+\t/* dump compressed 64bit to variable */\n+\tsvst1_u64(PG64_64BIT, &vld_all, svreinterpret_u64_u8(vld_u8));\n+\tif (vld_all > 0)\n+\t\treturn;\n+\n+\thns3_tx_bulk_free_buffers(txq);\n+}\n+\n+static inline void\n+hns3_tx_fill_hw_ring_sve(struct hns3_tx_queue *txq,\n+\t\t\t struct rte_mbuf **pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+#define DATA_OFF_LEN_VAL_MASK\t0xFFFF\n+\tstruct hns3_desc *txdp = &txq->tx_ring[txq->next_to_use];\n+\tstruct hns3_entry *tx_entry = &txq->sw_ring[txq->next_to_use];\n+\tconst uint64_t valid_bit = (BIT(HNS3_TXD_VLD_B) | BIT(HNS3_TXD_FE_B)) <<\n+\t\t\t\t HNS3_UINT32_BIT;\n+\tsvuint64_t base_addr, buf_iova, data_off, data_len, addr;\n+\tsvuint64_t offsets = svindex_u64(0, BD_SIZE);\n+\tuint32_t i = 0;\n+\tsvbool_t pg = svwhilelt_b64_u32(i, nb_pkts);\n+\n+\tdo {\n+\t\tbase_addr = svld1_u64(pg, (uint64_t *)pkts);\n+\t\t/* calc mbuf's field buf_iova address */\n+\t\tbuf_iova = svadd_n_u64_z(pg, base_addr,\n+\t\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n+\t\t/* calc mbuf's field data_off address */\n+\t\tdata_off = svadd_n_u64_z(pg, base_addr,\n+\t\t\t\t\t offsetof(struct rte_mbuf, data_off));\n+\t\t/* calc mbuf's field data_len address */\n+\t\tdata_len = svadd_n_u64_z(pg, base_addr,\n+\t\t\t\t\t offsetof(struct rte_mbuf, data_len));\n+\t\t/* store mbuf to tx_entry */\n+\t\tsvst1_u64(pg, (uint64_t *)tx_entry, base_addr);\n+\t\t/* read pkts->buf_iova */\n+\t\tbuf_iova = svld1_gather_u64base_u64(pg, buf_iova);\n+\t\t/* read pkts->data_off's 64bit val */\n+\t\tdata_off = svld1_gather_u64base_u64(pg, data_off);\n+\t\t/* read pkts->data_len's 64bit val */\n+\t\tdata_len = svld1_gather_u64base_u64(pg, data_len);\n+\t\t/* zero data_off high 48bit by svand ops */\n+\t\tdata_off = svand_n_u64_z(pg, data_off, DATA_OFF_LEN_VAL_MASK);\n+\t\t/* zero data_len high 48bit by svand ops */\n+\t\tdata_len = svand_n_u64_z(pg, data_len, DATA_OFF_LEN_VAL_MASK);\n+\t\t/* calc mbuf data region iova addr */\n+\t\taddr = svadd_u64_z(pg, buf_iova, data_off);\n+\t\t/* shift due data_len's offset is 2byte of BD's second 8byte */\n+\t\tdata_len = svlsl_n_u64_z(pg, data_len, HNS3_UINT16_BIT);\n+\t\t/* save offset 0~7byte of every BD */\n+\t\tsvst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->addr,\n+\t\t\t\t\t offsets, addr);\n+\t\t/* save offset 8~15byte of every BD */\n+\t\tsvst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.vlan_tag,\n+\t\t\t\t\t offsets, data_len);\n+\t\t/* save offset 16~23byte of every BD */\n+\t\tsvst1_scatter_u64offset_u64(pg,\n+\t\t\t\t(uint64_t *)&txdp->tx.outer_vlan_tag,\n+\t\t\t\toffsets, svdup_n_u64(0));\n+\t\t/* save offset 24~31byte of every BD */\n+\t\tsvst1_scatter_u64offset_u64(pg, (uint64_t *)&txdp->tx.paylen,\n+\t\t\t\t\t offsets, svdup_n_u64(valid_bit));\n+\n+\t\t/* update index for next loop */\n+\t\ti += svcntd();\n+\t\tpkts += svcntd();\n+\t\ttxdp += svcntd();\n+\t\ttx_entry += svcntd();\n+\t\tpg = svwhilelt_b64_u32(i, nb_pkts);\n+\t} while (svptest_any(svptrue_b64(), pg));\n+}\n+\n+static uint16_t\n+hns3_xmit_fixed_burst_vec_sve(void *__restrict tx_queue,\n+\t\t\t struct rte_mbuf **__restrict tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;\n+\tuint16_t nb_tx = 0;\n+\n+\tif (txq->tx_bd_ready < txq->tx_free_thresh)\n+\t\thns3_tx_free_buffers_sve(txq);\n+\n+\tnb_pkts = RTE_MIN(txq->tx_bd_ready, nb_pkts);\n+\tif (unlikely(nb_pkts == 0)) {\n+\t\ttxq->queue_full_cnt++;\n+\t\treturn 0;\n+\t}\n+\n+\tif (txq->next_to_use + nb_pkts > txq->nb_tx_desc) {\n+\t\tnb_tx = txq->nb_tx_desc - txq->next_to_use;\n+\t\thns3_tx_fill_hw_ring_sve(txq, tx_pkts, nb_tx);\n+\t\ttxq->next_to_use = 0;\n+\t}\n+\n+\thns3_tx_fill_hw_ring_sve(txq, tx_pkts + nb_tx, nb_pkts - nb_tx);\n+\ttxq->next_to_use += nb_pkts - nb_tx;\n+\n+\ttxq->tx_bd_ready -= nb_pkts;\n+\thns3_write_reg_opt(txq->io_tail_reg, nb_pkts);\n+\n+\treturn nb_pkts;\n+}\n+\n+uint16_t\n+hns3_xmit_pkts_vec_sve(void *tx_queue,\n+\t\t struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tstruct hns3_tx_queue *txq = (struct hns3_tx_queue *)tx_queue;\n+\tuint16_t ret, new_burst;\n+\tuint16_t nb_tx = 0;\n+\n+\twhile (nb_pkts) {\n+\t\tnew_burst = RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\t\tret = hns3_xmit_fixed_burst_vec_sve(tx_queue, &tx_pkts[nb_tx],\n+\t\t\t\t\t\t new_burst);\n+\t\tnb_tx += ret;\n+\t\tnb_pkts -= ret;\n+\t\tif (ret < new_burst)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn nb_tx;\n+}\n", "prefixes": [ "2/2" ] }