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{
    "id": 8050,
    "url": "https://patches.dpdk.org/api/patches/8050/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1445939209-12783-5-git-send-email-jing.d.chen@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1445939209-12783-5-git-send-email-jing.d.chen@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1445939209-12783-5-git-send-email-jing.d.chen@intel.com",
    "date": "2015-10-27T09:46:37",
    "name": "[dpdk-dev,v3,04/16] fm10k: add func to re-allocate mbuf for RX ring",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "0ebc9c8b2960845a45aac34f696fd62acec6fd2f",
    "submitter": {
        "id": 40,
        "url": "https://patches.dpdk.org/api/people/40/?format=api",
        "name": "Chen, Jing D",
        "email": "jing.d.chen@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1445939209-12783-5-git-send-email-jing.d.chen@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/8050/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/8050/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0838A8DA7;\n\tTue, 27 Oct 2015 10:47:12 +0100 (CET)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id EAFC65A56\n\tfor <dev@dpdk.org>; Tue, 27 Oct 2015 10:47:09 +0100 (CET)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga103.jf.intel.com with ESMTP; 27 Oct 2015 02:47:09 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 27 Oct 2015 02:47:08 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9R9l26T030871;\n\tTue, 27 Oct 2015 17:47:02 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9R9l0Si012845; Tue, 27 Oct 2015 17:47:02 +0800",
            "(from jingche2@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9R9l0et012841; \n\tTue, 27 Oct 2015 17:47:00 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,204,1444719600\"; d=\"scan'208\";a=\"672566141\"",
        "From": "\"Chen Jing D(Mark)\" <jing.d.chen@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue, 27 Oct 2015 17:46:37 +0800",
        "Message-Id": "<1445939209-12783-5-git-send-email-jing.d.chen@intel.com>",
        "X-Mailer": "git-send-email 1.7.12.2",
        "In-Reply-To": "<1445939209-12783-1-git-send-email-jing.d.chen@intel.com>",
        "References": "<1445507104-22563-2-git-send-email-jing.d.chen@intel.com>\n\t<1445939209-12783-1-git-send-email-jing.d.chen@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 04/16] fm10k: add func to re-allocate mbuf for\n\tRX ring",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: \"Chen Jing D(Mark)\" <jing.d.chen@intel.com>\n\nAdd function fm10k_rxq_rearm to re-allocate mbuf for used desc\nin RX HW ring.\n\nSigned-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com>\n---\n drivers/net/fm10k/fm10k.h          |    9 ++++\n drivers/net/fm10k/fm10k_ethdev.c   |    3 +\n drivers/net/fm10k/fm10k_rxtx_vec.c |   90 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 102 insertions(+), 0 deletions(-)",
    "diff": "diff --git a/drivers/net/fm10k/fm10k.h b/drivers/net/fm10k/fm10k.h\nindex 362a2d0..5df7960 100644\n--- a/drivers/net/fm10k/fm10k.h\n+++ b/drivers/net/fm10k/fm10k.h\n@@ -123,6 +123,12 @@\n #define FM10K_VFTA_BIT(vlan_id)    (1 << ((vlan_id) & 0x1F))\n #define FM10K_VFTA_IDX(vlan_id)    ((vlan_id) >> 5)\n \n+#define RTE_FM10K_RXQ_REARM_THRESH      32\n+#define RTE_FM10K_VPMD_TX_BURST         32\n+#define RTE_FM10K_MAX_RX_BURST          RTE_FM10K_RXQ_REARM_THRESH\n+#define RTE_FM10K_TX_MAX_FREE_BUF_SZ    64\n+#define RTE_FM10K_DESCS_PER_LOOP    4\n+\n struct fm10k_macvlan_filter_info {\n \tuint16_t vlan_num;       /* Total VLAN number */\n \tuint16_t mac_num;        /* Total mac number */\n@@ -178,6 +184,9 @@ struct fm10k_rx_queue {\n \tvolatile uint32_t *tail_ptr;\n \tuint16_t nb_desc;\n \tuint16_t queue_id;\n+\t/* Below 2 fields only valid in case vPMD is applied. */\n+\tuint16_t rxrearm_nb;     /* number of remaining to be re-armed */\n+\tuint16_t rxrearm_start;  /* the idx we start the re-arming from */\n \tuint8_t port_id;\n \tuint8_t drop_en;\n \tuint8_t rx_deferred_start; /* don't start this queue in dev start. */\ndiff --git a/drivers/net/fm10k/fm10k_ethdev.c b/drivers/net/fm10k/fm10k_ethdev.c\nindex 363ef98..44c3d34 100644\n--- a/drivers/net/fm10k/fm10k_ethdev.c\n+++ b/drivers/net/fm10k/fm10k_ethdev.c\n@@ -121,6 +121,9 @@ rx_queue_reset(struct fm10k_rx_queue *q)\n \tq->next_alloc = 0;\n \tq->next_trigger = q->alloc_thresh - 1;\n \tFM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);\n+\tq->rxrearm_start = 0;\n+\tq->rxrearm_nb = 0;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/fm10k/fm10k_rxtx_vec.c b/drivers/net/fm10k/fm10k_rxtx_vec.c\nindex 34b677b..75533f9 100644\n--- a/drivers/net/fm10k/fm10k_rxtx_vec.c\n+++ b/drivers/net/fm10k/fm10k_rxtx_vec.c\n@@ -64,3 +64,93 @@ fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq)\n \trxq->mbuf_initializer = *(uint64_t *)p;\n \treturn 0;\n }\n+\n+static inline void\n+fm10k_rxq_rearm(struct fm10k_rx_queue *rxq)\n+{\n+\tint i;\n+\tuint16_t rx_id;\n+\tvolatile union fm10k_rx_desc *rxdp;\n+\tstruct rte_mbuf **mb_alloc = &rxq->sw_ring[rxq->rxrearm_start];\n+\tstruct rte_mbuf *mb0, *mb1;\n+\t__m128i head_off = _mm_set_epi64x(\n+\t\t\tRTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1,\n+\t\t\tRTE_PKTMBUF_HEADROOM + FM10K_RX_DATABUF_ALIGN - 1);\n+\t__m128i dma_addr0, dma_addr1;\n+\t/* Rx buffer need to be aligned with 512 byte */\n+\tconst __m128i hba_msk = _mm_set_epi64x(0,\n+\t\t\t\tUINT64_MAX - FM10K_RX_DATABUF_ALIGN + 1);\n+\n+\trxdp = rxq->hw_ring + rxq->rxrearm_start;\n+\n+\t/* Pull 'n' more MBUFs into the software ring */\n+\tif (rte_mempool_get_bulk(rxq->mp,\n+\t\t\t\t (void *)mb_alloc,\n+\t\t\t\t RTE_FM10K_RXQ_REARM_THRESH) < 0) {\n+\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n+\t\t\tRTE_FM10K_RXQ_REARM_THRESH;\n+\t\treturn;\n+\t}\n+\n+\t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n+\tfor (i = 0; i < RTE_FM10K_RXQ_REARM_THRESH; i += 2, mb_alloc += 2) {\n+\t\t__m128i vaddr0, vaddr1;\n+\t\tuintptr_t p0, p1;\n+\n+\t\tmb0 = mb_alloc[0];\n+\t\tmb1 = mb_alloc[1];\n+\n+\t\t/* Flush mbuf with pkt template.\n+\t\t * Data to be rearmed is 6 bytes long.\n+\t\t * Though, RX will overwrite ol_flags that are coming next\n+\t\t * anyway. So overwrite whole 8 bytes with one load:\n+\t\t * 6 bytes of rearm_data plus first 2 bytes of ol_flags.\n+\t\t */\n+\t\tp0 = (uintptr_t)&mb0->rearm_data;\n+\t\t*(uint64_t *)p0 = rxq->mbuf_initializer;\n+\t\tp1 = (uintptr_t)&mb1->rearm_data;\n+\t\t*(uint64_t *)p1 = rxq->mbuf_initializer;\n+\n+\t\t/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */\n+\t\tvaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));\n+\t\tvaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));\n+\n+\t\t/* convert pa to dma_addr hdr/data */\n+\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n+\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n+\n+\t\t/* add headroom to pa values */\n+\t\tdma_addr0 = _mm_add_epi64(dma_addr0, head_off);\n+\t\tdma_addr1 = _mm_add_epi64(dma_addr1, head_off);\n+\n+\t\t/* Do 512 byte alignment to satisfy HW requirement, in the\n+\t\t * meanwhile, set Header Buffer Address to zero.\n+\t\t */\n+\t\tdma_addr0 = _mm_and_si128(dma_addr0, hba_msk);\n+\t\tdma_addr1 = _mm_and_si128(dma_addr1, hba_msk);\n+\n+\t\t/* flush desc with pa dma_addr */\n+\t\t_mm_store_si128((__m128i *)&rxdp++->q, dma_addr0);\n+\t\t_mm_store_si128((__m128i *)&rxdp++->q, dma_addr1);\n+\n+\t\t/* enforce 512B alignment on default Rx virtual addresses */\n+\t\tmb0->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb0->buf_addr\n+\t\t\t\t+ RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)\n+\t\t\t\t- (char *)mb0->buf_addr);\n+\t\tmb1->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb1->buf_addr\n+\t\t\t\t+ RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)\n+\t\t\t\t- (char *)mb1->buf_addr);\n+\t}\n+\n+\trxq->rxrearm_start += RTE_FM10K_RXQ_REARM_THRESH;\n+\tif (rxq->rxrearm_start >= rxq->nb_desc)\n+\t\trxq->rxrearm_start = 0;\n+\n+\trxq->rxrearm_nb -= RTE_FM10K_RXQ_REARM_THRESH;\n+\n+\trx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?\n+\t\t\t     (rxq->nb_desc - 1) : (rxq->rxrearm_start - 1));\n+\n+\t/* Update the tail pointer on the NIC */\n+\tFM10K_PCI_REG_WRITE(rxq->tail_ptr, rx_id);\n+}\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "04/16"
    ]
}