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GET /api/patches/8011/?format=api
{ "id": 8011, "url": "https://patches.dpdk.org/api/patches/8011/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1445837254-6188-7-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1445837254-6188-7-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1445837254-6188-7-git-send-email-wenzhuo.lu@intel.com", "date": "2015-10-26T05:27:33", "name": "[dpdk-dev,v5,6/7] ixgbe: implementation for fdir new modes' config", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6d656a493f90025433563db8f5b19516f6b6baa0", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1445837254-6188-7-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/8011/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/8011/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id C0B7D8D9C;\n\tMon, 26 Oct 2015 06:27:58 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 27B5E8D9C\n\tfor <dev@dpdk.org>; Mon, 26 Oct 2015 06:27:57 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP; 25 Oct 2015 22:27:57 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 25 Oct 2015 22:27:55 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t9Q5Rsa8031254;\n\tMon, 26 Oct 2015 13:27:54 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t9Q5RoaV006265; Mon, 26 Oct 2015 13:27:52 +0800", "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9Q5RoMV006261; \n\tMon, 26 Oct 2015 13:27:50 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,200,1444719600\"; d=\"scan'208\";a=\"819338941\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 26 Oct 2015 13:27:33 +0800", "Message-Id": "<1445837254-6188-7-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1445837254-6188-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1443161125-1035-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1445837254-6188-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 6/7] ixgbe: implementation for fdir new modes'\n\tconfig", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Implement the new CLIs for fdir mac vlan and tunnel modes, including\nflow_director_filter and flow_director_mask. Set the mask of fdir.\nAdd, delete or update the entities of filter.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.h | 3 +\n drivers/net/ixgbe/ixgbe_fdir.c | 262 ++++++++++++++++++++++++++++++++++-----\n 2 files changed, 235 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h\nindex c3d4f4f..1e971b9 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.h\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.h\n@@ -133,6 +133,9 @@ struct ixgbe_hw_fdir_mask {\n \tuint16_t src_port_mask;\n \tuint16_t dst_port_mask;\n \tuint16_t flex_bytes_mask;\n+\tuint8_t mac_addr_byte_mask;\n+\tuint32_t tunnel_id_mask;\n+\tuint8_t tunnel_type_mask;\n };\n \n struct ixgbe_hw_fdir_info {\ndiff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.c\nindex 5c8b833..2b4c46a 100644\n--- a/drivers/net/ixgbe/ixgbe_fdir.c\n+++ b/drivers/net/ixgbe/ixgbe_fdir.c\n@@ -105,15 +105,23 @@\n \trte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\\\n } while (0)\n \n+#define DEFAULT_VXLAN_PORT 4789\n+#define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4\n+\n static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);\n+static int fdir_set_input_mask(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_eth_fdir_masks *input_mask);\n static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,\n \t\tconst struct rte_eth_fdir_masks *input_mask);\n+static int fdir_set_input_mask_x550(struct rte_eth_dev *dev,\n+\t\t\t\t const struct rte_eth_fdir_masks *input_mask);\n static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,\n \t\tconst struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);\n static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);\n static int ixgbe_fdir_filter_to_atr_input(\n \t\tconst struct rte_eth_fdir_filter *fdir_filter,\n-\t\tunion ixgbe_atr_input *input);\n+\t\tunion ixgbe_atr_input *input,\n+\t\tenum rte_fdir_mode mode);\n static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,\n \t\t\t\t uint32_t key);\n static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,\n@@ -122,7 +130,8 @@ static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n \t\tenum rte_fdir_pballoc_type pballoc);\n static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \t\t\tunion ixgbe_atr_input *input, uint8_t queue,\n-\t\t\tuint32_t fdircmd, uint32_t fdirhash);\n+\t\t\tuint32_t fdircmd, uint32_t fdirhash,\n+\t\t\tenum rte_fdir_mode mode);\n static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n \t\tunion ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,\n \t\tuint32_t fdirhash);\n@@ -243,9 +252,16 @@ configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)\n \t*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<\n \t\t IXGBE_FDIRCTRL_FLEX_SHIFT;\n \n-\tif (conf->mode == RTE_FDIR_MODE_PERFECT) {\n+\tif (conf->mode >= RTE_FDIR_MODE_PERFECT &&\n+\t conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {\n \t\t*fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;\n \t\t*fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);\n+\t\tif (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)\n+\t\t\t*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN\n+\t\t\t\t\t<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);\n+\t\telse if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)\n+\t\t\t*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD\n+\t\t\t\t\t<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);\n \t}\n \n \treturn 0;\n@@ -274,7 +290,7 @@ reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)\n }\n \n /*\n- * This is based on ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,\n+ * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,\n * but makes use of the rte_fdir_masks structure to see which bits to set.\n */\n static int\n@@ -342,7 +358,6 @@ fdir_set_input_mask_82599(struct rte_eth_dev *dev,\n \n \tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {\n \t\t/*\n-\t\t * IPv6 mask is only meaningful in signature mode\n \t\t * Store source and destination IPv6 masks (bit reversed)\n \t\t */\n \t\tIPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);\n@@ -358,6 +373,123 @@ fdir_set_input_mask_82599(struct rte_eth_dev *dev,\n }\n \n /*\n+ * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,\n+ * but makes use of the rte_fdir_masks structure to see which bits to set.\n+ */\n+static int\n+fdir_set_input_mask_x550(struct rte_eth_dev *dev,\n+\t\t\t const struct rte_eth_fdir_masks *input_mask)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_hw_fdir_info *info =\n+\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n+\t/* mask VM pool and DIPv6 since there are currently not supported\n+\t * mask FLEX byte, it will be set in flex_conf\n+\t */\n+\tuint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |\n+\t\t\t IXGBE_FDIRM_FLEX;\n+\tuint32_t fdiripv6m;\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n+\tuint16_t mac_mask;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* set the default UDP port for VxLAN */\n+\tif (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);\n+\n+\t/* some bits must be set for mac vlan or tunnel mode */\n+\tfdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;\n+\n+\tif (input_mask->vlan_tci_mask == 0x0FFF)\n+\t\t/* mask VLAN Priority */\n+\t\tfdirm |= IXGBE_FDIRM_VLANP;\n+\telse if (input_mask->vlan_tci_mask == 0xE000)\n+\t\t/* mask VLAN ID */\n+\t\tfdirm |= IXGBE_FDIRM_VLANID;\n+\telse if (input_mask->vlan_tci_mask == 0)\n+\t\t/* mask VLAN ID and Priority */\n+\t\tfdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;\n+\telse if (input_mask->vlan_tci_mask != 0xEFFF) {\n+\t\tPMD_INIT_LOG(ERR, \"invalid vlan_tci_mask\");\n+\t\treturn -EINVAL;\n+\t}\n+\tinfo->mask.vlan_tci_mask = input_mask->vlan_tci_mask;\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n+\n+\tfdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);\n+\tfdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;\n+\tif (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)\n+\t\tfdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |\n+\t\t\t\tIXGBE_FDIRIP6M_TNI_VNI;\n+\n+\tmac_mask = input_mask->mac_addr_byte_mask;\n+\tfdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)\n+\t\t\t& IXGBE_FDIRIP6M_INNER_MAC;\n+\tinfo->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;\n+\n+\tif (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {\n+\t\tswitch (input_mask->tunnel_type_mask) {\n+\t\tcase 0:\n+\t\t\t/* Mask turnnel type */\n+\t\t\tfdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;\n+\t\t\tbreak;\n+\t\tcase 1:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tPMD_INIT_LOG(ERR, \"invalid tunnel_type_mask\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tinfo->mask.tunnel_type_mask =\n+\t\t\tinput_mask->tunnel_type_mask;\n+\n+\t\tswitch (input_mask->tunnel_id_mask & 0xFFFFFFFF) {\n+\t\tcase 0x0:\n+\t\t\t/* Mask vxlan id */\n+\t\t\tfdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;\n+\t\t\tbreak;\n+\t\tcase 0x00FFFFFF:\n+\t\t\tfdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;\n+\t\t\tbreak;\n+\t\tcase 0xFFFFFFFF:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tPMD_INIT_LOG(ERR, \"invalid tunnel_id_mask\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tinfo->mask.tunnel_id_mask =\n+\t\t\tinput_mask->tunnel_id_mask;\n+\t}\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);\n+\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+static int\n+fdir_set_input_mask(struct rte_eth_dev *dev,\n+\t\t const struct rte_eth_fdir_masks *input_mask)\n+{\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n+\n+\tif (mode >= RTE_FDIR_MODE_SIGNATURE &&\n+\t mode <= RTE_FDIR_MODE_PERFECT)\n+\t\treturn fdir_set_input_mask_82599(dev, input_mask);\n+\telse if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&\n+\t\t mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)\n+\t\treturn fdir_set_input_mask_x550(dev, input_mask);\n+\n+\tPMD_DRV_LOG(ERR, \"Not supported fdir mode - %d!\", mode);\n+\treturn -ENOTSUP;\n+}\n+\n+/*\n * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration\n * arguments are valid\n */\n@@ -431,6 +563,7 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)\n \tint err;\n \tuint32_t fdirctrl, pbsize;\n \tint i;\n+\tenum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;\n \n \tPMD_INIT_FUNC_TRACE();\n \n@@ -440,6 +573,13 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)\n \t\thw->mac.type != ixgbe_mac_X550EM_x)\n \t\treturn -ENOSYS;\n \n+\t/* x550 supports mac-vlan and tunnel mode but other NICs not */\n+\tif (hw->mac.type != ixgbe_mac_X550 &&\n+\t hw->mac.type != ixgbe_mac_X550EM_x &&\n+\t mode != RTE_FDIR_MODE_SIGNATURE &&\n+\t mode != RTE_FDIR_MODE_PERFECT)\n+\t\treturn -ENOSYS;\n+\n \terr = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);\n \tif (err)\n \t\treturn err;\n@@ -462,7 +602,7 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)\n \tfor (i = 1; i < 8; i++)\n \t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);\n \n-\terr = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);\n+\terr = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);\n \tif (err < 0) {\n \t\tPMD_INIT_LOG(ERR, \" Error on setting FD mask\");\n \t\treturn err;\n@@ -488,7 +628,7 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)\n */\n static int\n ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,\n-\t\tunion ixgbe_atr_input *input)\n+\t\tunion ixgbe_atr_input *input, enum rte_fdir_mode mode)\n {\n \tinput->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;\n \tinput->formatted.flex_bytes = (uint16_t)(\n@@ -521,8 +661,7 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,\n \t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(ERR, \" Error on flow_type input\");\n-\t\treturn -EINVAL;\n+\t\tbreak;\n \t}\n \n \tswitch (fdir_filter->input.flow_type) {\n@@ -558,8 +697,23 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,\n \t\t\t sizeof(input->formatted.dst_ip));\n \t\tbreak;\n \tdefault:\n-\t\tPMD_DRV_LOG(ERR, \" Error on flow_type input\");\n-\t\treturn -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\tif (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {\n+\t\trte_memcpy(\n+\t\t\tinput->formatted.inner_mac,\n+\t\t\tfdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,\n+\t\t\tsizeof(input->formatted.inner_mac));\n+\t} else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {\n+\t\trte_memcpy(\n+\t\t\tinput->formatted.inner_mac,\n+\t\t\tfdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,\n+\t\t\tsizeof(input->formatted.inner_mac));\n+\t\tinput->formatted.tunnel_type =\n+\t\t\tfdir_filter->input.flow.tunnel_flow.tunnel_type;\n+\t\tinput->formatted.tni_vni =\n+\t\t\tfdir_filter->input.flow.tunnel_flow.tunnel_id;\n \t}\n \n \treturn 0;\n@@ -743,20 +897,52 @@ atr_compute_sig_hash_82599(union ixgbe_atr_input *input,\n static int\n fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \t\t\tunion ixgbe_atr_input *input, uint8_t queue,\n-\t\t\tuint32_t fdircmd, uint32_t fdirhash)\n+\t\t\tuint32_t fdircmd, uint32_t fdirhash,\n+\t\t\tenum rte_fdir_mode mode)\n {\n \tuint32_t fdirport, fdirvlan;\n+\tu32 addr_low, addr_high;\n+\tu32 tunnel_type = 0;\n \tint err = 0;\n \n-\t/* record the IPv4 address (big-endian) */\n-\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);\n-\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);\n-\n-\t/* record source and destination port (little-endian)*/\n-\tfdirport = IXGBE_NTOHS(input->formatted.dst_port);\n-\tfdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;\n-\tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n-\tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n+\tif (mode == RTE_FDIR_MODE_PERFECT) {\n+\t\t/* record the IPv4 address (big-endian) */\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA,\n+\t\t\t\tinput->formatted.src_ip[0]);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA,\n+\t\t\t\tinput->formatted.dst_ip[0]);\n+\n+\t\t/* record source and destination port (little-endian)*/\n+\t\tfdirport = IXGBE_NTOHS(input->formatted.dst_port);\n+\t\tfdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;\n+\t\tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n+\t} else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&\n+\t\t mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {\n+\t\t/* for mac vlan and tunnel modes */\n+\t\taddr_low = ((u32)input->formatted.inner_mac[0] |\n+\t\t\t ((u32)input->formatted.inner_mac[1] << 8) |\n+\t\t\t ((u32)input->formatted.inner_mac[2] << 16) |\n+\t\t\t ((u32)input->formatted.inner_mac[3] << 24));\n+\t\taddr_high = ((u32)input->formatted.inner_mac[4] |\n+\t\t\t ((u32)input->formatted.inner_mac[5] << 8));\n+\n+\t\tif (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);\n+\t\t} else {\n+\t\t\t/* tunnel mode */\n+\t\t\tif (input->formatted.tunnel_type !=\n+\t\t\t\tRTE_FDIR_TUNNEL_TYPE_NVGRE)\n+\t\t\t\ttunnel_type = 0x80000000;\n+\t\t\ttunnel_type |= addr_high;\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),\n+\t\t\t\t\tinput->formatted.tni_vni);\n+\t\t}\n+\t}\n \n \t/* record vlan (little-endian) and flex_bytes(big-endian) */\n \tfdirvlan = input->formatted.flex_bytes;\n@@ -894,8 +1080,9 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,\n \tint err;\n \tstruct ixgbe_hw_fdir_info *info =\n \t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n+\tenum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;\n \n-\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)\n+\tif (fdir_mode == RTE_FDIR_MODE_NONE)\n \t\treturn -ENOTSUP;\n \n \t/*\n@@ -917,12 +1104,14 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,\n \t\treturn -ENOTSUP;\n \t}\n \n-\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)\n+\tif (fdir_mode >= RTE_FDIR_MODE_PERFECT &&\n+\t fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)\n \t\tis_perfect = TRUE;\n \n \tmemset(&input, 0, sizeof(input));\n \n-\terr = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);\n+\terr = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input,\n+\t\t\t\t\t fdir_mode);\n \tif (err)\n \t\treturn err;\n \n@@ -966,7 +1155,8 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,\n \n \tif (is_perfect) {\n \t\terr = fdir_write_perfect_filter_82599(hw, &input, queue,\n-\t\t\t\tfdircmd_flags, fdirhash);\n+\t\t\t\tfdircmd_flags, fdirhash,\n+\t\t\t\tfdir_mode);\n \t} else {\n \t\terr = fdir_add_signature_filter_82599(hw, &input, queue,\n \t\t\t\tfdircmd_flags, fdirhash);\n@@ -1018,7 +1208,8 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info\n \tfdir_info->mode = dev->data->dev_conf.fdir_conf.mode;\n \tmax_num = (1 << (FDIRENTRIES_NUM_SHIFT +\n \t\t\t(fdirctrl & FDIRCTRL_PBALLOC_MASK)));\n-\tif (fdir_info->mode == RTE_FDIR_MODE_PERFECT)\n+\tif (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&\n+\t fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)\n \t\tfdir_info->guarant_spc = max_num;\n \telse if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)\n \t\tfdir_info->guarant_spc = max_num * 4;\n@@ -1032,11 +1223,20 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info\n \t\t\tfdir_info->mask.ipv6_mask.dst_ip);\n \tfdir_info->mask.src_port_mask = info->mask.src_port_mask;\n \tfdir_info->mask.dst_port_mask = info->mask.dst_port_mask;\n+\tfdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;\n+\tfdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;\n+\tfdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;\n \tfdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;\n-\tfdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;\n+\n+\tif (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||\n+\t fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)\n+\t\tfdir_info->flow_types_mask[0] = 0;\n+\telse\n+\t\tfdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;\n+\n \tfdir_info->flex_payload_unit = sizeof(uint16_t);\n \tfdir_info->max_flex_payload_segment_num = 1;\n-\tfdir_info->flex_payload_limit = 62;\n+\tfdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;\n \tfdir_info->flex_conf.nb_payloads = 1;\n \tfdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;\n \tfdir_info->flex_conf.flex_set[0].src_offset[0] = offset;\n@@ -1056,6 +1256,7 @@ ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_st\n \tstruct ixgbe_hw_fdir_info *info =\n \t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n \tuint32_t reg, max_num;\n+\tenum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;\n \n \t/* Get the information from registers */\n \treg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);\n@@ -1095,9 +1296,10 @@ ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_st\n \treg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);\n \tmax_num = (1 << (FDIRENTRIES_NUM_SHIFT +\n \t\t\t(reg & FDIRCTRL_PBALLOC_MASK)));\n-\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)\n+\tif (fdir_mode >= RTE_FDIR_MODE_PERFECT &&\n+\t fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)\n \t\t\tfdir_stats->guarant_cnt = max_num - fdir_stats->free;\n-\telse if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)\n+\telse if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)\n \t\tfdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;\n \n }\n", "prefixes": [ "dpdk-dev", "v5", "6/7" ] }