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GET /api/patches/79672/?format=api
{ "id": 79672, "url": "https://patches.dpdk.org/api/patches/79672/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-55-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005120910.189343-55-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-55-jiawenwu@trustnetic.com", "date": "2020-10-05T12:09:08", "name": "[v2,54/56] net/txgbe: add PTP support", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b91774019ca0a0876b7830aa4127e9e02aeadbd4", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-55-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12690, "url": "https://patches.dpdk.org/api/series/12690/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12690", "date": "2020-10-05T12:08:14", "name": "net: txgbe PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/12690/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79672/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/79672/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EFBC6A04B1;\n\tMon, 5 Oct 2020 14:31:04 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 708871C1BB;\n\tMon, 5 Oct 2020 14:10:16 +0200 (CEST)", "from qq.com (smtpbg550.qq.com [183.3.226.152])\n by dpdk.org (Postfix) with ESMTP id 9D4E81BF6D\n for <dev@dpdk.org>; Mon, 5 Oct 2020 14:09:47 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 05 Oct 2020 20:09:43 +0800 (CST)" ], "X-QQ-mid": "bizesmtp9t1601899783tik3o4yhu", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "ql6Zc2TW8JwKNakl70pU614m6j36ox44EnRBedeVjrw1+2kcOQlhn1Sb8kN5E\n TjKxH2klejFAT8xLXYhi40aLUaBy7Af87fui8UbXhTTSOV2+hrTX8b3njapnwvty1KPtIjp\n vQ3PoBFSYM8SJ813Kq35gPbGBIkPyIZM2tILmT5kGS9asOal3TkgXSj7lckBCyTee/eLF9h\n 5vlhcPyGKD8eA1ztQD1MpXaxw57QJ8Ep6R0pQ5noUAXsSURa5J/z6xqWWrtQ0zvdFL7yuIk\n tPQZyUsUn2TPYPBNI4UA7/DjKDqfaDQLgxhLFttZQqvUS6r8y4cf/JlV1o69rTPl310m/k9\n oFw3DYr4zWfIDdVhX4=", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "jiawenwu <jiawenwu@trustnetic.com>", "Date": "Mon, 5 Oct 2020 20:09:08 +0800", "Message-Id": "<20201005120910.189343-55-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgweb:qybgweb11", "Subject": "[dpdk-dev] [PATCH v2 54/56] net/txgbe: add PTP support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd PTP support.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n doc/guides/nics/txgbe.rst | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 234 +++++++++++++++++++++++++++++\n drivers/net/txgbe/txgbe_ethdev.h | 22 +++\n drivers/net/txgbe/txgbe_rxtx.c | 31 +++-\n 5 files changed, 287 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex a57a1f04f..1684bcc7e 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -36,6 +36,7 @@ L4 checksum offload = P\n Inner L3 checksum = P\n Inner L4 checksum = P\n Packet type parsing = Y\n+Timesync = Y\n Basic stats = Y\n Extended stats = Y\n Stats per queue = Y\ndiff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst\nindex 7865b87aa..76da3d859 100644\n--- a/doc/guides/nics/txgbe.rst\n+++ b/doc/guides/nics/txgbe.rst\n@@ -26,6 +26,7 @@ Features\n - Interrupt mode for RX\n - Scattered and gather for TX and RX\n - DCB\n+- IEEE 1588\n - FW version\n - LRO\n \ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex 3b4a67293..c59b582d2 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -3679,6 +3679,233 @@ txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t\t txgbe_dev_addr_list_itr, TRUE);\n }\n \n+static uint64_t\n+txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint64_t systime_cycles;\n+\n+\tsystime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);\n+\tsystime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;\n+\n+\treturn systime_cycles;\n+}\n+\n+static uint64_t\n+txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint64_t rx_tstamp_cycles;\n+\n+\t/* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */\n+\trx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);\n+\trx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;\n+\n+\treturn rx_tstamp_cycles;\n+}\n+\n+static uint64_t\n+txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint64_t tx_tstamp_cycles;\n+\n+\t/* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */\n+\ttx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);\n+\ttx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;\n+\n+\treturn tx_tstamp_cycles;\n+}\n+\n+static void\n+txgbe_start_timecounters(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\tstruct rte_eth_link link;\n+\tuint32_t incval = 0;\n+\tuint32_t shift = 0;\n+\n+\t/* Get current link speed. */\n+\ttxgbe_dev_link_update(dev, 1);\n+\trte_eth_linkstatus_get(dev, &link);\n+\n+\tswitch (link.link_speed) {\n+\tcase ETH_SPEED_NUM_100M:\n+\t\tincval = TXGBE_INCVAL_100;\n+\t\tshift = TXGBE_INCVAL_SHIFT_100;\n+\t\tbreak;\n+\tcase ETH_SPEED_NUM_1G:\n+\t\tincval = TXGBE_INCVAL_1GB;\n+\t\tshift = TXGBE_INCVAL_SHIFT_1GB;\n+\t\tbreak;\n+\tcase ETH_SPEED_NUM_10G:\n+\tdefault:\n+\t\tincval = TXGBE_INCVAL_10GB;\n+\t\tshift = TXGBE_INCVAL_SHIFT_10GB;\n+\t\tbreak;\n+\t}\n+\n+\twr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));\n+\n+\tmemset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\n+\tadapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;\n+\tadapter->systime_tc.cc_shift = shift;\n+\tadapter->systime_tc.nsec_mask = (1ULL << shift) - 1;\n+\n+\tadapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;\n+\tadapter->rx_tstamp_tc.cc_shift = shift;\n+\tadapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;\n+\n+\tadapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;\n+\tadapter->tx_tstamp_tc.cc_shift = shift;\n+\tadapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;\n+}\n+\n+static int\n+txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\n+\tadapter->systime_tc.nsec += delta;\n+\tadapter->rx_tstamp_tc.nsec += delta;\n+\tadapter->tx_tstamp_tc.nsec += delta;\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\n+\tns = rte_timespec_to_ns(ts);\n+\t/* Set the timecounters to a new value. */\n+\tadapter->systime_tc.nsec = ns;\n+\tadapter->rx_tstamp_tc.nsec = ns;\n+\tadapter->tx_tstamp_tc.nsec = ns;\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns, systime_cycles;\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\n+\tsystime_cycles = txgbe_read_systime_cyclecounter(dev);\n+\tns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);\n+\t*ts = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t tsync_ctl;\n+\n+\t/* Stop the timesync system time. */\n+\twr32(hw, TXGBE_TSTIMEINC, 0x0);\n+\t/* Reset the timesync system time value. */\n+\twr32(hw, TXGBE_TSTIMEL, 0x0);\n+\twr32(hw, TXGBE_TSTIMEH, 0x0);\n+\n+\ttxgbe_start_timecounters(dev);\n+\n+\t/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n+\twr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),\n+\t\tRTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);\n+\n+\t/* Enable timestamping of received PTP packets. */\n+\ttsync_ctl = rd32(hw, TXGBE_TSRXCTL);\n+\ttsync_ctl |= TXGBE_TSRXCTL_ENA;\n+\twr32(hw, TXGBE_TSRXCTL, tsync_ctl);\n+\n+\t/* Enable timestamping of transmitted PTP packets. */\n+\ttsync_ctl = rd32(hw, TXGBE_TSTXCTL);\n+\ttsync_ctl |= TXGBE_TSTXCTL_ENA;\n+\twr32(hw, TXGBE_TSTXCTL, tsync_ctl);\n+\n+\ttxgbe_flush(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t tsync_ctl;\n+\n+\t/* Disable timestamping of transmitted PTP packets. */\n+\ttsync_ctl = rd32(hw, TXGBE_TSTXCTL);\n+\ttsync_ctl &= ~TXGBE_TSTXCTL_ENA;\n+\twr32(hw, TXGBE_TSTXCTL, tsync_ctl);\n+\n+\t/* Disable timestamping of received PTP packets. */\n+\ttsync_ctl = rd32(hw, TXGBE_TSRXCTL);\n+\ttsync_ctl &= ~TXGBE_TSRXCTL_ENA;\n+\twr32(hw, TXGBE_TSRXCTL, tsync_ctl);\n+\n+\t/* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n+\twr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);\n+\n+\t/* Stop incrementating the System Time registers. */\n+\twr32(hw, TXGBE_TSTIMEINC, 0);\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp,\n+\t\t\t\t uint32_t flags __rte_unused)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\tuint32_t tsync_rxctl;\n+\tuint64_t rx_tstamp_cycles;\n+\tuint64_t ns;\n+\n+\ttsync_rxctl = rd32(hw, TXGBE_TSRXCTL);\n+\tif ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)\n+\t\treturn -EINVAL;\n+\n+\trx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);\n+\tns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);\n+\tuint32_t tsync_txctl;\n+\tuint64_t tx_tstamp_cycles;\n+\tuint64_t ns;\n+\n+\ttsync_txctl = rd32(hw, TXGBE_TSTXCTL);\n+\tif ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)\n+\t\treturn -EINVAL;\n+\n+\ttx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);\n+\tns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n static int\n txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n {\n@@ -3916,12 +4143,19 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.set_mc_addr_list = txgbe_dev_set_mc_addr_list,\n \t.rxq_info_get = txgbe_rxq_info_get,\n \t.txq_info_get = txgbe_txq_info_get,\n+\t.timesync_enable = txgbe_timesync_enable,\n+\t.timesync_disable = txgbe_timesync_disable,\n+\t.timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,\n+\t.timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,\n \t.get_reg = txgbe_get_regs,\n \t.get_eeprom_length = txgbe_get_eeprom_length,\n \t.get_eeprom = txgbe_get_eeprom,\n \t.set_eeprom = txgbe_set_eeprom,\n \t.get_module_info = txgbe_get_module_info,\n \t.get_module_eeprom = txgbe_get_module_eeprom,\n+\t.timesync_adjust_time = txgbe_timesync_adjust_time,\n+\t.timesync_read_time = txgbe_timesync_read_time,\n+\t.timesync_write_time = txgbe_timesync_write_time,\n };\n \n RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex 93f6a0f20..66ba8db39 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -5,8 +5,11 @@\n #ifndef _TXGBE_ETHDEV_H_\n #define _TXGBE_ETHDEV_H_\n \n+#include <stdint.h>\n+\n #include \"base/txgbe.h\"\n #include \"txgbe_ptypes.h\"\n+#include <rte_time.h>\n \n /* need update link, bit flag */\n #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n@@ -148,6 +151,10 @@ struct txgbe_adapter {\n \tstruct txgbe_filter_info filter;\n \tstruct txgbe_bw_conf bw_conf;\n \tbool rx_bulk_alloc_allowed;\n+\tstruct rte_timecounter systime_tc;\n+\tstruct rte_timecounter rx_tstamp_tc;\n+\tstruct rte_timecounter tx_tstamp_tc;\n+\n \t/* For RSS reta table update */\n \tuint8_t rss_reta_updated;\n };\n@@ -352,6 +359,21 @@ txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,\n #define TXGBE_DEFAULT_TX_HTHRESH 0\n #define TXGBE_DEFAULT_TX_WTHRESH 0\n \n+/* Additional timesync values. */\n+#define NSEC_PER_SEC 1000000000L\n+#define TXGBE_INCVAL_10GB 0xCCCCCC\n+#define TXGBE_INCVAL_1GB 0x800000\n+#define TXGBE_INCVAL_100 0xA00000\n+#define TXGBE_INCVAL_10 0xC7F380\n+#define TXGBE_INCVAL_FPGA 0x800000\n+#define TXGBE_INCVAL_SHIFT_10GB 20\n+#define TXGBE_INCVAL_SHIFT_1GB 18\n+#define TXGBE_INCVAL_SHIFT_100 15\n+#define TXGBE_INCVAL_SHIFT_10 12\n+#define TXGBE_INCVAL_SHIFT_FPGA 17\n+\n+#define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n+\n /* store statistics names and its offset in stats structure */\n struct rte_txgbe_xstats_name_off {\n \tchar name[RTE_ETH_XSTATS_NAME_SIZE];\ndiff --git a/drivers/net/txgbe/txgbe_rxtx.c b/drivers/net/txgbe/txgbe_rxtx.c\nindex d0e40d18c..12fc49165 100644\n--- a/drivers/net/txgbe/txgbe_rxtx.c\n+++ b/drivers/net/txgbe/txgbe_rxtx.c\n@@ -39,6 +39,11 @@\n #include \"txgbe_ethdev.h\"\n #include \"txgbe_rxtx.h\"\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+#define TXGBE_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST\n+#else\n+#define TXGBE_TX_IEEE1588_TMST 0\n+#endif\n /* Bit Mask to indicate what bits required for building TX context */\n static const u64 TXGBE_TX_OFFLOAD_MASK = (\n \t\tPKT_TX_OUTER_IPV6 |\n@@ -50,7 +55,8 @@ static const u64 TXGBE_TX_OFFLOAD_MASK = (\n \t\tPKT_TX_L4_MASK |\n \t\tPKT_TX_TCP_SEG |\n \t\tPKT_TX_TUNNEL_MASK |\n-\t\tPKT_TX_OUTER_IP_CKSUM);\n+\t\tPKT_TX_OUTER_IP_CKSUM |\n+\t\tTXGBE_TX_IEEE1588_TMST);\n \n #define TXGBE_TX_OFFLOAD_NOTSUP_MASK \\\n \t\t(PKT_TX_OFFLOAD_MASK ^ TXGBE_TX_OFFLOAD_MASK)\n@@ -866,6 +872,11 @@ txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t */\n \t\tcmd_type_len = TXGBE_TXD_FCS;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\t\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n+\t\t\tcmd_type_len |= TXGBE_TXD_1588;\n+#endif\n+\n \t\tolinfo_status = 0;\n \t\tif (tx_ol_req) {\n \n@@ -1042,8 +1053,20 @@ txgbe_rxd_pkt_info_to_pkt_flags(uint32_t pkt_info)\n \t\tPKT_RX_RSS_HASH, 0, 0, 0,\n \t\t0, 0, 0, PKT_RX_FDIR,\n \t};\n-\n+#ifdef RTE_LIBRTE_IEEE1588\n+\tstatic uint64_t ip_pkt_etqf_map[8] = {\n+\t\t0, 0, 0, PKT_RX_IEEE1588_PTP,\n+\t\t0, 0, 0, 0,\n+\t};\n+\tint etfid = txgbe_etflt_id(TXGBE_RXD_PTID(pkt_info));\n+\tif (likely(-1 != etfid))\n+\t\treturn ip_pkt_etqf_map[etfid] |\n+\t\t ip_rss_types_map[TXGBE_RXD_RSSTYPE(pkt_info)];\n+\telse\n+\t\treturn ip_rss_types_map[TXGBE_RXD_RSSTYPE(pkt_info)];\n+#else\n \treturn ip_rss_types_map[TXGBE_RXD_RSSTYPE(pkt_info)];\n+#endif\n }\n \n static inline uint64_t\n@@ -1060,6 +1083,10 @@ rx_desc_status_to_pkt_flags(uint32_t rx_status, uint64_t vlan_flags)\n \t\t vlan_flags & PKT_RX_VLAN_STRIPPED)\n \t\t ? vlan_flags : 0;\n \n+#ifdef RTE_LIBRTE_IEEE1588\n+\tif (rx_status & TXGBE_RXD_STAT_1588)\n+\t\tpkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;\n+#endif\n \treturn pkt_flags;\n }\n \n", "prefixes": [ "v2", "54/56" ] }