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GET /api/patches/79658/?format=api
{ "id": 79658, "url": "https://patches.dpdk.org/api/patches/79658/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-41-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005120910.189343-41-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-41-jiawenwu@trustnetic.com", "date": "2020-10-05T12:08:54", "name": "[v2,40/56] net/txgbe: add PF module configure for SRIOV", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a5b04c14941f630a37eb90080240bfba13b9446a", "submitter": { "id": 1932, "url": "https://patches.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-41-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 12690, "url": "https://patches.dpdk.org/api/series/12690/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12690", "date": "2020-10-05T12:08:14", "name": "net: txgbe PMD", "version": 2, "mbox": "https://patches.dpdk.org/series/12690/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79658/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/79658/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 847E9A04B1;\n\tMon, 5 Oct 2020 14:25:47 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B8A881C0DA;\n\tMon, 5 Oct 2020 14:09:55 +0200 (CEST)", "from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166])\n by dpdk.org (Postfix) with ESMTP id 1B41E1BEA5\n for <dev@dpdk.org>; Mon, 5 Oct 2020 14:09:33 +0200 (CEST)", "from localhost.localdomain.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Mon, 05 Oct 2020 20:09:27 +0800 (CST)" ], "X-QQ-mid": "bizesmtp9t1601899768twze2sn4q", "X-QQ-SSF": "01400000002000C0C000B00A0000000", "X-QQ-FEAT": "VP6n2TeHyWXii3KRyVAM/RnMAnWSnp/pPhX0J/9Pah0ZVg2hbJFeP8eFxD58N\n hNXYvqtOuKQBKyCt/6HqqKIg7rfHqgnne3V0I2PPd13btbQRODGxFqJ1vkCVzRihsecq6HX\n 8ieS/yAkq6TyUCEfZz4319TgBjQGs7WSAiZkRKj6OFE4BCO5S01eKQSR9FTwBKicpacsg+q\n rQ53E2nIXdJMv1LoEV3sfr+6znou2pddBCKkuVAYy6Bzz6UurBPznHqoO49D4MmROVgottk\n O5ulnTthuww9qgmnP2sTEQZWXB7vdNHAMe8MizfJyL63XVXPAA6cpjvUaLDR2pzqwoGM3C2\n RQrImgv", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "jiawenwu <jiawenwu@trustnetic.com>", "Date": "Mon, 5 Oct 2020 20:08:54 +0800", "Message-Id": "<20201005120910.189343-41-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.18.4", "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v2 40/56] net/txgbe: add PF module configure for\n\tSRIOV", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd PF module configure for SRIOV.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/txgbe.ini | 1 +\n drivers/net/txgbe/base/txgbe_hw.c | 345 ++++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_hw.h | 12 +\n drivers/net/txgbe/base/txgbe_type.h | 1 +\n drivers/net/txgbe/txgbe_ethdev.c | 129 +++++++++++\n drivers/net/txgbe/txgbe_ethdev.h | 71 ++++++\n drivers/net/txgbe/txgbe_pf.c | 140 +++++++++++\n 7 files changed, 699 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini\nindex 1d00f3105..022e56d45 100644\n--- a/doc/guides/nics/features/txgbe.ini\n+++ b/doc/guides/nics/features/txgbe.ini\n@@ -17,6 +17,7 @@ Unicast MAC filter = Y\n Multicast MAC filter = Y\n SR-IOV = Y\n VLAN filter = Y\n+Rate limitation = Y\n CRC offload = P\n VLAN offload = P\n QinQ offload = P\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex de47f8fc9..99a394ab0 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -969,6 +969,92 @@ s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)\n \treturn 0;\n }\n \n+/**\n+ * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to disassociate\n+ * @vmdq: VMDq pool index to remove from the rar\n+ **/\n+s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)\n+{\n+\tu32 mpsar_lo, mpsar_hi;\n+\tu32 rar_entries = hw->mac.num_rar_entries;\n+\n+\tDEBUGFUNC(\"txgbe_clear_vmdq\");\n+\n+\t/* Make sure we are using a valid rar index range */\n+\tif (rar >= rar_entries) {\n+\t\tDEBUGOUT(\"RAR index %d is out of range.\\n\", rar);\n+\t\treturn TXGBE_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\twr32(hw, TXGBE_ETHADDRIDX, rar);\n+\tmpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);\n+\tmpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);\n+\n+\tif (TXGBE_REMOVED(hw->hw_addr))\n+\t\tgoto done;\n+\n+\tif (!mpsar_lo && !mpsar_hi)\n+\t\tgoto done;\n+\n+\tif (vmdq == BIT_MASK32) {\n+\t\tif (mpsar_lo) {\n+\t\t\twr32(hw, TXGBE_ETHADDRASSL, 0);\n+\t\t\tmpsar_lo = 0;\n+\t\t}\n+\t\tif (mpsar_hi) {\n+\t\t\twr32(hw, TXGBE_ETHADDRASSH, 0);\n+\t\t\tmpsar_hi = 0;\n+\t\t}\n+\t} else if (vmdq < 32) {\n+\t\tmpsar_lo &= ~(1 << vmdq);\n+\t\twr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);\n+\t} else {\n+\t\tmpsar_hi &= ~(1 << (vmdq - 32));\n+\t\twr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);\n+\t}\n+\n+\t/* was that the last pool using this rar? */\n+\tif (mpsar_lo == 0 && mpsar_hi == 0 &&\n+\t rar != 0 && rar != hw->mac.san_mac_rar_index)\n+\t\thw->mac.clear_rar(hw, rar);\n+done:\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_set_vmdq - Associate a VMDq pool index with a rx address\n+ * @hw: pointer to hardware struct\n+ * @rar: receive address register index to associate with a VMDq index\n+ * @vmdq: VMDq pool index\n+ **/\n+s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)\n+{\n+\tu32 mpsar;\n+\tu32 rar_entries = hw->mac.num_rar_entries;\n+\n+\tDEBUGFUNC(\"txgbe_set_vmdq\");\n+\n+\t/* Make sure we are using a valid rar index range */\n+\tif (rar >= rar_entries) {\n+\t\tDEBUGOUT(\"RAR index %d is out of range.\\n\", rar);\n+\t\treturn TXGBE_ERR_INVALID_ARGUMENT;\n+\t}\n+\n+\twr32(hw, TXGBE_ETHADDRIDX, rar);\n+\tif (vmdq < 32) {\n+\t\tmpsar = rd32(hw, TXGBE_ETHADDRASSL);\n+\t\tmpsar |= 1 << vmdq;\n+\t\twr32(hw, TXGBE_ETHADDRASSL, mpsar);\n+\t} else {\n+\t\tmpsar = rd32(hw, TXGBE_ETHADDRASSH);\n+\t\tmpsar |= 1 << (vmdq - 32);\n+\t\twr32(hw, TXGBE_ETHADDRASSH, mpsar);\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * txgbe_init_uta_tables - Initialize the Unicast Table Array\n * @hw: pointer to hardware structure\n@@ -986,6 +1072,214 @@ s32 txgbe_init_uta_tables(struct txgbe_hw *hw)\n \treturn 0;\n }\n \n+/**\n+ * txgbe_find_vlvf_slot - find the vlanid or the first empty slot\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vlvf_bypass: true to find vlanid only, false returns first empty slot if\n+ *\t\t vlanid not found\n+ *\n+ *\n+ * return the VLVF index where this VLAN id should be placed\n+ *\n+ **/\n+s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)\n+{\n+\ts32 regindex, first_empty_slot;\n+\tu32 bits;\n+\n+\t/* short cut the special case */\n+\tif (vlan == 0)\n+\t\treturn 0;\n+\n+\t/* if vlvf_bypass is set we don't want to use an empty slot, we\n+\t * will simply bypass the VLVF if there are no entries present in the\n+\t * VLVF that contain our VLAN\n+\t */\n+\tfirst_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;\n+\n+\t/* add VLAN enable bit for comparison */\n+\tvlan |= TXGBE_PSRVLAN_EA;\n+\n+\t/* Search for the vlan id in the VLVF entries. Save off the first empty\n+\t * slot found along the way.\n+\t *\n+\t * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1\n+\t */\n+\tfor (regindex = TXGBE_NUM_POOL; --regindex;) {\n+\t\twr32(hw, TXGBE_PSRVLANIDX, regindex);\n+\t\tbits = rd32(hw, TXGBE_PSRVLAN);\n+\t\tif (bits == vlan)\n+\t\t\treturn regindex;\n+\t\tif (!first_empty_slot && !bits)\n+\t\t\tfirst_empty_slot = regindex;\n+\t}\n+\n+\t/* If we are here then we didn't find the VLAN. Return first empty\n+\t * slot we found during our search, else error.\n+\t */\n+\tif (!first_empty_slot)\n+\t\tDEBUGOUT(\"No space in VLVF.\\n\");\n+\n+\treturn first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;\n+}\n+\n+/**\n+ * txgbe_set_vfta - Set VLAN filter table\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in VLVFB\n+ * @vlan_on: boolean flag to turn on/off VLAN\n+ * @vlvf_bypass: boolean flag indicating updating default pool is okay\n+ *\n+ * Turn on/off specified VLAN in the VLAN filter table.\n+ **/\n+s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,\n+\t\t\t bool vlan_on, bool vlvf_bypass)\n+{\n+\tu32 regidx, vfta_delta, vfta;\n+\ts32 err;\n+\n+\tDEBUGFUNC(\"txgbe_set_vfta\");\n+\n+\tif (vlan > 4095 || vind > 63)\n+\t\treturn TXGBE_ERR_PARAM;\n+\n+\t/*\n+\t * this is a 2 part operation - first the VFTA, then the\n+\t * VLVF and VLVFB if VT Mode is set\n+\t * We don't write the VFTA until we know the VLVF part succeeded.\n+\t */\n+\n+\t/* Part 1\n+\t * The VFTA is a bitstring made up of 128 32-bit registers\n+\t * that enable the particular VLAN id, much like the MTA:\n+\t * bits[11-5]: which register\n+\t * bits[4-0]: which bit in the register\n+\t */\n+\tregidx = vlan / 32;\n+\tvfta_delta = 1 << (vlan % 32);\n+\tvfta = rd32(hw, TXGBE_VLANTBL(regidx));\n+\n+\t/*\n+\t * vfta_delta represents the difference between the current value\n+\t * of vfta and the value we want in the register. Since the diff\n+\t * is an XOR mask we can just update the vfta using an XOR\n+\t */\n+\tvfta_delta &= vlan_on ? ~vfta : vfta;\n+\tvfta ^= vfta_delta;\n+\n+\t/* Part 2\n+\t * Call txgbe_set_vlvf to set VLVFB and VLVF\n+\t */\n+\terr = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,\n+\t\t\t\t\t vfta, vlvf_bypass);\n+\tif (err != 0) {\n+\t\tif (vlvf_bypass)\n+\t\t\tgoto vfta_update;\n+\t\treturn err;\n+\t}\n+\n+vfta_update:\n+\t/* Update VFTA now that we are ready for traffic */\n+\tif (vfta_delta)\n+\t\twr32(hw, TXGBE_VLANTBL(regidx), vfta);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * txgbe_set_vlvf - Set VLAN Pool Filter\n+ * @hw: pointer to hardware structure\n+ * @vlan: VLAN id to write to VLAN filter\n+ * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM\n+ * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN\n+ * @vfta_delta: pointer to the difference between the current value\n+ *\t\t of PSRVLANPLM and the desired value\n+ * @vfta: the desired value of the VFTA\n+ * @vlvf_bypass: boolean flag indicating updating default pool is okay\n+ *\n+ * Turn on/off specified bit in VLVF table.\n+ **/\n+s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,\n+\t\t\t bool vlan_on, u32 *vfta_delta, u32 vfta,\n+\t\t\t bool vlvf_bypass)\n+{\n+\tu32 bits;\n+\tu32 portctl;\n+\ts32 vlvf_index;\n+\n+\tDEBUGFUNC(\"txgbe_set_vlvf\");\n+\n+\tif (vlan > 4095 || vind > 63)\n+\t\treturn TXGBE_ERR_PARAM;\n+\n+\t/* If VT Mode is set\n+\t * Either vlan_on\n+\t * make sure the vlan is in PSRVLAN\n+\t * set the vind bit in the matching PSRVLANPLM\n+\t * Or !vlan_on\n+\t * clear the pool bit and possibly the vind\n+\t */\n+\tportctl = rd32(hw, TXGBE_PORTCTL);\n+\tif (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))\n+\t\treturn 0;\n+\n+\tvlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);\n+\tif (vlvf_index < 0)\n+\t\treturn vlvf_index;\n+\n+\twr32(hw, TXGBE_PSRVLANIDX, vlvf_index);\n+\tbits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));\n+\n+\t/* set the pool bit */\n+\tbits |= 1 << (vind % 32);\n+\tif (vlan_on)\n+\t\tgoto vlvf_update;\n+\n+\t/* clear the pool bit */\n+\tbits ^= 1 << (vind % 32);\n+\n+\tif (!bits &&\n+\t !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {\n+\t\t/* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise\n+\t\t * we run the risk of stray packets leaking into\n+\t\t * the PF via the default pool\n+\t\t */\n+\t\tif (*vfta_delta)\n+\t\t\twr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);\n+\n+\t\t/* disable VLVF and clear remaining bit from pool */\n+\t\twr32(hw, TXGBE_PSRVLAN, 0);\n+\t\twr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);\n+\n+\t\treturn 0;\n+\t}\n+\n+\t/* If there are still bits set in the PSRVLANPLM registers\n+\t * for the VLAN ID indicated we need to see if the\n+\t * caller is requesting that we clear the PSRVLANPLM entry bit.\n+\t * If the caller has requested that we clear the PSRVLANPLM\n+\t * entry bit but there are still pools/VFs using this VLAN\n+\t * ID entry then ignore the request. We're not worried\n+\t * about the case where we're turning the PSRVLANPLM VLAN ID\n+\t * entry bit on, only when requested to turn it off as\n+\t * there may be multiple pools and/or VFs using the\n+\t * VLAN ID entry. In that case we cannot clear the\n+\t * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also\n+\t * been cleared. This will be indicated by \"bits\" being\n+\t * zero.\n+\t */\n+\t*vfta_delta = 0;\n+\n+vlvf_update:\n+\t/* record pool change and enable VLAN ID if not already enabled */\n+\twr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);\n+\twr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);\n+\n+\treturn 0;\n+}\n+\n /**\n * txgbe_clear_vfta - Clear VLAN filter table\n * @hw: pointer to hardware structure\n@@ -1179,6 +1473,49 @@ s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,\n \treturn 0;\n }\n \n+/**\n+ * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for MAC anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing\n+ *\n+ **/\n+void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)\n+{\n+\tint vf_target_reg = vf >> 3;\n+\tint vf_target_shift = vf % 8;\n+\tu32 pfvfspoof;\n+\n+\tpfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));\n+\tif (enable)\n+\t\tpfvfspoof |= (1 << vf_target_shift);\n+\telse\n+\t\tpfvfspoof &= ~(1 << vf_target_shift);\n+\twr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);\n+}\n+\n+/**\n+ * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing\n+ * @hw: pointer to hardware structure\n+ * @enable: enable or disable switch for Ethertype anti-spoofing\n+ * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n+ *\n+ **/\n+void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,\n+\t\tbool enable, int vf)\n+{\n+\tint vf_target_reg = vf >> 3;\n+\tint vf_target_shift = vf % 8;\n+\tu32 pfvfspoof;\n+\n+\tpfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));\n+\tif (enable)\n+\t\tpfvfspoof |= (1 << vf_target_shift);\n+\telse\n+\t\tpfvfspoof &= ~(1 << vf_target_shift);\n+\twr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);\n+}\n+\n /**\n * txgbe_get_device_caps - Get additional device capabilities\n * @hw: pointer to hardware structure\n@@ -1754,14 +2091,22 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)\n \tmac->autoc_read = txgbe_autoc_read;\n \tmac->autoc_write = txgbe_autoc_write;\n \n+\t/* RAR, Multicast, VLAN */\n \tmac->set_rar = txgbe_set_rar;\n \tmac->clear_rar = txgbe_clear_rar;\n \tmac->init_rx_addrs = txgbe_init_rx_addrs;\n \tmac->enable_rx = txgbe_enable_rx;\n \tmac->disable_rx = txgbe_disable_rx;\n+\tmac->set_vmdq = txgbe_set_vmdq;\n+\tmac->clear_vmdq = txgbe_clear_vmdq;\n+\tmac->set_vfta = txgbe_set_vfta;\n+\tmac->set_vlvf = txgbe_set_vlvf;\n \tmac->clear_vfta = txgbe_clear_vfta;\n \tmac->init_uta_tables = txgbe_init_uta_tables;\n \tmac->setup_sfp = txgbe_setup_sfp_modules;\n+\tmac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;\n+\tmac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;\n+\n \t/* Link */\n \tmac->get_link_capabilities = txgbe_get_link_capabilities_raptor;\n \tmac->check_link = txgbe_check_mac_link;\ndiff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h\nindex 60e02f5e7..a3466340e 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.h\n+++ b/drivers/net/txgbe/base/txgbe_hw.h\n@@ -35,8 +35,17 @@ void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask);\n s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr);\n s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr);\n \n+s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);\n+s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);\n s32 txgbe_init_uta_tables(struct txgbe_hw *hw);\n+s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan,\n+\t\t\t u32 vind, bool vlan_on, bool vlvf_bypass);\n+s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,\n+\t\t\t bool vlan_on, u32 *vfta_delta, u32 vfta,\n+\t\t\t bool vlvf_bypass);\n s32 txgbe_clear_vfta(struct txgbe_hw *hw);\n+s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass);\n+\n s32 txgbe_check_mac_link(struct txgbe_hw *hw,\n \t\t\t u32 *speed,\n \t\t\t bool *link_up, bool link_up_wait_to_complete);\n@@ -44,6 +53,9 @@ s32 txgbe_check_mac_link(struct txgbe_hw *hw,\n s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,\n \t\t\t\t u16 *wwpn_prefix);\n \n+void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf);\n+void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,\n+\t\tbool enable, int vf);\n s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps);\n void txgbe_clear_tx_pending(struct txgbe_hw *hw);\n \ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 9ee542407..a7bdb259d 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -5,6 +5,7 @@\n #ifndef _TXGBE_TYPE_H_\n #define _TXGBE_TYPE_H_\n \n+#define TXGBE_DCB_TC_MAX\tTXGBE_MAX_UP\n #define TXGBE_LINK_UP_TIME\t90 /* 9.0 Seconds */\n #define TXGBE_AUTO_NEG_TIME\t45 /* 4.5 Seconds */\n \ndiff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c\nindex ee758ba2c..ab25086b3 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.c\n+++ b/drivers/net/txgbe/txgbe_ethdev.c\n@@ -1152,6 +1152,83 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)\n \tintr->mask_misc |= TXGBE_ICRMISC_GPIO;\n }\n \n+int\n+txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n+\t\t\tuint16_t tx_rate, uint64_t q_msk)\n+{\n+\tstruct txgbe_hw *hw;\n+\tstruct txgbe_vf_info *vfinfo;\n+\tstruct rte_eth_link link;\n+\tuint8_t nb_q_per_pool;\n+\tuint32_t queue_stride;\n+\tuint32_t queue_idx, idx = 0, vf_idx;\n+\tuint32_t queue_end;\n+\tuint16_t total_rate = 0;\n+\tstruct rte_pci_device *pci_dev;\n+\tint ret;\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tret = rte_eth_link_get_nowait(dev->data->port_id, &link);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tif (vf >= pci_dev->max_vfs)\n+\t\treturn -EINVAL;\n+\n+\tif (tx_rate > link.link_speed)\n+\t\treturn -EINVAL;\n+\n+\tif (q_msk == 0)\n+\t\treturn 0;\n+\n+\thw = TXGBE_DEV_HW(dev);\n+\tvfinfo = *(TXGBE_DEV_VFDATA(dev));\n+\tnb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;\n+\tqueue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;\n+\tqueue_idx = vf * queue_stride;\n+\tqueue_end = queue_idx + nb_q_per_pool - 1;\n+\tif (queue_end >= hw->mac.max_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\tif (vfinfo) {\n+\t\tfor (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {\n+\t\t\tif (vf_idx == vf)\n+\t\t\t\tcontinue;\n+\t\t\tfor (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);\n+\t\t\t\tidx++)\n+\t\t\t\ttotal_rate += vfinfo[vf_idx].tx_rate[idx];\n+\t\t}\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Store tx_rate for this vf. */\n+\tfor (idx = 0; idx < nb_q_per_pool; idx++) {\n+\t\tif (((uint64_t)0x1 << idx) & q_msk) {\n+\t\t\tif (vfinfo[vf].tx_rate[idx] != tx_rate)\n+\t\t\t\tvfinfo[vf].tx_rate[idx] = tx_rate;\n+\t\t\ttotal_rate += tx_rate;\n+\t\t}\n+\t}\n+\n+\tif (total_rate > dev->data->dev_link.link_speed) {\n+\t\t/* Reset stored TX rate of the VF if it causes exceed\n+\t\t * link speed.\n+\t\t */\n+\t\tmemset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Set ARBTXRATE of each queue/pool for vf X */\n+\tfor (; queue_idx <= queue_end; queue_idx++) {\n+\t\tif (0x1 & q_msk)\n+\t\t\ttxgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);\n+\t\tq_msk = q_msk >> 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /*\n * Configure device link speed and setup link.\n * It returns 0 on success.\n@@ -1161,6 +1238,7 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n {\n \tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n \tstruct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);\n+\tstruct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tuint32_t intr_vector = 0;\n@@ -1170,6 +1248,7 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \tuint32_t allowed_speeds = 0;\n \tint mask = 0;\n \tint status;\n+\tuint16_t vf, idx;\n \tuint32_t *link_speeds;\n \n \tPMD_INIT_FUNC_TRACE();\n@@ -1206,6 +1285,9 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \thw->mac.start_hw(hw);\n \thw->mac.get_link_status = true;\n \n+\t/* configure PF module if SRIOV enabled */\n+\ttxgbe_pf_host_configure(dev);\n+\n \ttxgbe_dev_phy_intr_setup(dev);\n \n \t/* check and configure queue intr-vector mapping */\n@@ -1249,6 +1331,16 @@ txgbe_dev_start(struct rte_eth_dev *dev)\n \t\tgoto error;\n \t}\n \n+\t/* Restore vf rate limit */\n+\tif (vfinfo != NULL) {\n+\t\tfor (vf = 0; vf < pci_dev->max_vfs; vf++)\n+\t\t\tfor (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)\n+\t\t\t\tif (vfinfo[vf].tx_rate[idx] != 0)\n+\t\t\t\t\ttxgbe_set_vf_rate_limit(dev, vf,\n+\t\t\t\t\t\tvfinfo[vf].tx_rate[idx],\n+\t\t\t\t\t\t1 << idx);\n+\t}\n+\n \terr = txgbe_dev_rxtx_start(dev);\n \tif (err < 0) {\n \t\tPMD_INIT_LOG(ERR, \"Unable to start rxtx queues\");\n@@ -1370,8 +1462,10 @@ txgbe_dev_stop(struct rte_eth_dev *dev)\n {\n \tstruct rte_eth_link link;\n \tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tstruct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint vf;\n \n \tif (hw->adapter_stopped)\n \t\treturn;\n@@ -1390,6 +1484,9 @@ txgbe_dev_stop(struct rte_eth_dev *dev)\n \t/* stop adapter */\n \ttxgbe_stop_hw(hw);\n \n+\tfor (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)\n+\t\tvfinfo[vf].clear_to_send = false;\n+\n \tif (hw->phy.media_type == txgbe_media_type_copper) {\n \t\t/* Turn off the copper */\n \t\thw->phy.set_phy_power(hw, false);\n@@ -2797,6 +2894,37 @@ txgbe_configure_msix(struct rte_eth_dev *dev)\n \t\t\t| TXGBE_ITR_WRDSA);\n }\n \n+int\n+txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,\n+\t\t\t uint16_t queue_idx, uint16_t tx_rate)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(dev);\n+\tuint32_t bcnrc_val;\n+\n+\tif (queue_idx >= hw->mac.max_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\tif (tx_rate != 0) {\n+\t\tbcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);\n+\t\tbcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);\n+\t} else {\n+\t\tbcnrc_val = 0;\n+\t}\n+\n+\t/*\n+\t * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW\n+\t * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.\n+\t */\n+\twr32(hw, TXGBE_ARBTXMMW, 0x14);\n+\n+\t/* Set ARBTXRATE of queue X */\n+\twr32(hw, TXGBE_ARBPOOLIDX, queue_idx);\n+\twr32(hw, TXGBE_ARBTXRATE, bcnrc_val);\n+\ttxgbe_flush(hw);\n+\n+\treturn 0;\n+}\n+\n static u8 *\n txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,\n \t\t\tu8 **mc_addr_ptr, u32 *vmdq)\n@@ -2861,6 +2989,7 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {\n \t.mac_addr_set = txgbe_set_default_mac_addr,\n \t.uc_hash_table_set = txgbe_uc_hash_table_set,\n \t.uc_all_hash_table_set = txgbe_uc_all_hash_table_set,\n+\t.set_queue_rate_limit = txgbe_set_queue_rate_limit,\n \t.set_mc_addr_list = txgbe_dev_set_mc_addr_list,\n \t.rxq_info_get = txgbe_rxq_info_get,\n \t.txq_info_get = txgbe_txq_info_get,\ndiff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h\nindex bc83c2576..eea8191b9 100644\n--- a/drivers/net/txgbe/txgbe_ethdev.h\n+++ b/drivers/net/txgbe/txgbe_ethdev.h\n@@ -33,6 +33,8 @@\n \n #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT\t500 /* 500us */\n \n+#define TXGBE_MAX_QUEUE_NUM_PER_VF 8\n+\n #define TXGBE_RSS_OFFLOAD_ALL ( \\\n \tETH_RSS_IPV4 | \\\n \tETH_RSS_NONFRAG_IPV4_TCP | \\\n@@ -96,6 +98,7 @@ struct txgbe_vf_info {\n \tuint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];\n \tuint16_t num_vf_mc_hashes;\n \tbool clear_to_send;\n+\tuint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];\n \tuint16_t vlan_count;\n \tuint8_t api_version;\n \tuint16_t switch_domain_id;\n@@ -103,6 +106,26 @@ struct txgbe_vf_info {\n \tuint16_t mac_count;\n };\n \n+struct txgbe_ethertype_filter {\n+\tuint16_t ethertype;\n+\tuint32_t etqf;\n+\tuint32_t etqs;\n+\t/**\n+\t * If this filter is added by configuration,\n+\t * it should not be removed.\n+\t */\n+\tbool conf;\n+};\n+\n+/*\n+ * Structure to store filters' info.\n+ */\n+struct txgbe_filter_info {\n+\tuint8_t ethertype_mask; /* Bit mask for every used ethertype filter */\n+\t/* store used ethertype filters*/\n+\tstruct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];\n+};\n+\n /*\n * Structure to store private data for each driver instance (for each port).\n */\n@@ -116,6 +139,7 @@ struct txgbe_adapter {\n \tstruct txgbe_mirror_info mr_data;\n \tstruct txgbe_vf_info *vfdata;\n \tstruct txgbe_uta_info uta_info;\n+\tstruct txgbe_filter_info filter;\n \tbool rx_bulk_alloc_allowed;\n };\n \n@@ -149,6 +173,9 @@ struct txgbe_adapter {\n #define TXGBE_DEV_UTA_INFO(dev) \\\n \t(&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)\n \n+#define TXGBE_DEV_FILTER(dev) \\\n+\t(&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)\n+\n /*\n * RX/TX function prototypes\n */\n@@ -226,6 +253,50 @@ void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);\n \n void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);\n \n+int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);\n+\n+int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n+\t\t\t uint16_t tx_rate, uint64_t q_msk);\n+int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t uint16_t tx_rate);\n+static inline int\n+txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,\n+\t\t\t uint16_t ethertype)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < TXGBE_ETF_ID_MAX; i++) {\n+\t\tif (filter_info->ethertype_filters[i].ethertype == ethertype &&\n+\t\t (filter_info->ethertype_mask & (1 << i)))\n+\t\t\treturn i;\n+\t}\n+\treturn -1;\n+}\n+\n+static inline int\n+txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,\n+\t\t\t struct txgbe_ethertype_filter *ethertype_filter)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < TXGBE_ETF_ID_MAX; i++) {\n+\t\tif (filter_info->ethertype_mask & (1 << i)) {\n+\t\t\tcontinue;\n+\t\t}\n+\t\tfilter_info->ethertype_mask |= 1 << i;\n+\t\tfilter_info->ethertype_filters[i].ethertype =\n+\t\t\t\tethertype_filter->ethertype;\n+\t\tfilter_info->ethertype_filters[i].etqf =\n+\t\t\t\tethertype_filter->etqf;\n+\t\tfilter_info->ethertype_filters[i].etqs =\n+\t\t\t\tethertype_filter->etqs;\n+\t\tfilter_info->ethertype_filters[i].conf =\n+\t\t\t\tethertype_filter->conf;\n+\t\tbreak;\n+\t}\n+\treturn (i < TXGBE_ETF_ID_MAX ? i : -1);\n+}\n+\n \n #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */\n #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */\ndiff --git a/drivers/net/txgbe/txgbe_pf.c b/drivers/net/txgbe/txgbe_pf.c\nindex 143153065..f96cced3d 100644\n--- a/drivers/net/txgbe/txgbe_pf.c\n+++ b/drivers/net/txgbe/txgbe_pf.c\n@@ -25,6 +25,7 @@\n #include \"txgbe_ethdev.h\"\n #include \"rte_pmd_txgbe.h\"\n \n+#define TXGBE_MAX_VFTA (128)\n #define TXGBE_VF_MSG_SIZE_DEFAULT 1\n #define TXGBE_VF_GET_QUEUE_MSG_SIZE 5\n \n@@ -142,6 +143,145 @@ void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)\n \t*vfinfo = NULL;\n }\n \n+static void\n+txgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);\n+\tstruct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);\n+\tuint16_t vf_num;\n+\tint i;\n+\tstruct txgbe_ethertype_filter ethertype_filter;\n+\n+\tif (!hw->mac.set_ethertype_anti_spoofing) {\n+\t\tPMD_DRV_LOG(INFO, \"ether type anti-spoofing is not supported.\\n\");\n+\t\treturn;\n+\t}\n+\n+\ti = txgbe_ethertype_filter_lookup(filter_info,\n+\t\t\t\t\t TXGBE_ETHERTYPE_FLOW_CTRL);\n+\tif (i >= 0) {\n+\t\tPMD_DRV_LOG(ERR, \"A ether type filter entity for flow control already exists!\\n\");\n+\t\treturn;\n+\t}\n+\n+\tethertype_filter.ethertype = TXGBE_ETHERTYPE_FLOW_CTRL;\n+\tethertype_filter.etqf = TXGBE_ETFLT_ENA |\n+\t\t\t\tTXGBE_ETFLT_TXAS |\n+\t\t\t\tTXGBE_ETHERTYPE_FLOW_CTRL;\n+\tethertype_filter.etqs = 0;\n+\tethertype_filter.conf = TRUE;\n+\ti = txgbe_ethertype_filter_insert(filter_info,\n+\t\t\t\t\t ðertype_filter);\n+\tif (i < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Cannot find an unused ether type filter entity for flow control.\\n\");\n+\t\treturn;\n+\t}\n+\n+\twr32(hw, TXGBE_ETFLT(i),\n+\t\t\t(TXGBE_ETFLT_ENA |\n+\t\t\tTXGBE_ETFLT_TXAS |\n+\t\t\tTXGBE_ETHERTYPE_FLOW_CTRL));\n+\n+\tvf_num = dev_num_vf(eth_dev);\n+\tfor (i = 0; i < vf_num; i++)\n+\t\thw->mac.set_ethertype_anti_spoofing(hw, true, i);\n+}\n+\n+int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev)\n+{\n+\tuint32_t vtctl, fcrth;\n+\tuint32_t vfre_slot, vfre_offset;\n+\tuint16_t vf_num;\n+\tconst uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */\n+\tconst uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);\n+\tstruct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);\n+\tuint32_t gpie;\n+\tuint32_t gcr_ext;\n+\tuint32_t vlanctrl;\n+\tint i;\n+\n+\tvf_num = dev_num_vf(eth_dev);\n+\tif (vf_num == 0)\n+\t\treturn -1;\n+\n+\t/* enable VMDq and set the default pool for PF */\n+\tvtctl = rd32(hw, TXGBE_POOLCTL);\n+\tvtctl &= ~TXGBE_POOLCTL_DEFPL_MASK;\n+\tvtctl |= TXGBE_POOLCTL_DEFPL(RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);\n+\tvtctl |= TXGBE_POOLCTL_RPLEN;\n+\twr32(hw, TXGBE_POOLCTL, vtctl);\n+\n+\tvfre_offset = vf_num & VFRE_MASK;\n+\tvfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;\n+\n+\t/* Enable pools reserved to PF only */\n+\twr32(hw, TXGBE_POOLRXENA(vfre_slot), (~0U) << vfre_offset);\n+\twr32(hw, TXGBE_POOLRXENA(vfre_slot ^ 1), vfre_slot - 1);\n+\twr32(hw, TXGBE_POOLTXENA(vfre_slot), (~0U) << vfre_offset);\n+\twr32(hw, TXGBE_POOLTXENA(vfre_slot ^ 1), vfre_slot - 1);\n+\n+\twr32(hw, TXGBE_PSRCTL, TXGBE_PSRCTL_LBENA);\n+\n+\t/* clear VMDq map to perment rar 0 */\n+\thw->mac.clear_vmdq(hw, 0, BIT_MASK32);\n+\n+\t/* clear VMDq map to scan rar 127 */\n+\twr32(hw, TXGBE_ETHADDRIDX, hw->mac.num_rar_entries);\n+\twr32(hw, TXGBE_ETHADDRASSL, 0);\n+\twr32(hw, TXGBE_ETHADDRASSH, 0);\n+\n+\t/* set VMDq map to default PF pool */\n+\thw->mac.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);\n+\n+\t/*\n+\t * SW msut set PORTCTL.VT_Mode the same as GPIE.VT_Mode\n+\t */\n+\tgpie = rd32(hw, TXGBE_GPIE);\n+\tgpie |= TXGBE_GPIE_MSIX;\n+\tgcr_ext = rd32(hw, TXGBE_PORTCTL);\n+\tgcr_ext &= ~TXGBE_PORTCTL_NUMVT_MASK;\n+\n+\tswitch (RTE_ETH_DEV_SRIOV(eth_dev).active) {\n+\tcase ETH_64_POOLS:\n+\t\tgcr_ext |= TXGBE_PORTCTL_NUMVT_64;\n+\t\tbreak;\n+\tcase ETH_32_POOLS:\n+\t\tgcr_ext |= TXGBE_PORTCTL_NUMVT_32;\n+\t\tbreak;\n+\tcase ETH_16_POOLS:\n+\t\tgcr_ext |= TXGBE_PORTCTL_NUMVT_16;\n+\t\tbreak;\n+\t}\n+\n+\twr32(hw, TXGBE_PORTCTL, gcr_ext);\n+\twr32(hw, TXGBE_GPIE, gpie);\n+\n+\t/*\n+\t * enable vlan filtering and allow all vlan tags through\n+\t */\n+\tvlanctrl = rd32(hw, TXGBE_VLANCTL);\n+\tvlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */\n+\twr32(hw, TXGBE_VLANCTL, vlanctrl);\n+\n+\t/* enable all vlan filters */\n+\tfor (i = 0; i < TXGBE_MAX_VFTA; i++)\n+\t\twr32(hw, TXGBE_VLANTBL(i), 0xFFFFFFFF);\n+\n+\t/* Enable MAC Anti-Spoofing */\n+\thw->mac.set_mac_anti_spoofing(hw, FALSE, vf_num);\n+\n+\t/* set flow control threshold to max to avoid tx switch hang */\n+\tfor (i = 0; i < TXGBE_DCB_TC_MAX; i++) {\n+\t\twr32(hw, TXGBE_FCWTRLO(i), 0);\n+\t\tfcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 32;\n+\t\twr32(hw, TXGBE_FCWTRHI(i), fcrth);\n+\t}\n+\n+\ttxgbe_add_tx_flow_control_drop_filter(eth_dev);\n+\n+\treturn 0;\n+}\n+\n static void\n txgbe_set_rx_mode(struct rte_eth_dev *eth_dev)\n {\n", "prefixes": [ "v2", "40/56" ] }