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{
    "id": 79634,
    "url": "https://patches.dpdk.org/api/patches/79634/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-18-jiawenwu@trustnetic.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20201005120910.189343-18-jiawenwu@trustnetic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20201005120910.189343-18-jiawenwu@trustnetic.com",
    "date": "2020-10-05T12:08:31",
    "name": "[v2,17/56] net/txgbe: add autoc read and write",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "83e6f2ee4823241abc61df4473c24abbb0e47c64",
    "submitter": {
        "id": 1932,
        "url": "https://patches.dpdk.org/api/people/1932/?format=api",
        "name": "Jiawen Wu",
        "email": "jiawenwu@trustnetic.com"
    },
    "delegate": {
        "id": 319,
        "url": "https://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20201005120910.189343-18-jiawenwu@trustnetic.com/mbox/",
    "series": [
        {
            "id": 12690,
            "url": "https://patches.dpdk.org/api/series/12690/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12690",
            "date": "2020-10-05T12:08:14",
            "name": "net: txgbe PMD",
            "version": 2,
            "mbox": "https://patches.dpdk.org/series/12690/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/79634/comments/",
    "check": "warning",
    "checks": "https://patches.dpdk.org/api/patches/79634/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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        ],
        "X-QQ-mid": "bizesmtp9t1601899740tsmrumsyo",
        "X-QQ-SSF": "01400000002000C0C000B00A0000000",
        "X-QQ-FEAT": "lm51M56XDGxwaeG2HWG13JYUZF2m2UlPMq5sJwztljm1BbL6Up5KxDOxTQxuQ\n p9ywag4RAnSAWEzaFmg4FYmBrBhb9khsG6n0SwHZQx/3ifJVlqMgGGdva8VJdk6ATCN/rUw\n lhtYqaYQDiF3hHQ09oKOWUcWsK/KVILiJTYmpBUf/EIyjZBCDQAcxJnWM+uwhEHWfiDzujn\n H9N10+yBHMRj/eK/nrcRepfcZqqejAtgCb1UxoVja915Crj4Yq7YlRRPsbqE1oF79MHa5Az\n T+Y3HxQT24uRXFcMBZr4xI6OxIPkVCvwTcUoSK9/xA6y+VZ+QCkVA0XT25CEnd+6vaapSAL\n KA1JW4n",
        "X-QQ-GoodBg": "2",
        "From": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "To": "dev@dpdk.org",
        "Cc": "jiawenwu <jiawenwu@trustnetic.com>",
        "Date": "Mon,  5 Oct 2020 20:08:31 +0800",
        "Message-Id": "<20201005120910.189343-18-jiawenwu@trustnetic.com>",
        "X-Mailer": "git-send-email 2.18.4",
        "In-Reply-To": "<20201005120910.189343-1-jiawenwu@trustnetic.com>",
        "References": "<20201005120910.189343-1-jiawenwu@trustnetic.com>",
        "X-QQ-SENDSIZE": "520",
        "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign7",
        "X-QQ-Bgrelay": "1",
        "Subject": "[dpdk-dev] [PATCH v2 17/56] net/txgbe: add autoc read and write",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: jiawenwu <jiawenwu@trustnetic.com>\n\nAdd autoc read and write for kr/kx/kx4/sfi link.\n\nSigned-off-by: jiawenwu <jiawenwu@trustnetic.com>\n---\n drivers/net/txgbe/base/txgbe_hw.c   |   2 +\n drivers/net/txgbe/base/txgbe_phy.c  | 848 ++++++++++++++++++++++++++++\n drivers/net/txgbe/base/txgbe_phy.h  |   2 +\n drivers/net/txgbe/base/txgbe_type.h |  21 +\n 4 files changed, 873 insertions(+)",
    "diff": "diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c\nindex 9daf6651a..ec1545d6a 100644\n--- a/drivers/net/txgbe/base/txgbe_hw.c\n+++ b/drivers/net/txgbe/base/txgbe_hw.c\n@@ -620,6 +620,8 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)\n \t/* MAC */\n \tmac->init_hw = txgbe_init_hw;\n \tmac->reset_hw = txgbe_reset_hw;\n+\tmac->autoc_read = txgbe_autoc_read;\n+\tmac->autoc_write = txgbe_autoc_write;\n \n \t/* Link */\n \tmac->get_link_capabilities = txgbe_get_link_capabilities_raptor;\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c\nindex 59d28506e..7981fb2f8 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.c\n+++ b/drivers/net/txgbe/base/txgbe_phy.c\n@@ -1373,3 +1373,851 @@ STATIC void txgbe_i2c_stop(struct txgbe_hw *hw)\n \twr32(hw, TXGBE_I2CENA, 0);\n }\n \n+static s32\n+txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)\n+{\n+\tu32 value;\n+\n+\twr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);\n+\twr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);\n+\twr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);\n+\tvalue = rd32_epcs(hw, SR_MII_MMD_CTL);\n+\tvalue = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);\n+\twr32_epcs(hw, SR_MII_MMD_CTL, value);\n+\treturn 0;\n+}\n+\n+static s32\n+txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)\n+{\n+\tu32 i;\n+\ts32 err = 0;\n+\n+\t/* 1. Wait xpcs power-up good */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)\n+\t\t\tbreak;\n+\t\tmsleep(10);\n+\t}\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_XPCS_POWER_UP_FAILED;\n+\t\tgoto out;\n+\t}\n+\n+\tif (!autoneg) {\n+\t\t/* 2. Disable xpcs AN-73 */\n+\t\twr32_epcs(hw, SR_AN_CTRL, 0x0);\n+\t\t/* Disable PHY MPLLA for eth mode change(after ECO) */\n+\t\twr32_ephy(hw, 0x4, 0x243A);\n+\t\ttxgbe_flush(hw);\n+\t\tmsleep(1);\n+\t\t/* Set the eth change_mode bit first in mis_rst register\n+\t\t * for corresponding LAN port */\n+\t\twr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));\n+\n+\t\t/* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register\n+\t\t * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,\n+\t\t\tTXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);\n+\n+\t\t/* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register\n+\t\t * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n+\n+\t\t/* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register\n+\t\t * Bit[15:8](VGA1/2_GAIN_0) = 8'h77\n+\t\t * Bit[7:5](CTLE_POLE_0) = 3'h2\n+\t\t * Bit[4:0](CTLE_BOOST_0) = 4'hA\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);\n+\n+\t\t/* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register\n+\t\t * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);\n+\n+\t\t/* 7. Initialize the mode by setting VR XS or PCS MMD Digital\n+\t\t * Control1 Register Bit[15](VR_RST) */\n+\t\twr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);\n+\n+\t\t/* Wait phy initialization done */\n+\t\tfor (i = 0; i < 100; i++) {\n+\t\t\tif ((rd32_epcs(hw,\n+\t\t\t\tVR_XS_OR_PCS_MMD_DIGI_CTL1) &\n+\t\t\t\tVR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)\n+\t\t\t\tbreak;\n+\t\t\tmsleep(100);\n+\t\t}\n+\t\tif (i == 100) {\n+\t\t\terr = TXGBE_ERR_PHY_INIT_NOT_DONE;\n+\t\t\tgoto out;\n+\t\t}\n+\t} else {\n+\t\t wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);\n+\t}\n+out:\n+\treturn err;\n+}\n+\n+static s32\n+txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)\n+{\n+\tu32 i;\n+\ts32 err = 0;\n+\tu32 value;\n+\n+\t/* Check link status, if already set, skip setting it again */\n+\tif (hw->link_status == TXGBE_LINK_STATUS_KX4) {\n+\t\tgoto out;\n+\t}\n+\n+\t/* 1. Wait xpcs power-up good */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)\n+\t\t\tbreak;\n+\t\tmsleep(10);\n+\t}\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_XPCS_POWER_UP_FAILED;\n+\t\tgoto out;\n+\t}\n+\n+\twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TE,\n+\t\t\t~TXGBE_MACTXCFG_TE);\n+\n+\t/* 2. Disable xpcs AN-73 */\n+\tif (!autoneg)\n+\t\twr32_epcs(hw, SR_AN_CTRL, 0x0);\n+\telse\n+\t\twr32_epcs(hw, SR_AN_CTRL, 0x3000);\n+\n+\t/* Disable PHY MPLLA for eth mode change(after ECO) */\n+\twr32_ephy(hw, 0x4, 0x250A);\n+\ttxgbe_flush(hw);\n+\tmsleep(1);\n+\n+\t/* Set the eth change_mode bit first in mis_rst register\n+\t * for corresponding LAN port */\n+\twr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));\n+\n+\t/* Set SR PCS Control2 Register Bits[1:0] = 2'b01\n+\t * PCS_TYPE_SEL: non KR\n+\t */\n+\twr32_epcs(hw, SR_XS_PCS_CTRL2,\n+\t\t\tSR_PCS_CTRL2_TYPE_SEL_X);\n+\n+\t/* Set SR PMA MMD Control1 Register Bit[13] = 1'b1\n+\t * SS13: 10G speed\n+\t */\n+\twr32_epcs(hw, SR_PMA_CTRL1,\n+\t\t\tSR_PMA_CTRL1_SS13_KX4);\n+\n+\tvalue = (0xf5f0 & ~0x7F0) |  (0x5 << 8) | (0x7 << 5) | 0x10;\n+\twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n+\n+\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n+\n+\tvalue = (0x1804 & ~0x3F3F);\n+\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\tvalue = (0x50 & ~0x7F) | 40 | (1 << 6);\n+\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tif (i == 0)\n+\t\t\tvalue = (0x45 & ~0xFFFF) | (0x7 << 12) | (0x7 << 8) | 0x6;\n+\t\telse\n+\t\t\tvalue = (0xff06 & ~0xFFFF) | (0x7 << 12) | (0x7 << 8) | 0x6;\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);\n+\t}\n+\n+\tvalue = 0x0 & ~0x7777;\n+\twr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);\n+\n+\twr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);\n+\n+\tvalue = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;\n+\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY MPLLA\n+\t * Control 0 Register Bit[7:0] = 8'd40  //MPLLA_MULTIPLIER\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,\n+\t\t\tTXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);\n+\n+\t/* Set VR XS, PMA or MII Synopsys Enterprise Gen5 12G PHY MPLLA\n+\t * Control 3 Register Bit[10:0] = 11'd86  //MPLLA_BANDWIDTH\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,\n+\t\t\tTXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Load 0 Register  Bit[12:0] = 13'd1360  //VCO_LD_VAL_0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,\n+\t\t\tTXGBE_PHY_VCO_CAL_LD0_OTHER);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Load 1 Register  Bit[12:0] = 13'd1360  //VCO_LD_VAL_1\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,\n+\t\t\tTXGBE_PHY_VCO_CAL_LD0_OTHER);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Load 2 Register  Bit[12:0] = 13'd1360  //VCO_LD_VAL_2\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,\n+\t\t\tTXGBE_PHY_VCO_CAL_LD0_OTHER);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Load 3 Register  Bit[12:0] = 13'd1360  //VCO_LD_VAL_3\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,\n+\t\t\tTXGBE_PHY_VCO_CAL_LD0_OTHER);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Reference 0 Register Bit[5:0] = 6'd34  //VCO_REF_LD_0/1\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Reference 1 Register Bit[5:0] = 6'd34  //VCO_REF_LD_2/3\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY AFE-DFE\n+\t * Enable Register Bit[7:0] = 8'd0  //AFE_EN_0/3_1, DFE_EN_0/3_1\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);\n+\n+\t/* Set  VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx\n+\t * Equalization Control 4 Register Bit[3:0] = 4'd0  //CONT_ADAPT_0/3_1\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Tx Rate\n+\t * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],\n+\t * all rates to 3'b010  //TX0/1/2/3_RATE\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx Rate\n+\t * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],\n+\t * all rates to 2'b10  //RX0/1/2/3_RATE\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Tx General\n+\t * Control 2 Register Bit[15:8] = 2'b01  //TX0/1/2/3_WIDTH: 10bits\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx General\n+\t * Control 2 Register Bit[15:8] = 2'b01  //RX0/1/2/3_WIDTH: 10bits\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY MPLLA Control\n+\t * 2 Register Bit[10:8] = 3'b010\n+\t * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,\n+\t\t\tTXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);\n+\n+\twr32_epcs(hw, 0x1f0000, 0x0);\n+\twr32_epcs(hw, 0x1f8001, 0x0);\n+\twr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);\n+\n+\t/* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1\n+\t * Register Bit[15](VR_RST) */\n+\twr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);\n+\n+\t/* Wait phy initialization done */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)\n+\t\t\tbreak;\n+\t\tmsleep(100);\n+\t}\n+\n+\t/* If success, set link status */\n+\thw->link_status = TXGBE_LINK_STATUS_KX4;\n+\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_PHY_INIT_NOT_DONE;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn err;\n+}\n+\n+static s32\n+txgbe_set_link_to_kx(struct txgbe_hw *hw,\n+\t\t\t       u32 speed,\n+\t\t\t       bool autoneg)\n+{\n+\tu32 i;\n+\ts32 err = 0;\n+\tu32 wdata = 0;\n+\tu32 value;\n+\n+\t/* Check link status, if already set, skip setting it again */\n+\tif (hw->link_status == TXGBE_LINK_STATUS_KX) {\n+\t\tgoto out;\n+\t}\n+\n+\t/* 1. Wait xpcs power-up good */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)\n+\t\t\tbreak;\n+\t\tmsleep(10);\n+\t}\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_XPCS_POWER_UP_FAILED;\n+\t\tgoto out;\n+\t}\n+\n+\twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TE,\n+\t\t\t\t~TXGBE_MACTXCFG_TE);\n+\n+\t/* 2. Disable xpcs AN-73 */\n+\tif (!autoneg)\n+\t\twr32_epcs(hw, SR_AN_CTRL, 0x0);\n+\telse\n+\t\twr32_epcs(hw, SR_AN_CTRL, 0x3000);\n+\n+\t/* Disable PHY MPLLA for eth mode change(after ECO) */\n+\twr32_ephy(hw, 0x4, 0x240A);\n+\ttxgbe_flush(hw);\n+\tmsleep(1);\n+\n+\t/* Set the eth change_mode bit first in mis_rst register\n+\t * for corresponding LAN port */\n+\twr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));\n+\n+\t/* Set SR PCS Control2 Register Bits[1:0] = 2'b01\n+\t * PCS_TYPE_SEL: non KR\n+\t */\n+\twr32_epcs(hw, SR_XS_PCS_CTRL2,\n+\t\t\tSR_PCS_CTRL2_TYPE_SEL_X);\n+\n+\t/* Set SR PMA MMD Control1 Register Bit[13] = 1'b0\n+\t * SS13: 1G speed\n+\t */\n+\twr32_epcs(hw, SR_PMA_CTRL1,\n+\t\t\tSR_PMA_CTRL1_SS13_KX);\n+\n+\t/* Set SR MII MMD Control Register to corresponding speed: {Bit[6],\n+\t * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]\n+\t */\n+\tif (speed == TXGBE_LINK_SPEED_100M_FULL)\n+\t\twdata = 0x2100;\n+\telse if (speed == TXGBE_LINK_SPEED_1GB_FULL)\n+\t\twdata = 0x0140;\n+\telse if (speed == TXGBE_LINK_SPEED_10M_FULL)\n+\t\twdata = 0x0100;\n+\twr32_epcs(hw, SR_MII_MMD_CTL,\n+\t\t\twdata);\n+\n+\tvalue = (0xf5f0 & ~0x710) |  (0x5 << 8);\n+\twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n+\n+\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);\n+\n+\tvalue = (0x1804 & ~0x3F3F) | (24 << 8) | 4;\n+\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\n+\tvalue = (0x50 & ~0x7F) | 16 | (1 << 6);\n+\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tif (i) {\n+\t\t\tvalue = 0xff06;\n+\t\t} else {\n+\t\t\tvalue = (0x45 & ~0xFFFF) | (0x7 << 12) |\n+\t\t\t\t(0x7 << 8) | 0x6;\n+\t\t}\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);\n+\t}\n+\n+\tvalue = 0x0 & ~0x7;\n+\twr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);\n+\n+\twr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);\n+\n+\tvalue = (0x6db & ~0x7) | 0x4;\n+\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY MPLLA Control\n+\t * 0 Register Bit[7:0] = 8'd32  //MPLLA_MULTIPLIER\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,\n+\t\t\tTXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);\n+\n+\t/* Set VR XS, PMA or MII Synopsys Enterprise Gen5 12G PHY MPLLA Control\n+\t * 3 Register Bit[10:0] = 11'd70  //MPLLA_BANDWIDTH\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,\n+\t\t\tTXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Load 0 Register  Bit[12:0] = 13'd1344  //VCO_LD_VAL_0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,\n+\t\t\tTXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);\n+\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY VCO\n+\t * Calibration Reference 0 Register Bit[5:0] = 6'd42  //VCO_REF_LD_0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,\n+\t\t\tTXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);\n+\n+\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY AFE-DFE\n+\t * Enable Register Bit[4], Bit[0] = 1'b0  //AFE_EN_0, DFE_EN_0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,\n+\t\t\t0x0);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx\n+\t * Equalization Control 4 Register Bit[0] = 1'b0  //CONT_ADAPT_0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,\n+\t\t\t0x0010);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Tx Rate\n+\t * Control Register Bit[2:0] = 3'b011  //TX0_RATE\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,\n+\t\t\tTXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx Rate\n+\t * Control Register Bit[2:0] = 3'b011 //RX0_RATE\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,\n+\t\t\tTXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);\n+\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Tx General\n+\t * Control 2 Register Bit[9:8] = 2'b01  //TX0_WIDTH: 10bits\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,\n+\t\t\tTXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY Rx General\n+\t * Control 2 Register Bit[9:8] = 2'b01  //RX0_WIDTH: 10bits\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,\n+\t\t\tTXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);\n+\t/* Set VR XS, PMA, or MII Synopsys Enterprise Gen5 12G PHY MPLLA Control\n+\t * 2 Register Bit[10:8] = 3'b010   //MPLLA_DIV16P5_CLK_EN=0,\n+\t * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0\n+\t */\n+\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,\n+\t\t\tTXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);\n+\n+\t/* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL\n+\t * Set to 8bit MII (required in 10M/100M SGMII)\n+\t */\n+\twr32_epcs(hw, SR_MII_MMD_AN_CTL,\n+\t\t\t0x0100);\n+\n+\t/* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1\n+\t * Register Bit[15](VR_RST)\n+\t */\n+\twr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);\n+\n+\t/* Wait phy initialization done */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)\n+\t\t\tbreak;\n+\t\tmsleep(100);\n+\t}\n+\n+\t/* If success, set link status */\n+\thw->link_status = TXGBE_LINK_STATUS_KX;\n+\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_PHY_INIT_NOT_DONE;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn err;\n+}\n+\n+static s32\n+txgbe_set_link_to_sfi(struct txgbe_hw *hw,\n+\t\t\t       u32 speed)\n+{\n+\tu32 i;\n+\ts32 err = 0;\n+\tu32 value = 0;\n+\n+\t/* Set the module link speed */\n+\thw->mac.set_rate_select_speed(hw, speed);\n+\t/* 1. Wait xpcs power-up good */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)\n+\t\t\tbreak;\n+\t\tmsleep(10);\n+\t}\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_XPCS_POWER_UP_FAILED;\n+\t\tgoto out;\n+\t}\n+\n+\twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TE,\n+\t\t\t~TXGBE_MACTXCFG_TE);\n+\n+\t/* 2. Disable xpcs AN-73 */\n+\twr32_epcs(hw, SR_AN_CTRL, 0x0);\n+\n+\t/* Disable PHY MPLLA for eth mode change(after ECO) */\n+\twr32_ephy(hw, 0x4, 0x243A);\n+\ttxgbe_flush(hw);\n+\tmsleep(1);\n+\t/* Set the eth change_mode bit first in mis_rst register\n+\t * for corresponding LAN port */\n+\twr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));\n+\n+\tif (speed == TXGBE_LINK_SPEED_10GB_FULL) {\n+\t\t/* Set SR PCS Control2 Register Bits[1:0] = 2'b00\n+\t\t * PCS_TYPE_SEL: KR\n+\t\t */\n+\t\twr32_epcs(hw, SR_XS_PCS_CTRL2, 0);\n+\t\tvalue = rd32_epcs(hw, SR_PMA_CTRL1);\n+\t\tvalue = value | 0x2000;\n+\t\twr32_epcs(hw, SR_PMA_CTRL1, value);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33\n+\t\t * MPLLA_MULTIPLIER\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);\n+\t\t/* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register\n+\t\t * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);\n+\t\tvalue = (value & ~0x700) | 0x500;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n+\t\t/* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register\n+\t\t * Bit[12:8](RX_VREF_CTRL) = 5'hF\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register\n+\t\t * Bit[12:0] = 13'd1353  //VCO_LD_VAL_0\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register\n+\t\t * Bit[5:0] = 6'd41  //VCO_REF_LD_0\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register\n+\t\t * Bit[2:0] = 3'b000  //TX0_RATE\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register\n+\t\t * Bit[2:0] = 3'b000  //RX0_RATE\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11\n+\t\t * TX0_WIDTH: 20bits\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11\n+\t\t * RX0_WIDTH: 20bits\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);\n+\t\t/* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register\n+\t\t * Bit[10:8] = 3'b110\n+\t\t * MPLLA_DIV16P5_CLK_EN=1\n+\t\t * MPLLA_DIV10_CLK_EN=1\n+\t\t * MPLLA_DIV8_CLK_EN=0\n+\t\t */\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);\n+\t\t/* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register\n+\t\t * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4\n+\t\t */\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n+\t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\t\t/* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register\n+\t\t * Bit[6](TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36\n+\t\t */\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\tvalue = (value & ~0x7F) | 16 | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t\tif (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||\n+\t\t\thw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {\n+\t\t\t/* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register\n+\t\t\t * Bit[15:8](VGA1/2_GAIN_0) = 8'h77\n+\t\t\t * Bit[7:5](CTLE_POLE_0) = 3'h2\n+\t\t\t * Bit[4:0](CTLE_BOOST_0) = 4'hF\n+\t\t\t */\n+\t\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);\n+\n+\t\t} else {\n+\t\t\t/* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register\n+\t\t\t * Bit[15:8](VGA1/2_GAIN_0) = 8'h00\n+\t\t\t * Bit[7:5](CTLE_POLE_0) = 3'h2\n+\t\t\t * Bit[4:0](CTLE_BOOST_0) = 4'hA\n+\t\t\t */\n+\t\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);\n+\t\t\tvalue = (value & ~0xFFFF) | (2 << 5) | 0x05;\n+\t\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);\n+\t\t}\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);\n+\t\tvalue = (value & ~0x7) | 0x0;\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);\n+\n+\t\tif (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||\n+\t\t\thw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {\n+\t\t\t/* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register\n+\t\t\t * Bit[7:0](DFE_TAP1_0) = 8'd20 */\n+\t\t\twr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);\n+\t\t\tvalue = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);\n+\t\t\tvalue = (value & ~0x11) | 0x11;\n+\t\t\twr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);\n+\t\t} else {\n+\t\t\t/* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register\n+\t\t\t * Bit[7:0](DFE_TAP1_0) = 8'd20 */\n+\t\t\twr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);\n+\t\t\t/* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register\n+\t\t\t * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 */\n+\t\t\tvalue = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);\n+\t\t\tvalue = (value & ~0x11) | 0x0;\n+\t\t\twr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);\n+\t\t}\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);\n+\t\tvalue = value & ~0x1;\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);\n+\t} else {\n+\t\t/* Set SR PCS Control2 Register Bits[1:0] = 2'b00\n+\t\t * PCS_TYPE_SEL: KR\n+\t\t */\n+\t\twr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);\n+\t\t/* Set SR PMA MMD Control1 Register Bit[13] = 1'b0\n+\t\t * SS13: 1G speed\n+\t\t */\n+\t\twr32_epcs(hw, SR_PMA_CTRL1, 0x0000);\n+\t\t/* Set SR MII MMD Control Register to corresponding speed */\n+\t\twr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);\n+\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);\n+\t\tvalue = (value & ~0x710) | 0x500;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);\n+\t\t/* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register\n+\t\t * Bit[12:8](RX_VREF_CTRL) = 5'hF */\n+\t\twr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);\n+\t\t/* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register\n+\t\t * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4 */\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);\n+\t\tvalue = (value & ~0x3F3F) | (24 << 8) | 4;\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);\n+\t\t/* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register Bit[6]\n+\t\t * (TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36 */\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);\n+\t\tvalue = (value & ~0x7F) | 16 | (1 << 6);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);\n+\t\tif (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||\n+\t\t\thw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {\n+\t\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);\n+\t\t} else {\n+\t\t\t/* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register\n+\t\t\t * Bit[15:8](VGA1/2_GAIN_0) = 8'h00\n+\t\t\t * Bit[7:5](CTLE_POLE_0) = 3'h2\n+\t\t\t * Bit[4:0](CTLE_BOOST_0) = 4'hA\n+\t\t\t */\n+\t\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);\n+\t\t\tvalue = (value & ~0xFFFF) | 0x7706;\n+\t\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);\n+\t\t}\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);\n+\t\tvalue = (value & ~0x7) | 0x0;\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);\n+\t\t/* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register\n+\t\t * Bit[7:0](DFE_TAP1_0) = 8'd00 */\n+\t\twr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);\n+\t\t/* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register\n+\t\t * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0 */\n+\t\tvalue = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);\n+\t\tvalue = (value & ~0x7) | 0x4;\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);\n+\t\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);\n+\t\twr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);\n+\t\twr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);\n+\t\twr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);\n+\t\twr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);\n+\t\twr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);\n+\t\twr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);\n+\t}\n+\t/* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1\n+\t * Register Bit[15](VR_RST) */\n+\twr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);\n+\n+\t/* Wait phy initialization done */\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &\n+\t\t\tVR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)\n+\t\t\tbreak;\n+\t\tmsleep(100);\n+\t}\n+\tif (i == 100) {\n+\t\terr = TXGBE_ERR_PHY_INIT_NOT_DONE;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\treturn err;\n+}\n+\n+/**\n+ *  txgbe_autoc_read - Hides MAC differences needed for AUTOC read\n+ *  @hw: pointer to hardware structure\n+ */\n+u64 txgbe_autoc_read(struct txgbe_hw *hw)\n+{\n+\tu64 autoc = 0;\n+\tu32 sr_pcs_ctl;\n+\tu32 sr_pma_ctl1;\n+\tu32 sr_an_ctl;\n+\tu32 sr_an_adv_reg2;\n+\n+\tif (hw->phy.multispeed_fiber) {\n+\t\tautoc |= TXGBE_AUTOC_LMS_10Gs;\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||\n+\t\t   hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {\n+\t\tautoc |= TXGBE_AUTOC_LMS_10Gs |\n+\t\t\t TXGBE_AUTOC_10Gs_SFI;\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {\n+\t\tautoc = 0; /*TBD*/\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI) {\n+\t\tautoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN |\n+\t\t\t TXGBE_AUTOC_10G_XAUI;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {\n+\t\tautoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |\n+\t\t\t\tTXGBE_PHYSICAL_LAYER_100BASE_TX;\n+\t}\n+\n+\tif (hw->device_id != TXGBE_DEV_ID_RAPTOR_SGMII) {\n+\t\treturn autoc;\n+\t}\n+\n+\tsr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);\n+\tsr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);\n+\tsr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);\n+\tsr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);\n+\n+\tif ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&\n+\t    (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&\n+\t    (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {\n+\t\t/* 1G or KX - no backplane auto-negotiation */\n+\t\tautoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |\n+\t\t\t TXGBE_AUTOC_1G_KX;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\t} else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==\n+\t\tSR_PCS_CTRL2_TYPE_SEL_X &&\n+\t\t(sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&\n+\t\t(sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {\n+\t\tautoc |= TXGBE_AUTOC_LMS_10Gs |\n+\t\t\t TXGBE_AUTOC_10G_KX4;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n+\t} else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==\n+\t\tSR_PCS_CTRL2_TYPE_SEL_R &&\n+\t\t(sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {\n+\t\t/* 10 GbE serial link (KR -no backplane auto-negotiation) */\n+\t\tautoc |= TXGBE_AUTOC_LMS_10Gs |\n+\t\t\t TXGBE_AUTOC_10Gs_KR;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;\n+\t} else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {\n+\t\t/* KX/KX4/KR backplane auto-negotiation enable */\n+\t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR) {\n+\t\t\tautoc |= TXGBE_AUTOC_10G_KR;\n+\t\t}\n+\t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4) {\n+\t\t\tautoc |= TXGBE_AUTOC_10G_KX4;\n+\t\t}\n+\t\tif (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX) {\n+\t\t\tautoc |= TXGBE_AUTOC_1G_KX;\n+\t\t}\n+\t\tautoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;\n+\t\thw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |\n+\t\t\t\tTXGBE_PHYSICAL_LAYER_10GBASE_KX4 |\n+\t\t\t\tTXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\t}\n+\n+\treturn autoc;\n+}\n+\n+/**\n+ * txgbe_autoc_write - Hides MAC differences needed for AUTOC write\n+ * @hw: pointer to hardware structure\n+ * @autoc: value to write to AUTOC\n+ */\n+void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)\n+{\n+\tbool autoneg;\n+\tu32 speed;\n+\tu32 mactxcfg = 0;\n+\n+\tspeed = TXGBE_AUTOC_SPEED(autoc);\n+\tautoc &= ~TXGBE_AUTOC_SPEED_MASK;\n+\tautoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);\n+\tautoc &= ~TXGBE_AUTOC_AUTONEG;\n+\n+\tif (hw->device_id == TXGBE_DEV_ID_RAPTOR_KR_KX_KX4) {\n+\t\tif (!autoneg) {\n+\t\t\tswitch (hw->phy.link_mode) {\n+\t\t\tcase TXGBE_PHYSICAL_LAYER_10GBASE_KR:\n+\t\t\t\ttxgbe_set_link_to_kr(hw, autoneg);\n+\t\t\t\tbreak;\n+\t\t\tcase TXGBE_PHYSICAL_LAYER_10GBASE_KX4:\n+\t\t\t\ttxgbe_set_link_to_kx4(hw, autoneg);\n+\t\t\t\tbreak;\n+\t\t\tcase TXGBE_PHYSICAL_LAYER_1000BASE_KX:\n+\t\t\t\ttxgbe_set_link_to_kx(hw, speed, autoneg);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI ||\n+\t\t   hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {\n+\t\tif (speed == TXGBE_LINK_SPEED_10GB_FULL) {\n+\t\t\ttxgbe_set_link_to_kx4(hw, autoneg);\n+\t\t} else {\n+\t\t\ttxgbe_set_link_to_kx(hw, speed, 0);\n+\t\t\ttxgbe_set_sgmii_an37_ability(hw);\n+\t\t}\n+\t} else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||\n+\t\t   hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {\n+\t\ttxgbe_set_link_to_sfi(hw, speed);\n+\t}\n+\n+\tif (speed == TXGBE_LINK_SPEED_10GB_FULL) {\n+\t\tmactxcfg = TXGBE_MACTXCFG_SPEED_10G;\n+\t} else if (speed == TXGBE_LINK_SPEED_1GB_FULL) {\n+\t\tmactxcfg = TXGBE_MACTXCFG_SPEED_1G;\n+\t}\n+\t/* enable mac transmitter */\n+\twr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_SPEED_MASK, mactxcfg);\n+}\n+\ndiff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h\nindex 56959b837..fbef67e78 100644\n--- a/drivers/net/txgbe/base/txgbe_phy.h\n+++ b/drivers/net/txgbe/base/txgbe_phy.h\n@@ -366,5 +366,7 @@ s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,\n \t\t\t\t  u8 *eeprom_data);\n s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,\n \t\t\t\t   u8 eeprom_data);\n+u64 txgbe_autoc_read(struct txgbe_hw *hw);\n+void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);\n \n #endif /* _TXGBE_PHY_H_ */\ndiff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h\nindex 39f8b3565..8a2760784 100644\n--- a/drivers/net/txgbe/base/txgbe_type.h\n+++ b/drivers/net/txgbe/base/txgbe_type.h\n@@ -14,6 +14,26 @@\n #include \"txgbe_osdep.h\"\n #include \"txgbe_devids.h\"\n \n+/* Physical layer type */\n+#define TXGBE_PHYSICAL_LAYER_UNKNOWN\t\t0\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_T\t\t0x00001\n+#define TXGBE_PHYSICAL_LAYER_1000BASE_T\t\t0x00002\n+#define TXGBE_PHYSICAL_LAYER_100BASE_TX\t\t0x00004\n+#define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU\t0x00008\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_LR\t\t0x00010\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_LRM\t0x00020\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_SR\t\t0x00040\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_KX4\t0x00080\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_CX4\t0x00100\n+#define TXGBE_PHYSICAL_LAYER_1000BASE_KX\t0x00200\n+#define TXGBE_PHYSICAL_LAYER_1000BASE_BX\t0x00400\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_KR\t\t0x00800\n+#define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI\t0x01000\n+#define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA\t0x02000\n+#define TXGBE_PHYSICAL_LAYER_1000BASE_SX\t0x04000\n+#define TXGBE_PHYSICAL_LAYER_10BASE_T\t\t0x08000\n+#define TXGBE_PHYSICAL_LAYER_2500BASE_KX\t0x10000\n+\n enum txgbe_eeprom_type {\n \ttxgbe_eeprom_unknown = 0,\n \ttxgbe_eeprom_spi,\n@@ -384,6 +404,7 @@ struct txgbe_phy_info {\n \tbool multispeed_fiber;\n \tbool qsfp_shared_i2c_bus;\n \tu32 nw_mng_if_sel;\n+\tu32 link_mode;\n };\n \n struct txgbe_mbx_info {\n",
    "prefixes": [
        "v2",
        "17/56"
    ]
}