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GET /api/patches/79209/?format=api
{ "id": 79209, "url": "https://patches.dpdk.org/api/patches/79209/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com", "date": "2020-09-29T15:36:00", "name": "[v3,1/2] net: add run-time architecture specific CRC selection", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "c78675fc6fe5e6cc3a40f21fcea590dfff1c4c72", "submitter": { "id": 1605, "url": "https://patches.dpdk.org/api/people/1605/?format=api", "name": "Mairtin o Loingsigh", "email": "mairtin.oloingsigh@intel.com" }, "delegate": { "id": 24651, "url": "https://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com/mbox/", "series": [ { "id": 12596, "url": "https://patches.dpdk.org/api/series/12596/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12596", "date": "2020-09-29T15:36:01", "name": "net: add CRC run-time checks and AVX512/VPCLMULQDQ based CRC", "version": 3, "mbox": "https://patches.dpdk.org/series/12596/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/79209/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/79209/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 695E9A04BC;\n\tTue, 29 Sep 2020 17:36:43 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 21E2D1D989;\n\tTue, 29 Sep 2020 17:36:18 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 5DA211D6EE\n for <dev@dpdk.org>; Tue, 29 Sep 2020 17:36:12 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Sep 2020 08:36:09 -0700", "from irvmail001.ir.intel.com ([163.33.26.43])\n by orsmga008.jf.intel.com with ESMTP; 29 Sep 2020 08:36:07 -0700", "from sivswdev08.ir.intel.com (sivswdev08.ir.intel.com\n [10.237.217.47])\n by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n 08TFa6dG010458; Tue, 29 Sep 2020 16:36:06 +0100", "from sivswdev08.ir.intel.com (localhost [127.0.0.1])\n by sivswdev08.ir.intel.com with ESMTP id 08TFa6DG011861;\n Tue, 29 Sep 2020 16:36:06 +0100", "(from moloings@localhost)\n by sivswdev08.ir.intel.com with LOCAL id 08TFa60I011857;\n Tue, 29 Sep 2020 16:36:06 +0100" ], "IronPort-SDR": [ "\n iw0iXmGCt9EjT/7HM0zYM893nAtLleSnqZsf+myhOqD8pNNh0gPEjabCrxD4wmfBeewgnJ4Vqy\n spEFVjs6Ov/A==", "\n 9ROgH8Idwd/IcAdTKrRKQUhrl33LDA5vECbls5Kas6/icJEXRT9Wgx4Z4TXU0O7c7H+uGWSSSB\n WlekIMRr+qwg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9759\"; a=\"180374255\"", "E=Sophos;i=\"5.77,319,1596524400\"; d=\"scan'208\";a=\"180374255\"", "E=Sophos;i=\"5.77,319,1596524400\"; d=\"scan'208\";a=\"340885140\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>", "To": "jasvinder.singh@intel.com, bruce.richardson@intel.com,\n pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org, brendan.ryan@intel.com, david.coyle@intel.com,\n Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>", "Date": "Tue, 29 Sep 2020 16:36:00 +0100", "Message-Id": "<1601393761-11588-2-git-send-email-mairtin.oloingsigh@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1601393761-11588-1-git-send-email-mairtin.oloingsigh@intel.com>", "References": "<1601393761-11588-1-git-send-email-mairtin.oloingsigh@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/2] net: add run-time architecture specific\n\tCRC selection", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds support for run-time selection of the optimal\narchitecture-specific CRC path, based on the supported instruction set(s)\nof the CPU.\n\nThe compiler option checks have been moved from the C files to the meson\nscript. The rte_cpu_get_flag_enabled function is called automatically by\nthe library at process initialization time to determine which\ninstructions the CPU supports, with the most optimal supported CRC path\nultimately selected.\n\nSigned-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>\nSigned-off-by: David Coyle <david.coyle@intel.com>\n---\n doc/guides/rel_notes/release_20_11.rst | 4 ++\n lib/librte_net/meson.build | 34 +++++++++++-\n lib/librte_net/net_crc.h | 34 ++++++++++++\n lib/librte_net/{net_crc_neon.h => net_crc_neon.c} | 27 +++------\n lib/librte_net/{net_crc_sse.h => net_crc_sse.c} | 34 ++++--------\n lib/librte_net/rte_net_crc.c | 67 ++++++++++++++---------\n 6 files changed, 132 insertions(+), 68 deletions(-)\n create mode 100644 lib/librte_net/net_crc.h\n rename lib/librte_net/{net_crc_neon.h => net_crc_neon.c} (95%)\n rename lib/librte_net/{net_crc_sse.h => net_crc_sse.c} (94%)", "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 4eb3224a7..6bd222dca 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -55,6 +55,10 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Updated CRC modules of rte_net library.**\n+\n+ * Added run-time selection of the optimal architecture-specific CRC path.\n+\n * **Updated Cisco enic driver.**\n \n * Added support for VF representors with single-queue Tx/Rx and flow API\ndiff --git a/lib/librte_net/meson.build b/lib/librte_net/meson.build\nindex 24ed8253b..b6880bd85 100644\n--- a/lib/librte_net/meson.build\n+++ b/lib/librte_net/meson.build\n@@ -1,5 +1,5 @@\n # SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2017 Intel Corporation\n+# Copyright(c) 2017-2020 Intel Corporation\n \n headers = files('rte_ip.h',\n \t'rte_tcp.h',\n@@ -20,3 +20,35 @@ headers = files('rte_ip.h',\n \n sources = files('rte_arp.c', 'rte_ether.c', 'rte_net.c', 'rte_net_crc.c')\n deps += ['mbuf']\n+\n+if dpdk_conf.has('RTE_ARCH_X86_64')\n+\tnet_crc_sse42_cpu_support = \\\n+\t\tcc.get_define('__PCLMUL__', args: machine_args) != ''\n+\tnet_crc_sse42_cc_support = \\\n+\t\tcc.has_argument('-mpclmul') and cc.has_argument('-maes')\n+\n+\tbuild_static_net_crc_sse42_lib = 0\n+\n+\tif net_crc_sse42_cpu_support == true\n+\t\tsources += files('net_crc_sse.c')\n+\t\tcflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT']\n+\telif net_crc_sse42_cc_support == true\n+\t\tbuild_static_net_crc_sse42_lib = 1\n+\t\tnet_crc_sse42_lib_cflags = ['-mpclmul', '-maes']\n+\t\tcflags += ['-DCC_X86_64_SSE42_PCLMULQDQ_SUPPORT']\n+\tendif\n+\n+\tif build_static_net_crc_sse42_lib == 1\n+\t\tnet_crc_sse42_lib = static_library(\n+\t\t\t\t\t'net_crc_sse42_lib',\n+\t\t\t\t\t'net_crc_sse.c',\n+\t\t\t\t\tdependencies: static_rte_eal,\n+\t\t\t\t\tc_args: [cflags,\n+\t\t\t\t\t\tnet_crc_sse42_lib_cflags])\n+\t\tobjs += net_crc_sse42_lib.extract_objects('net_crc_sse.c')\n+\tendif\n+elif dpdk_conf.has('RTE_ARCH_ARM64') and \\\n+\t\tcc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != ''\n+\tsources += files('net_crc_neon.c')\n+\tcflags += ['-DCC_ARM64_NEON_PMULL_SUPPORT']\n+endif\ndiff --git a/lib/librte_net/net_crc.h b/lib/librte_net/net_crc.h\nnew file mode 100644\nindex 000000000..a1578a56c\n--- /dev/null\n+++ b/lib/librte_net/net_crc.h\n@@ -0,0 +1,34 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _NET_CRC_H_\n+#define _NET_CRC_H_\n+\n+/*\n+ * Different implementations of CRC\n+ */\n+\n+/* SSE4.2 */\n+\n+void\n+rte_net_crc_sse42_init(void);\n+\n+uint32_t\n+rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len);\n+\n+uint32_t\n+rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len);\n+\n+/* NEON */\n+\n+void\n+rte_net_crc_neon_init(void);\n+\n+uint32_t\n+rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len);\n+\n+uint32_t\n+rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len);\n+\n+#endif /* _NET_CRC_H_ */\ndiff --git a/lib/librte_net/net_crc_neon.h b/lib/librte_net/net_crc_neon.c\nsimilarity index 95%\nrename from lib/librte_net/net_crc_neon.h\nrename to lib/librte_net/net_crc_neon.c\nindex 63fa1d4a1..b79684ec2 100644\n--- a/lib/librte_net/net_crc_neon.h\n+++ b/lib/librte_net/net_crc_neon.c\n@@ -1,18 +1,17 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2017 Cavium, Inc\n+ * Copyright(c) 2020 Intel Corporation\n */\n \n-#ifndef _NET_CRC_NEON_H_\n-#define _NET_CRC_NEON_H_\n+#include <string.h>\n \n+#include <rte_common.h>\n #include <rte_branch_prediction.h>\n #include <rte_net_crc.h>\n #include <rte_vect.h>\n #include <rte_cpuflags.h>\n \n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n+#include \"net_crc.h\"\n \n /** PMULL CRC computation context structure */\n struct crc_pmull_ctx {\n@@ -218,7 +217,7 @@ crc32_eth_calc_pmull(\n \treturn n;\n }\n \n-static inline void\n+void\n rte_net_crc_neon_init(void)\n {\n \t/* Initialize CRC16 data */\n@@ -242,9 +241,8 @@ rte_net_crc_neon_init(void)\n \tcrc32_eth_pmull.rk7_rk8 = vld1q_u64(eth_k7_k8);\n }\n \n-static inline uint32_t\n-rte_crc16_ccitt_neon_handler(const uint8_t *data,\n-\tuint32_t data_len)\n+uint32_t\n+rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len)\n {\n \treturn (uint16_t)~crc32_eth_calc_pmull(data,\n \t\tdata_len,\n@@ -252,18 +250,11 @@ rte_crc16_ccitt_neon_handler(const uint8_t *data,\n \t\t&crc16_ccitt_pmull);\n }\n \n-static inline uint32_t\n-rte_crc32_eth_neon_handler(const uint8_t *data,\n-\tuint32_t data_len)\n+uint32_t\n+rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len)\n {\n \treturn ~crc32_eth_calc_pmull(data,\n \t\tdata_len,\n \t\t0xffffffffUL,\n \t\t&crc32_eth_pmull);\n }\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _NET_CRC_NEON_H_ */\ndiff --git a/lib/librte_net/net_crc_sse.h b/lib/librte_net/net_crc_sse.c\nsimilarity index 94%\nrename from lib/librte_net/net_crc_sse.h\nrename to lib/librte_net/net_crc_sse.c\nindex 1c7b7a548..053b54b39 100644\n--- a/lib/librte_net/net_crc_sse.h\n+++ b/lib/librte_net/net_crc_sse.c\n@@ -1,18 +1,16 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017 Intel Corporation\n+ * Copyright(c) 2017-2020 Intel Corporation\n */\n \n-#ifndef _RTE_NET_CRC_SSE_H_\n-#define _RTE_NET_CRC_SSE_H_\n+#include <string.h>\n \n+#include <rte_common.h>\n #include <rte_branch_prediction.h>\n+#include <rte_cpuflags.h>\n \n-#include <x86intrin.h>\n-#include <cpuid.h>\n+#include \"net_crc.h\"\n \n-#ifdef __cplusplus\n-extern \"C\" {\n-#endif\n+#include <x86intrin.h>\n \n /** PCLMULQDQ CRC computation context structure */\n struct crc_pclmulqdq_ctx {\n@@ -259,8 +257,7 @@ crc32_eth_calc_pclmulqdq(\n \treturn n;\n }\n \n-\n-static inline void\n+void\n rte_net_crc_sse42_init(void)\n {\n \tuint64_t k1, k2, k5, k6;\n@@ -303,12 +300,10 @@ rte_net_crc_sse42_init(void)\n \t * use other data types such as float, double, etc.\n \t */\n \t_mm_empty();\n-\n }\n \n-static inline uint32_t\n-rte_crc16_ccitt_sse42_handler(const uint8_t *data,\n-\tuint32_t data_len)\n+uint32_t\n+rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len)\n {\n \t/** return 16-bit CRC value */\n \treturn (uint16_t)~crc32_eth_calc_pclmulqdq(data,\n@@ -317,18 +312,11 @@ rte_crc16_ccitt_sse42_handler(const uint8_t *data,\n \t\t&crc16_ccitt_pclmulqdq);\n }\n \n-static inline uint32_t\n-rte_crc32_eth_sse42_handler(const uint8_t *data,\n-\tuint32_t data_len)\n+uint32_t\n+rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len)\n {\n \treturn ~crc32_eth_calc_pclmulqdq(data,\n \t\tdata_len,\n \t\t0xffffffffUL,\n \t\t&crc32_eth_pclmulqdq);\n }\n-\n-#ifdef __cplusplus\n-}\n-#endif\n-\n-#endif /* _RTE_NET_CRC_SSE_H_ */\ndiff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c\nindex 4f5b9e828..83dccbfba 100644\n--- a/lib/librte_net/rte_net_crc.c\n+++ b/lib/librte_net/rte_net_crc.c\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2017 Intel Corporation\n+ * Copyright(c) 2017-2020 Intel Corporation\n */\n \n #include <stddef.h>\n@@ -10,17 +10,7 @@\n #include <rte_common.h>\n #include <rte_net_crc.h>\n \n-#if defined(RTE_ARCH_X86_64) && defined(__PCLMUL__)\n-#define X86_64_SSE42_PCLMULQDQ 1\n-#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRYPTO)\n-#define ARM64_NEON_PMULL 1\n-#endif\n-\n-#ifdef X86_64_SSE42_PCLMULQDQ\n-#include <net_crc_sse.h>\n-#elif defined ARM64_NEON_PMULL\n-#include <net_crc_neon.h>\n-#endif\n+#include \"net_crc.h\"\n \n /** CRC polynomials */\n #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL\n@@ -47,13 +37,13 @@ static rte_net_crc_handler handlers_scalar[] = {\n \t[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,\n \t[RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,\n };\n-\n-#ifdef X86_64_SSE42_PCLMULQDQ\n+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n static rte_net_crc_handler handlers_sse42[] = {\n \t[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,\n \t[RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,\n };\n-#elif defined ARM64_NEON_PMULL\n+#endif\n+#ifdef CC_ARM64_NEON_PMULL_SUPPORT\n static rte_net_crc_handler handlers_neon[] = {\n \t[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,\n \t[RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,\n@@ -142,22 +132,44 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)\n \t\tcrc32_eth_lut);\n }\n \n+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n+static uint8_t\n+sse42_pclmulqdq_cpu_supported(void)\n+{\n+\treturn rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ);\n+}\n+#endif\n+\n+#ifdef CC_ARM64_NEON_PMULL_SUPPORT\n+static uint8_t\n+neon_pmull_cpu_supported(void)\n+{\n+\treturn rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL);\n+}\n+#endif\n+\n void\n rte_net_crc_set_alg(enum rte_net_crc_alg alg)\n {\n \tswitch (alg) {\n-#ifdef X86_64_SSE42_PCLMULQDQ\n+#ifdef RTE_ARCH_X86_64\n \tcase RTE_NET_CRC_SSE42:\n-\t\thandlers = handlers_sse42;\n-\t\tbreak;\n-#elif defined ARM64_NEON_PMULL\n-\t\t/* fall-through */\n+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n+\t\tif (sse42_pclmulqdq_cpu_supported()) {\n+\t\t\thandlers = handlers_sse42;\n+\t\t\tbreak;\n+\t\t}\n+#endif\n+#endif /* RTE_ARCH_X86_64 */\n+#ifdef RTE_ARCH_ARM64\n \tcase RTE_NET_CRC_NEON:\n-\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {\n+#ifdef CC_ARM64_NEON_PMULL_SUPPORT\n+\t\tif (neon_pmull_cpu_supported()) {\n \t\t\thandlers = handlers_neon;\n \t\t\tbreak;\n \t\t}\n #endif\n+#endif /* RTE_ARCH_ARM64 */\n \t\t/* fall-through */\n \tcase RTE_NET_CRC_SCALAR:\n \t\t/* fall-through */\n@@ -188,11 +200,14 @@ RTE_INIT(rte_net_crc_init)\n \n \trte_net_crc_scalar_init();\n \n-#ifdef X86_64_SSE42_PCLMULQDQ\n-\talg = RTE_NET_CRC_SSE42;\n-\trte_net_crc_sse42_init();\n-#elif defined ARM64_NEON_PMULL\n-\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {\n+#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT\n+\tif (sse42_pclmulqdq_cpu_supported()) {\n+\t\talg = RTE_NET_CRC_SSE42;\n+\t\trte_net_crc_sse42_init();\n+\t}\n+#endif\n+#ifdef CC_ARM64_NEON_PMULL_SUPPORT\n+\tif (neon_pmull_cpu_supported()) {\n \t\talg = RTE_NET_CRC_NEON;\n \t\trte_net_crc_neon_init();\n \t}\n", "prefixes": [ "v3", "1/2" ] }