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GET /api/patches/78731/?format=api
{ "id": 78731, "url": "https://patches.dpdk.org/api/patches/78731/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-52-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1600949555-28043-52-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1600949555-28043-52-git-send-email-arybchenko@solarflare.com", "date": "2020-09-24T12:12:26", "name": "[v3,51/60] common/sfc_efx/base: replace PCI efsys macros with functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bf77066083d2a1c4d9d0dcaf8e4a554d931e71c7", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1600949555-28043-52-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 12473, "url": "https://patches.dpdk.org/api/series/12473/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=12473", "date": "2020-09-24T12:11:40", "name": "common/sfc_efx: support Riverhead NIC family", "version": 3, "mbox": "https://patches.dpdk.org/series/12473/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/78731/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/78731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EAE5EA04B1;\n\tThu, 24 Sep 2020 14:22:47 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1F5841E4C8;\n\tThu, 24 Sep 2020 14:14:18 +0200 (CEST)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id CB9B91DE35\n for <dev@dpdk.org>; Thu, 24 Sep 2020 14:13:06 +0200 (CEST)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.60])\n by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id\n 579A76005E for <dev@dpdk.org>; Thu, 24 Sep 2020 12:13:06 +0000 (UTC)", "from us4-mdac16-37.ut7.mdlocal (unknown [10.7.66.156])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 55F08200A0\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:13:06 +0000 (UTC)", "from mx1-us1.ppe-hosted.com (unknown [10.7.65.200])\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n A28F11C005C\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:13:05 +0000 (UTC)", "from webmail.solarflare.com (uk.solarflare.com [193.34.186.16])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n (No client certificate requested)\n by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id\n 39CFD80005A\n for <dev@dpdk.org>; Thu, 24 Sep 2020 12:13:05 +0000 (UTC)", "from ukex01.SolarFlarecom.com (10.17.10.4) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Thu, 24 Sep 2020 13:12:48 +0100", "from opal.uk.solarflarecom.com (10.17.10.1) by\n ukex01.SolarFlarecom.com (10.17.10.4) with Microsoft SMTP Server id\n 15.0.1497.2 via Frontend Transport; Thu, 24 Sep 2020 13:12:48 +0100", "from ukv-loginhost.uk.solarflarecom.com\n (ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id 08OCCmeU026094;\n Thu, 24 Sep 2020 13:12:48 +0100", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 5CD891613A9;\n Thu, 24 Sep 2020 13:12:48 +0100 (BST)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Igor Romanov <igor.romanov@oktetlabs.ru>", "Date": "Thu, 24 Sep 2020 13:12:26 +0100", "Message-ID": "<1600949555-28043-52-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "References": "<1600764594-14752-1-git-send-email-arybchenko@solarflare.com>\n <1600949555-28043-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-TM-AS-Result": "No-6.347300-8.000000-10", "X-TMASE-MatchedRID": "+0fscSjG5oc1+o7k1G1Nsf3HILfxLV/9eouvej40T4htw+n+iKWyyABJ\n DO15WqH4lUCS+T43Hcy9gZrT7uIToMpY2Ci+polznFVnNmvv47tLXPA26IG0hN9RlPzeVuQQQEC\n MXtkIBFZ0U4rGHlQpbPYSjSdarl3/+gtEW3D/QKaHjFnwsKDMDC9Xl/s/QdUMuyL9jjE2skEWXb\n bsSFp0wcKUy0IWNZvl4BvGwuuszG+LA5FCQxdGvE+zv2ByYSDQfLNHMurfykged11F9IsKFAknl\n zYrXW3xGZx9oY8DzNHA7V1UWABhghp6rGfLEa9i4jRkIImnX0OC0NRF+4xj4NSNWqsiFFWqNTqH\n vNfE9UEzswktlxv7q2G474XgMsqlkfRhdidsajMURSScn+QSXt0H8LFZNFG7hqz53n/yPnoB5ZT\n RzcnhDQCrPP5q7dr9Gv5T3m92cgDWyNcAFRGx8boOfFLgUu3n", "X-TM-AS-User-Approved-Sender": "Yes", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--6.347300-8.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.6.1012-25674.003", "X-MDID": "1600949586-fyuCbfdULx93", "Subject": "[dpdk-dev] [PATCH v3 51/60] common/sfc_efx/base: replace PCI efsys\n\tmacros with functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Igor Romanov <igor.romanov@oktetlabs.ru>\n\nefsys macros that manipulate PCI devices cannot be defined in\ncommon sfc_efx DPDK driver since in DPDK build the bus drivers\nthat provide required functionality are built after common drivers.\n\nReplace the macros with function callbacks to remove that build\ndependency. Drivers now should pass the callbacks directly to\nefx function instead of defining implementation in efsys.\n\nSigned-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\nReviewed-by: Andy Moreton <amoreton@xilinx.com>\n---\n drivers/common/sfc_efx/base/efx.h | 29 ++++++++++++++++++++\n drivers/common/sfc_efx/base/efx_impl.h | 4 +++\n drivers/common/sfc_efx/base/efx_nic.c | 3 ++-\n drivers/common/sfc_efx/base/efx_pci.c | 34 +++++++++++++-----------\n drivers/common/sfc_efx/base/rhead_impl.h | 1 +\n drivers/common/sfc_efx/base/rhead_pci.c | 8 +++---\n 6 files changed, 60 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h\nindex 4a0a1231dc..7e747e6122 100644\n--- a/drivers/common/sfc_efx/base/efx.h\n+++ b/drivers/common/sfc_efx/base/efx.h\n@@ -82,6 +82,34 @@ efx_family(\n \n #if EFSYS_OPT_PCI\n \n+typedef struct efx_pci_ops_s {\n+\t/*\n+\t * Function for reading PCIe configuration space.\n+\t *\n+\t * espcp\tSystem-specific PCIe device handle;\n+\t * offset\tOffset inside PCIe configuration space to start reading\n+\t *\t\tfrom;\n+\t * edp\t\tEFX DWORD structure that should be populated by function\n+\t *\t\tin little-endian order;\n+\t *\n+\t * Returns status code, 0 on success, any other value on error.\n+\t */\n+\tefx_rc_t\t(*epo_config_readd)(efsys_pci_config_t *espcp,\n+\t\t\t\t\t uint32_t offset, efx_dword_t *edp);\n+\t/*\n+\t * Function for finding PCIe memory bar handle by its index from a PCIe\n+\t * device handle. The found memory bar is available in read-only mode.\n+\t *\n+\t * configp\tSystem-specific PCIe device handle;\n+\t * index\tMemory bar index;\n+\t * memp\t\tPointer to the found memory bar handle;\n+\t *\n+\t * Returns status code, 0 on success, any other value on error.\n+\t */\n+\tefx_rc_t\t(*epo_find_mem_bar)(efsys_pci_config_t *configp,\n+\t\t\t\t\t int index, efsys_bar_t *memp);\n+} efx_pci_ops_t;\n+\n /* Determine EFX family and perform lookup of the function control window\n *\n * The function requires PCI config handle from which all memory bars can\n@@ -95,6 +123,7 @@ efx_family_probe_bar(\n \t__in\t\tuint16_t venid,\n \t__in\t\tuint16_t devid,\n \t__in\t\tefsys_pci_config_t *espcp,\n+\t__in\t\tconst efx_pci_ops_t *epop,\n \t__out\t\tefx_family_t *efp,\n \t__out\t\tefx_bar_region_t *ebrp);\n \ndiff --git a/drivers/common/sfc_efx/base/efx_impl.h b/drivers/common/sfc_efx/base/efx_impl.h\nindex be3f3f6bf5..f58586bee0 100644\n--- a/drivers/common/sfc_efx/base/efx_impl.h\n+++ b/drivers/common/sfc_efx/base/efx_impl.h\n@@ -1588,6 +1588,7 @@ LIBEFX_INTERNAL\n extern\t__checkReturn\t\t\tefx_rc_t\n efx_pci_config_find_next_ext_cap(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__in\t\t\t\tuint16_t cap_id,\n \t__inout\t\t\t\tsize_t *offsetp);\n \n@@ -1602,6 +1603,7 @@ LIBEFX_INTERNAL\n extern\t__checkReturn\t\t\tefx_rc_t\n efx_pci_config_next_ext_cap(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__inout\t\t\t\tsize_t *offsetp);\n \n /*\n@@ -1614,6 +1616,7 @@ LIBEFX_INTERNAL\n extern\t__checkReturn\t\t\tefx_rc_t\n efx_pci_find_next_xilinx_cap_table(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__inout\t\t\t\tsize_t *pci_cap_offsetp,\n \t__out\t\t\t\tunsigned int *xilinx_tbl_barp,\n \t__out\t\t\t\tefsys_dma_addr_t *xilinx_tbl_offsetp);\n@@ -1629,6 +1632,7 @@ LIBEFX_INTERNAL\n extern\t__checkReturn\t\t\tefx_rc_t\n efx_pci_read_ext_cap_xilinx_table(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__in\t\t\t\tsize_t cap_offset,\n \t__out\t\t\t\tunsigned int *barp,\n \t__out\t\t\t\tefsys_dma_addr_t *offsetp);\ndiff --git a/drivers/common/sfc_efx/base/efx_nic.c b/drivers/common/sfc_efx/base/efx_nic.c\nindex dcf0987ebf..a78c4c3737 100644\n--- a/drivers/common/sfc_efx/base/efx_nic.c\n+++ b/drivers/common/sfc_efx/base/efx_nic.c\n@@ -110,6 +110,7 @@ efx_family_probe_bar(\n \t__in\t\tuint16_t venid,\n \t__in\t\tuint16_t devid,\n \t__in\t\tefsys_pci_config_t *espcp,\n+\t__in\t\tconst efx_pci_ops_t *epop,\n \t__out\t\tefx_family_t *efp,\n \t__out\t\tefx_bar_region_t *ebrp)\n {\n@@ -121,7 +122,7 @@ efx_family_probe_bar(\n #if EFSYS_OPT_RIVERHEAD\n \t\tcase EFX_PCI_DEVID_RIVERHEAD:\n \t\tcase EFX_PCI_DEVID_RIVERHEAD_VF:\n-\t\t\trc = rhead_pci_nic_membar_lookup(espcp, ebrp);\n+\t\t\trc = rhead_pci_nic_membar_lookup(espcp, epop, ebrp);\n \t\t\tif (rc == 0)\n \t\t\t\t*efp = EFX_FAMILY_RIVERHEAD;\n \ndiff --git a/drivers/common/sfc_efx/base/efx_pci.c b/drivers/common/sfc_efx/base/efx_pci.c\nindex bdf995cf84..1e7307476f 100644\n--- a/drivers/common/sfc_efx/base/efx_pci.c\n+++ b/drivers/common/sfc_efx/base/efx_pci.c\n@@ -12,6 +12,7 @@\n \t__checkReturn\t\t\tefx_rc_t\n efx_pci_config_next_ext_cap(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__inout\t\t\t\tsize_t *offsetp)\n {\n \tefx_dword_t hdr;\n@@ -26,9 +27,9 @@ efx_pci_config_next_ext_cap(\n \tif (*offsetp == 0) {\n \t\t*offsetp = ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE;\n \t} else {\n-\t\tEFSYS_PCI_CONFIG_READD(espcp, *offsetp +\n+\t\trc = epop->epo_config_readd(espcp, *offsetp +\n \t\t\t\t(EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8),\n-\t\t\t\t&hdr, &rc);\n+\t\t\t\t&hdr);\n \t\tif (rc != 0) {\n \t\t\trc = EIO;\n \t\t\tgoto fail2;\n@@ -58,6 +59,7 @@ efx_pci_config_next_ext_cap(\n \t__checkReturn\t\t\tefx_rc_t\n efx_pci_config_find_next_ext_cap(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__in\t\t\t\tuint16_t cap_id,\n \t__inout\t\t\t\tsize_t *offsetp)\n {\n@@ -73,7 +75,7 @@ efx_pci_config_find_next_ext_cap(\n \tposition = *offsetp;\n \n \twhile (1) {\n-\t\trc = efx_pci_config_next_ext_cap(espcp, &position);\n+\t\trc = efx_pci_config_next_ext_cap(espcp, epop, &position);\n \t\tif (rc != 0) {\n \t\t\tif (rc == ENOENT)\n \t\t\t\tbreak;\n@@ -81,9 +83,9 @@ efx_pci_config_find_next_ext_cap(\n \t\t\t\tgoto fail2;\n \t\t}\n \n-\t\tEFSYS_PCI_CONFIG_READD(espcp, position +\n+\t\trc = epop->epo_config_readd(espcp, position +\n \t\t\t\t(EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8),\n-\t\t\t\t&hdr, &rc);\n+\t\t\t\t&hdr);\n \t\tif (rc != 0) {\n \t\t\trc = EIO;\n \t\t\tgoto fail3;\n@@ -116,6 +118,7 @@ efx_pci_config_find_next_ext_cap(\n \t__checkReturn\t\t\tefx_rc_t\n efx_pci_find_next_xilinx_cap_table(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__inout\t\t\t\tsize_t *pci_cap_offsetp,\n \t__out\t\t\t\tunsigned int *xilinx_tbl_barp,\n \t__out\t\t\t\tefsys_dma_addr_t *xilinx_tbl_offsetp)\n@@ -134,7 +137,7 @@ efx_pci_find_next_xilinx_cap_table(\n \t\tunsigned int tbl_bar;\n \t\tefsys_dma_addr_t tbl_offset;\n \n-\t\trc = efx_pci_config_find_next_ext_cap(espcp,\n+\t\trc = efx_pci_config_find_next_ext_cap(espcp, epop,\n \t\t\t\tESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR, &cap_offset);\n \t\tif (rc != 0) {\n \t\t\tif (rc == ENOENT)\n@@ -149,7 +152,7 @@ efx_pci_find_next_xilinx_cap_table(\n \t\t * locator. Try to read it and skip it if the capability is\n \t\t * not the locator.\n \t\t */\n-\t\trc = efx_pci_read_ext_cap_xilinx_table(espcp, cap_offset,\n+\t\trc = efx_pci_read_ext_cap_xilinx_table(espcp, epop, cap_offset,\n \t\t\t\t\t\t &tbl_bar, &tbl_offset);\n \t\tif (rc == 0) {\n \t\t\t*xilinx_tbl_barp = tbl_bar;\n@@ -183,6 +186,7 @@ efx_pci_find_next_xilinx_cap_table(\n \t__checkReturn\t\t\tefx_rc_t\n efx_pci_read_ext_cap_xilinx_table(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__in\t\t\t\tsize_t cap_offset,\n \t__out\t\t\t\tunsigned int *barp,\n \t__out\t\t\t\tefsys_dma_addr_t *offsetp)\n@@ -199,9 +203,9 @@ efx_pci_read_ext_cap_xilinx_table(\n \tefsys_dma_addr_t offset;\n \tefx_rc_t rc;\n \n-\tEFSYS_PCI_CONFIG_READD(espcp, cap_offset +\n+\trc = epop->epo_config_readd(espcp, cap_offset +\n \t\t\t (EFX_LOW_BIT(ESF_GZ_PCI_EXPRESS_XCAP_ID) / 8),\n-\t\t\t &cap_hdr, &rc);\n+\t\t\t &cap_hdr);\n \tif (rc != 0) {\n \t\trc = EIO;\n \t\tgoto fail1;\n@@ -213,9 +217,9 @@ efx_pci_read_ext_cap_xilinx_table(\n \t\tgoto fail2;\n \t}\n \n-\tEFSYS_PCI_CONFIG_READD(espcp, vsec_offset +\n+\trc = epop->epo_config_readd(espcp, vsec_offset +\n \t\t\t (EFX_LOW_BIT(ESF_GZ_VSEC_ID) / 8),\n-\t\t\t &vsec.eo_dword[0], &rc);\n+\t\t\t &vsec.eo_dword[0]);\n \tif (rc != 0) {\n \t\trc = EIO;\n \t\tgoto fail3;\n@@ -240,9 +244,9 @@ efx_pci_read_ext_cap_xilinx_table(\n \t\tgoto fail5;\n \t}\n \n-\tEFSYS_PCI_CONFIG_READD(espcp, vsec_offset +\n+\trc = epop->epo_config_readd(espcp, vsec_offset +\n \t\t\t (EFX_LOW_BIT(ESF_GZ_VSEC_TBL_BAR) / 8),\n-\t\t\t &vsec.eo_dword[1], &rc);\n+\t\t\t &vsec.eo_dword[1]);\n \tif (rc != 0) {\n \t\trc = EIO;\n \t\tgoto fail6;\n@@ -252,9 +256,9 @@ efx_pci_read_ext_cap_xilinx_table(\n \toffset_low = EFX_OWORD_FIELD32(vsec, ESF_GZ_VSEC_TBL_OFF_LO);\n \n \tif (vsec_len >= ESE_GZ_VSEC_LEN_HIGH_OFFT) {\n-\t\tEFSYS_PCI_CONFIG_READD(espcp, vsec_offset +\n+\t\trc = epop->epo_config_readd(espcp, vsec_offset +\n \t\t\t\t(EFX_LOW_BIT(ESF_GZ_VSEC_TBL_OFF_HI) / 8),\n-\t\t\t\t&vsec.eo_dword[2], &rc);\n+\t\t\t\t&vsec.eo_dword[2]);\n \t\tif (rc != 0) {\n \t\t\trc = EIO;\n \t\t\tgoto fail7;\ndiff --git a/drivers/common/sfc_efx/base/rhead_impl.h b/drivers/common/sfc_efx/base/rhead_impl.h\nindex 4d5307d18b..3383c47ec6 100644\n--- a/drivers/common/sfc_efx/base/rhead_impl.h\n+++ b/drivers/common/sfc_efx/base/rhead_impl.h\n@@ -461,6 +461,7 @@ LIBEFX_INTERNAL\n extern\t__checkReturn\t\t\tefx_rc_t\n rhead_pci_nic_membar_lookup(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__out\t\t\t\tefx_bar_region_t *ebrp);\n \n #endif /* EFSYS_OPT_PCI */\ndiff --git a/drivers/common/sfc_efx/base/rhead_pci.c b/drivers/common/sfc_efx/base/rhead_pci.c\nindex dfb163b96d..0f4b4cb910 100644\n--- a/drivers/common/sfc_efx/base/rhead_pci.c\n+++ b/drivers/common/sfc_efx/base/rhead_pci.c\n@@ -47,6 +47,7 @@ rhead_xilinx_cap_tbl_find_ef100_locator(\n \t__checkReturn\t\t\tefx_rc_t\n rhead_pci_nic_membar_lookup(\n \t__in\t\t\t\tefsys_pci_config_t *espcp,\n+\t__in\t\t\t\tconst efx_pci_ops_t *epop,\n \t__out\t\t\t\tefx_bar_region_t *ebrp)\n {\n \tboolean_t xilinx_tbl_found = B_FALSE;\n@@ -65,7 +66,8 @@ rhead_pci_nic_membar_lookup(\n \t * the following discovery steps.\n \t */\n \twhile (1) {\n-\t\trc = efx_pci_find_next_xilinx_cap_table(espcp, &pci_capa_offset,\n+\t\trc = efx_pci_find_next_xilinx_cap_table(espcp, epop,\n+\t\t\t\t\t\t\t&pci_capa_offset,\n \t\t\t\t\t\t\t&xilinx_tbl_bar,\n \t\t\t\t\t\t\t&xilinx_tbl_offset);\n \t\tif (rc != 0) {\n@@ -90,7 +92,7 @@ rhead_pci_nic_membar_lookup(\n \n \t\txilinx_tbl_found = B_TRUE;\n \n-\t\tEFSYS_PCI_FIND_MEM_BAR(espcp, xilinx_tbl_bar, &xil_eb, &rc);\n+\t\trc = epop->epo_find_mem_bar(espcp, xilinx_tbl_bar, &xil_eb);\n \t\tif (rc != 0)\n \t\t\tgoto fail2;\n \n@@ -110,7 +112,7 @@ rhead_pci_nic_membar_lookup(\n \tif (bar_found == B_FALSE)\n \t\tgoto fail4;\n \n-\tEFSYS_PCI_FIND_MEM_BAR(espcp, ebrp->ebr_index, &nic_eb, &rc);\n+\trc = epop->epo_find_mem_bar(espcp, ebrp->ebr_index, &nic_eb);\n \tif (rc != 0)\n \t\tgoto fail5;\n \n", "prefixes": [ "v3", "51/60" ] }