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{
    "id": 7702,
    "url": "https://patches.dpdk.org/api/patches/7702/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1444992324-5504-2-git-send-email-alejandro.lucero@netronome.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1444992324-5504-2-git-send-email-alejandro.lucero@netronome.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1444992324-5504-2-git-send-email-alejandro.lucero@netronome.com",
    "date": "2015-10-16T10:45:21",
    "name": "[dpdk-dev,v3,1/4] nfp: new poll mode driver for netronome nfp6000 card",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "fb8a95e99653319f1e4777ed74777d3cfcab0f16",
    "submitter": {
        "id": 270,
        "url": "https://patches.dpdk.org/api/people/270/?format=api",
        "name": "Alejandro Lucero",
        "email": "alejandro.lucero@netronome.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1444992324-5504-2-git-send-email-alejandro.lucero@netronome.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/7702/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/7702/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id A85498E99;\n\tFri, 16 Oct 2015 12:45:20 +0200 (CEST)",
            "from ubuntu (host217-39-174-19.in-addr.btopenworld.com\n\t[217.39.174.19]) by dpdk.org (Postfix) with SMTP id 0083B2FDD\n\tfor <dev@dpdk.org>; Fri, 16 Oct 2015 12:45:11 +0200 (CEST)",
            "by ubuntu (Postfix, from userid 5466)\n\tid 9E4D9EA763; Fri, 16 Oct 2015 11:45:24 +0100 (BST)"
        ],
        "From": "\"Alejandro.Lucero\" <alejandro.lucero@netronome.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 16 Oct 2015 11:45:21 +0100",
        "Message-Id": "<1444992324-5504-2-git-send-email-alejandro.lucero@netronome.com>",
        "X-Mailer": "git-send-email 1.7.9.5",
        "In-Reply-To": "<1444992324-5504-1-git-send-email-alejandro.lucero@netronome.com>",
        "References": "<1444992324-5504-1-git-send-email-alejandro.lucero@netronome.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "quoted-printable",
        "Subject": "[dpdk-dev] =?utf-8?q?=5BPATCH_v3_1/4=5D_nfp=3A_new_poll_mode_driv?=\n\t=?utf-8?q?er_for_netronome_nfp6000_card?=",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: \"Alejandro.Lucero\" <alejandro.lucero@netronome.com>\n\nThis patch adds a new PMD for using PCI Virtual Functions with Netronome\nnfp6000 card.\n\nSigned-off-by: Alejandro.Lucero <alejandro.lucero@netronome.com>\nSigned-off-by: Rolf.Neugebauer <rolf.neugebauer@netronome.com>\n---\n MAINTAINERS                          |    9 +\n config/common_linuxapp               |    6 +\n doc/guides/rel_notes/release_2_2.rst |    8 +\n drivers/net/Makefile                 |    1 +\n drivers/net/nfp/Makefile             |   88 ++\n drivers/net/nfp/nfp_net.c            | 2495 ++++++++++++++++++++++++++++++++++\n drivers/net/nfp/nfp_net_ctrl.h       |  290 ++++\n drivers/net/nfp/nfp_net_logs.h       |   75 +\n drivers/net/nfp/nfp_net_pmd.h        |  434 ++++++\n mk/rte.app.mk                        |    1 +\n 10 files changed, 3407 insertions(+)\n create mode 100644 drivers/net/nfp/Makefile\n create mode 100644 drivers/net/nfp/nfp_net.c\n create mode 100644 drivers/net/nfp/nfp_net_ctrl.h\n create mode 100644 drivers/net/nfp/nfp_net_logs.h\n create mode 100644 drivers/net/nfp/nfp_net_pmd.h",
    "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 080a8e8..1fb2ba6 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -167,6 +167,10 @@ FreeBSD UIO\n M: Bruce Richardson <bruce.richardson@intel.com>\n F: lib/librte_eal/bsdapp/nic_uio/\n \n+NFP UIO\n+M: Alejandro Lucero <alejandro.lucero@netronome.com>\n+F: lib/librte_eal/linuxapp/nfp_uio/\n+\n \n Core Libraries\n --------------\n@@ -255,6 +259,11 @@ M: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n F: drivers/net/mlx4/\n F: doc/guides/nics/mlx4.rst\n \n+Netronome NFP\n+M: Alejandro Lucero <alejandro.lucero@netronome.com>\n+F: drivers/net/nfp/\n+F: doc/guides/nics/nfp.rst\n+\n RedHat virtio\n M: Huawei Xie <huawei.xie@intel.com>\n M: Changchun Ouyang <changchun.ouyang@intel.com>\ndiff --git a/config/common_linuxapp b/config/common_linuxapp\nindex 0de43d5..d8d6384 100644\n--- a/config/common_linuxapp\n+++ b/config/common_linuxapp\n@@ -108,6 +108,7 @@ CONFIG_RTE_LIBEAL_USE_HPET=n\n CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n\n CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n\n CONFIG_RTE_EAL_IGB_UIO=y\n+CONFIG_RTE_EAL_NFP_UIO=y\n CONFIG_RTE_EAL_VFIO=y\n CONFIG_RTE_MALLOC_DEBUG=n\n \n@@ -238,6 +239,11 @@ CONFIG_RTE_LIBRTE_ENIC_PMD=y\n CONFIG_RTE_LIBRTE_ENIC_DEBUG=n\n \n #\n+# Compile burst-oriented Netronome PMD driver\n+#\n+CONFIG_RTE_LIBRTE_NFP_PMD=y\n+\n+#\n # Compile burst-oriented VIRTIO PMD driver\n #\n CONFIG_RTE_LIBRTE_VIRTIO_PMD=y\ndiff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst\nindex 5687676..364cca3 100644\n--- a/doc/guides/rel_notes/release_2_2.rst\n+++ b/doc/guides/rel_notes/release_2_2.rst\n@@ -16,6 +16,10 @@ EAL\n   Fixed issue where the ``rte_epoll_wait()`` function didn't return when the\n   underlying call to ``epoll_wait()`` timed out.\n \n+* **eal/linuxapp: New UIO driver for Netronome´s NFP support**\n+\n+  Netronome´s NFP PMD requires some specific configuration. Current implementation\n+  supports just VFs. Future PF support will require major changes to this driver.\n \n Drivers\n ~~~~~~~\n@@ -39,6 +43,10 @@ Drivers\n \n   Fixed issue with libvirt ``virsh destroy`` not killing the VM.\n \n+* **drivers/net: New PMD for Netronome´s NFP 6xxx cards**\n+\n+  PMD supporting VFs with Netronome´s NFP card. It requires specific UIO\n+  driver, nfp_uio, and previous configuration using Netronome´s BSP.\n \n Libraries\n ~~~~~~~~~\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex 5ebf963..bc08591 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -48,6 +48,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += ring\n DIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio\n DIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += vmxnet3\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += xenvirt\n+DIRS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp\n \n include $(RTE_SDK)/mk/rte.sharelib.mk\n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/net/nfp/Makefile b/drivers/net/nfp/Makefile\nnew file mode 100644\nindex 0000000..ef74e27\n--- /dev/null\n+++ b/drivers/net/nfp/Makefile\n@@ -0,0 +1,88 @@\n+#   BSD LICENSE\n+#\n+#   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+#   All rights reserved.\n+#\n+#   Redistribution and use in source and binary forms, with or without\n+#   modification, are permitted provided that the following conditions\n+#   are met:\n+#\n+#     * Redistributions of source code must retain the above copyright\n+#       notice, this list of conditions and the following disclaimer.\n+#     * Redistributions in binary form must reproduce the above copyright\n+#       notice, this list of conditions and the following disclaimer in\n+#       the documentation and/or other materials provided with the\n+#       distribution.\n+#     * Neither the name of Intel Corporation nor the names of its\n+#       contributors may be used to endorse or promote products derived\n+#       from this software without specific prior written permission.\n+#\n+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+#   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_nfp.a\n+\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+\n+#\n+# Add extra flags for base driver files (also known as shared code)\n+# to disable warnings\n+#\n+ifeq ($(CC), icc)\n+CFLAGS_BASE_DRIVER = -wd593\n+else ifeq ($(CC), clang)\n+CFLAGS_BASE_DRIVER += -Wno-sign-compare\n+CFLAGS_BASE_DRIVER += -Wno-unused-value\n+CFLAGS_BASE_DRIVER += -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-strict-aliasing\n+CFLAGS_BASE_DRIVER += -Wno-format\n+CFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\n+CFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast\n+CFLAGS_BASE_DRIVER += -Wno-format-nonliteral\n+else\n+CFLAGS_BASE_DRIVER  = -Wno-sign-compare\n+CFLAGS_BASE_DRIVER += -Wno-unused-value\n+CFLAGS_BASE_DRIVER += -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-strict-aliasing\n+CFLAGS_BASE_DRIVER += -Wno-format\n+CFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\n+CFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast\n+CFLAGS_BASE_DRIVER += -Wno-format-nonliteral\n+CFLAGS_BASE_DRIVER += -Wno-format-security\n+\n+ifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\n+CFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable\n+endif\n+\n+endif\n+OBJS_BASE_DRIVER=$(patsubst %.c,%.o,$(notdir $(wildcard $(RTE_SDK)/lib/librte_pmd_nfp/*.c)))\n+$(foreach obj, $(OBJS_BASE_DRIVER), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n+\n+VPATH += $(RTE_SDK)/drivers/net/nfp/\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+SRCS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += nfp_net.c\n+\n+# this lib depends upon:\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += lib/librte_eal lib/librte_ether\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += lib/librte_mempool lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_NFP_PMD) += lib/librte_net lib/librte_malloc\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/nfp/nfp_net.c b/drivers/net/nfp/nfp_net.c\nnew file mode 100644\nindex 0000000..2f2d6fc\n--- /dev/null\n+++ b/drivers/net/nfp/nfp_net.c\n@@ -0,0 +1,2495 @@\n+/*\n+ * Copyright (c) 2014, 2015 Netronome Systems, Inc.\n+ * All rights reserved.\n+ *\n+ * Small portions derived from code Copyright(c) 2010-2015 Intel Corporation.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *  this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *  notice, this list of conditions and the following disclaimer in the\n+ *  documentation and/or other materials provided with the distribution\n+ *\n+ * 3. Neither the name of the copyright holder nor the names of its\n+ *  contributors may be used to endorse or promote products derived from this\n+ *  software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/*\n+ * vim:shiftwidth=8:noexpandtab\n+ *\n+ * @file dpdk/pmd/nfp_net.c\n+ *\n+ * Netronome vNIC DPDK Poll-Mode Driver: Main entry point\n+ */\n+\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <stdint.h>\n+#include <unistd.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <sys/socket.h>\n+#include <sys/io.h>\n+#include <assert.h>\n+#include <time.h>\n+#include <math.h>\n+#include <inttypes.h>\n+\n+#include <rte_byteorder.h>\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_debug.h>\n+#include <rte_ethdev.h>\n+#include <rte_dev.h>\n+#include <rte_ether.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_mempool.h>\n+#include <rte_version.h>\n+#include <rte_string_fns.h>\n+#include <rte_alarm.h>\n+\n+#include \"nfp_net_pmd.h\"\n+#include \"nfp_net_logs.h\"\n+#include \"nfp_net_ctrl.h\"\n+\n+/* Prototypes */\n+static void nfp_net_close(struct rte_eth_dev *dev);\n+static int nfp_net_configure(struct rte_eth_dev *dev);\n+static void nfp_net_dev_interrupt_handler(struct rte_intr_handle *handle,\n+\t\t\t\t\t  void *param);\n+static void nfp_net_dev_interrupt_delayed_handler(void *param);\n+static int nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n+static void nfp_net_infos_get(struct rte_eth_dev *dev,\n+\t\t\t      struct rte_eth_dev_info *dev_info);\n+static int nfp_net_init(struct rte_eth_dev *eth_dev);\n+static int nfp_net_link_update(struct rte_eth_dev *dev, int wait_to_complete);\n+static void nfp_net_promisc_enable(struct rte_eth_dev *dev);\n+static void nfp_net_promisc_disable(struct rte_eth_dev *dev);\n+static int nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq);\n+static uint32_t nfp_net_rx_queue_count(struct rte_eth_dev *dev,\n+\t\t\t\t       uint16_t queue_idx);\n+static uint16_t nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n+\t\t\t\t  uint16_t nb_pkts);\n+static void nfp_net_rx_queue_release(void *rxq);\n+static int nfp_net_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t\t  uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t\t  const struct rte_eth_rxconf *rx_conf,\n+\t\t\t\t  struct rte_mempool *mp);\n+static int nfp_net_tx_free_bufs(struct nfp_net_txq *txq);\n+static void nfp_net_tx_queue_release(void *txq);\n+static int nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t\t\t  uint16_t nb_desc, unsigned int socket_id,\n+\t\t\t\t  const struct rte_eth_txconf *tx_conf);\n+static int nfp_net_start(struct rte_eth_dev *dev);\n+static void nfp_net_stats_get(struct rte_eth_dev *dev,\n+\t\t\t      struct rte_eth_stats *stats);\n+static void nfp_net_stats_reset(struct rte_eth_dev *dev);\n+static void nfp_net_stop(struct rte_eth_dev *dev);\n+static uint16_t nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\t  uint16_t nb_pkts);\n+\n+/*\n+ * The offset of the queue controller queues in the PCIe Target. These\n+ * happen to be at the same offset on the NFP6000 and the NFP3200 so\n+ * we use a single macro here.\n+ */\n+#define NFP_PCIE_QUEUE(_q)\t(0x80000 + (0x800 * ((_q) & 0xff)))\n+\n+/* Maximum value which can be added to a queue with one transaction */\n+#define NFP_QCP_MAX_ADD\t0x7f\n+\n+#define RTE_MBUF_DMA_ADDR_DEFAULT(mb) \\\n+\t(uint64_t)((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n+\n+/* nfp_qcp_ptr - Read or Write Pointer of a queue */\n+enum nfp_qcp_ptr {\n+\tNFP_QCP_READ_PTR = 0,\n+\tNFP_QCP_WRITE_PTR\n+};\n+\n+/*\n+ * nfp_qcp_ptr_add - Add the value to the selected pointer of a queue\n+ * @q: Base address for queue structure\n+ * @ptr: Add to the Read or Write pointer\n+ * @val: Value to add to the queue pointer\n+ *\n+ * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.\n+ */\n+static inline void\n+nfp_qcp_ptr_add(__u8 *q, enum nfp_qcp_ptr ptr, __u32 val)\n+{\n+\t__u32 off;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_ADD_RPTR;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_ADD_WPTR;\n+\n+\twhile (val > NFP_QCP_MAX_ADD) {\n+\t\tnn_writel(rte_cpu_to_le_32(NFP_QCP_MAX_ADD), q + off);\n+\t\tval -= NFP_QCP_MAX_ADD;\n+\t}\n+\n+\tnn_writel(rte_cpu_to_le_32(val), q + off);\n+}\n+\n+/*\n+ * nfp_qcp_read - Read the current Read/Write pointer value for a queue\n+ * @q:  Base address for queue structure\n+ * @ptr: Read or Write pointer\n+ */\n+static inline __u32\n+nfp_qcp_read(__u8 *q, enum nfp_qcp_ptr ptr)\n+{\n+\t__u32 off;\n+\t__u32 val;\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\toff = NFP_QCP_QUEUE_STS_LO;\n+\telse\n+\t\toff = NFP_QCP_QUEUE_STS_HI;\n+\n+\tval = rte_cpu_to_le_32(nn_readl(q + off));\n+\n+\tif (ptr == NFP_QCP_READ_PTR)\n+\t\treturn val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;\n+\telse\n+\t\treturn val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;\n+}\n+\n+/*\n+ * Functions to read/write from/to Config BAR\n+ * Performs any endian conversion necessary.\n+ */\n+static inline __u8\n+nn_cfg_readb(struct nfp_net_hw *hw, int off)\n+{\n+\treturn nn_readb(hw->ctrl_bar + off);\n+}\n+\n+static inline void\n+nn_cfg_writeb(struct nfp_net_hw *hw, int off, __u8 val)\n+{\n+\tnn_writeb(val, hw->ctrl_bar + off);\n+}\n+\n+static inline __u32\n+nn_cfg_readl(struct nfp_net_hw *hw, int off)\n+{\n+\treturn rte_le_to_cpu_32(nn_readl(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writel(struct nfp_net_hw *hw, int off, __u32 val)\n+{\n+\tnn_writel(rte_cpu_to_le_32(val), hw->ctrl_bar + off);\n+}\n+\n+static inline __u64\n+nn_cfg_readq(struct nfp_net_hw *hw, int off)\n+{\n+\treturn rte_le_to_cpu_64(nn_readq(hw->ctrl_bar + off));\n+}\n+\n+static inline void\n+nn_cfg_writeq(struct nfp_net_hw *hw, int off, __u64 val)\n+{\n+\tnn_writeq(rte_cpu_to_le_64(val), hw->ctrl_bar + off);\n+}\n+\n+/* Creating memzone for hardware rings. */\n+static const struct rte_memzone *\n+ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n+\t\t      uint16_t queue_id, uint32_t ring_size, int socket_id)\n+{\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\n+\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n+\t\t dev->driver->pci_drv.name,\n+\t\t ring_name, dev->data->port_id, queue_id);\n+\n+\tmz = rte_memzone_lookup(z_name);\n+\tif (mz)\n+\t\treturn mz;\n+\n+\treturn rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0,\n+\t\t\t\t\t   NFP_MEMZONE_ALIGN);\n+}\n+\n+/*\n+ * Atomically reads link status information from global structure rte_eth_dev.\n+ *\n+ * @param dev\n+ *   - Pointer to the structure rte_eth_dev to read from.\n+ *   - Pointer to the buffer to be saved with the link status.\n+ *\n+ * @return\n+ *   - On success, zero.\n+ *   - On failure, negative value.\n+ */\n+static inline int\n+nfp_net_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n+\t\t\t\t    struct rte_eth_link *link)\n+{\n+\tstruct rte_eth_link *dst = link;\n+\tstruct rte_eth_link *src = &dev->data->dev_link;\n+\n+\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n+\t\t\t\t*(uint64_t *)src) == 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Atomically writes the link status information into global\n+ * structure rte_eth_dev.\n+ *\n+ * @param dev\n+ *   - Pointer to the structure rte_eth_dev to read from.\n+ *   - Pointer to the buffer to be saved with the link status.\n+ *\n+ * @return\n+ *   - On success, zero.\n+ *   - On failure, negative value.\n+ */\n+static inline int\n+nfp_net_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n+\t\t\t\t     struct rte_eth_link *link)\n+{\n+\tstruct rte_eth_link *dst = &dev->data->dev_link;\n+\tstruct rte_eth_link *src = link;\n+\n+\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n+\t\t\t\t*(uint64_t *)src) == 0)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static void\n+nfp_net_rx_queue_release_mbufs(struct nfp_net_rxq *rxq)\n+{\n+\tunsigned i;\n+\n+\tif (rxq->rxbufs == NULL)\n+\t\treturn;\n+\n+\tfor (i = 0; i < rxq->rx_count; i++) {\n+\t\tif (rxq->rxbufs[i].mbuf) {\n+\t\t\trte_pktmbuf_free_seg(rxq->rxbufs[i].mbuf);\n+\t\t\trxq->rxbufs[i].mbuf = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static void\n+nfp_net_rx_queue_release(void *rx_queue)\n+{\n+\tstruct nfp_net_rxq *rxq = rx_queue;\n+\n+\tif (rxq) {\n+\t\tnfp_net_rx_queue_release_mbufs(rxq);\n+\t\trte_free(rxq->rxbufs);\n+\t\trte_free(rxq);\n+\t}\n+}\n+\n+static void\n+nfp_net_reset_rx_queue(struct nfp_net_rxq *rxq)\n+{\n+\tnfp_net_rx_queue_release_mbufs(rxq);\n+\trxq->wr_p = 0;\n+\trxq->rd_p = 0;\n+\trxq->nb_rx_hold = 0;\n+}\n+\n+static void\n+nfp_net_tx_queue_release_mbufs(struct nfp_net_txq *txq)\n+{\n+\tunsigned i;\n+\n+\tif (txq->txbufs == NULL)\n+\t\treturn;\n+\n+\tfor (i = 0; i < txq->tx_count; i++) {\n+\t\tif (txq->txbufs[i].mbuf) {\n+\t\t\trte_pktmbuf_free_seg(txq->txbufs[i].mbuf);\n+\t\t\ttxq->txbufs[i].mbuf = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static void\n+nfp_net_tx_queue_release(void *tx_queue)\n+{\n+\tstruct nfp_net_txq *txq = tx_queue;\n+\n+\tif (txq) {\n+\t\tnfp_net_tx_queue_release_mbufs(txq);\n+\t\trte_free(txq->txbufs);\n+\t\trte_free(txq);\n+\t}\n+}\n+\n+static void\n+nfp_net_reset_tx_queue(struct nfp_net_txq *txq)\n+{\n+\tnfp_net_tx_queue_release_mbufs(txq);\n+\ttxq->wr_p = 0;\n+\ttxq->rd_p = 0;\n+\ttxq->tail = 0;\n+}\n+\n+static int\n+__nfp_net_reconfig(struct nfp_net_hw *hw, __u32 update)\n+{\n+\tint cnt;\n+\t__u32 new;\n+\tstruct timespec wait;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Writing to the configuration queue (%p)...\\n\",\n+\t\t    hw->qcp_cfg);\n+\n+\tif (hw->qcp_cfg == NULL)\n+\t\trte_panic(\"Bad configuration queue pointer\\n\");\n+\n+\tnfp_qcp_ptr_add(hw->qcp_cfg, NFP_QCP_WRITE_PTR, 1);\n+\n+\twait.tv_sec = 0;\n+\twait.tv_nsec = 1000000;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Polling for update ack...\\n\");\n+\n+\t/* Poll update field, waiting for NFP to ack the config */\n+\tfor (cnt = 0; ; cnt++) {\n+\t\tnew = nn_cfg_readl(hw, NFP_NET_CFG_UPDATE);\n+\t\tif (new == 0)\n+\t\t\tbreak;\n+\t\tif (new & NFP_NET_CFG_UPDATE_ERR) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Reconfig error: 0x%08x\\n\", new);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (cnt >= NFP_NET_POLL_TIMEOUT) {\n+\t\t\tPMD_INIT_LOG(ERR, \"Reconfig timeout for 0x%08x after\"\n+\t\t\t\t\t  \" %dms\\n\", update, cnt);\n+\t\t\trte_panic(\"Exiting\\n\");\n+\t\t}\n+\t\tnanosleep(&wait, 0); /* waiting for a 1ms */\n+\t}\n+\tPMD_DRV_LOG(DEBUG, \"Ack DONE\\n\");\n+\treturn 0;\n+}\n+\n+/*\n+ * Reconfigure the NIC\n+ * @nn:    device to reconfigure\n+ * @ctrl:    The value for the ctrl field in the BAR config\n+ * @update:  The value for the update field in the BAR config\n+ *\n+ * Write the update word to the BAR and ping the reconfig queue. Then poll\n+ * until the firmware has acknowledged the update by zeroing the update word.\n+ */\n+static int\n+nfp_net_reconfig(struct nfp_net_hw *hw, __u32 ctrl, __u32 update)\n+{\n+\t__u32 err;\n+\n+\tPMD_DRV_LOG(DEBUG, \"nfp_net_reconfig: ctrl=%08x update=%08x\\n\",\n+\t\t    ctrl, update);\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, ctrl);\n+\tnn_cfg_writel(hw, NFP_NET_CFG_UPDATE, update);\n+\n+\trte_wmb();\n+\n+\terr = __nfp_net_reconfig(hw, update);\n+\n+\tif (!err)\n+\t\treturn 0;\n+\n+\t/*\n+\t * Reconfig errors imply situations where they can be handled.\n+\t * Otherwise, rte_panic is called inside __nfp_net_reconfig\n+\t */\n+\tPMD_INIT_LOG(ERR, \"Error nfp_net reconfig for ctrl: %x update: %x\\n\",\n+\t\t     ctrl, update);\n+\treturn -EIO;\n+}\n+\n+/*\n+ * Configure an Ethernet device. This function must be invoked first\n+ * before any other function in the Ethernet API. This function can\n+ * also be re-invoked when a device is in the stopped state.\n+ */\n+static int\n+nfp_net_configure(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_conf *dev_conf;\n+\tstruct rte_eth_rxmode *rxmode;\n+\tstruct rte_eth_txmode *txmode;\n+\tuint32_t new_ctrl = 0;\n+\tuint32_t update = 0;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/*\n+\t * A DPDK app sends info about how many queues to use and how\n+\t * those queues need to be configured. This is used by the\n+\t * DPDK core and it makes sure no more queues than those\n+\t * advertised by the driver are requested. This function is\n+\t * called after that internal process\n+\t */\n+\n+\tPMD_INIT_LOG(DEBUG, \"Configure\\n\");\n+\n+\tdev_conf = &dev->data->dev_conf;\n+\trxmode = &dev_conf->rxmode;\n+\ttxmode = &dev_conf->txmode;\n+\n+\t/* Checking TX mode */\n+\tif (txmode->mq_mode) {\n+\t\tPMD_INIT_LOG(INFO, \"TX mq_mode DCB and VMDq not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Checking RX mode */\n+\tif (rxmode->mq_mode & ETH_MQ_RX_RSS) {\n+\t\tif (hw->cap & NFP_NET_CFG_CTRL_RSS) {\n+\t\t\tupdate = NFP_NET_CFG_UPDATE_RSS;\n+\t\t\tnew_ctrl = NFP_NET_CFG_CTRL_RSS;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(INFO, \"RSS not supported\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (rxmode->split_hdr_size) {\n+\t\tPMD_INIT_LOG(INFO, \"rxmode does not support split header\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rxmode->hw_ip_checksum) {\n+\t\tif (hw->cap & NFP_NET_CFG_CTRL_RXCSUM) {\n+\t\t\tnew_ctrl |= NFP_NET_CFG_CTRL_RXCSUM;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(INFO, \"RXCSUM not supported\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (rxmode->hw_vlan_filter) {\n+\t\tPMD_INIT_LOG(INFO, \"VLAN filter not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rxmode->hw_vlan_strip) {\n+\t\tif (hw->cap & NFP_NET_CFG_CTRL_RXVLAN) {\n+\t\t\tnew_ctrl |= NFP_NET_CFG_CTRL_RXVLAN;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(INFO, \"hw vlan strip not supported\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (rxmode->hw_vlan_extend) {\n+\t\tPMD_INIT_LOG(INFO, \"VLAN extended not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Supporting VLAN insertion by default */\n+\tif (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)\n+\t\tnew_ctrl |= NFP_NET_CFG_CTRL_TXVLAN;\n+\n+\tif (rxmode->jumbo_frame)\n+\t\t/* this is handled in rte_eth_dev_configure */\n+\n+\tif (rxmode->hw_strip_crc) {\n+\t\tPMD_INIT_LOG(INFO, \"strip CRC not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rxmode->enable_scatter) {\n+\t\tPMD_INIT_LOG(INFO, \"Scatter not supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!new_ctrl)\n+\t\treturn 0;\n+\n+\tupdate |= NFP_NET_CFG_UPDATE_GEN;\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn -EIO;\n+\n+\thw->ctrl = new_ctrl;\n+\n+\treturn 0;\n+}\n+\n+static void\n+nfp_net_enable_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct nfp_net_hw *hw;\n+\tuint64_t enabled_queues = 0;\n+\tint i;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/* Enabling the required TX queues in the device */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n+\t\tenabled_queues |= (1 << i);\n+\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, enabled_queues);\n+\n+\tenabled_queues = 0;\n+\n+\t/* Enabling the required RX queues in the device */\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n+\t\tenabled_queues |= (1 << i);\n+\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, enabled_queues);\n+}\n+\n+static void\n+nfp_net_disable_queues(struct rte_eth_dev *dev)\n+{\n+\tstruct nfp_net_hw *hw;\n+\tuint32_t new_ctrl, update = 0;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_TXRS_ENABLE, 0);\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_RXRS_ENABLE, 0);\n+\n+\tnew_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_ENABLE;\n+\tupdate = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING |\n+\t\t NFP_NET_CFG_UPDATE_MSIX;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)\n+\t\tnew_ctrl &= ~NFP_NET_CFG_CTRL_RINGCFG;\n+\n+\t/* If an error when reconfig we avoid to change hw state */\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn;\n+\n+\thw->ctrl = new_ctrl;\n+}\n+\n+static int\n+nfp_net_rx_freelist_setup(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tif (nfp_net_rx_fill_freelist(dev->data->rx_queues[i]) < 0)\n+\t\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+static void\n+nfp_net_params_setup(struct nfp_net_hw *hw)\n+{\n+\tuint32_t *mac_address;\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_MTU, hw->mtu);\n+\tnn_cfg_writel(hw, NFP_NET_CFG_FLBUFSZ, hw->flbufsz);\n+\n+\t/* A MAC address is 8 bytes long */\n+\tmac_address = (uint32_t *)(hw->mac_addr);\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_MACADDR,\n+\t\t      rte_cpu_to_be_32(*mac_address));\n+\tnn_cfg_writel(hw, NFP_NET_CFG_MACADDR + 4,\n+\t\t      rte_cpu_to_be_32(*(mac_address + 4)));\n+}\n+\n+static void\n+nfp_net_cfg_queue_setup(struct nfp_net_hw *hw)\n+{\n+\thw->qcp_cfg = hw->tx_bar + NFP_QCP_QUEUE_ADDR_SZ;\n+}\n+\n+static int\n+nfp_net_start(struct rte_eth_dev *dev)\n+{\n+\tuint32_t new_ctrl, update = 0;\n+\tstruct nfp_net_hw *hw;\n+\tint ret;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_LOG(DEBUG, \"Start\\n\");\n+\n+\t/* Disabling queues just in case... */\n+\tnfp_net_disable_queues(dev);\n+\n+\t/* Writing configuration parameters in the device */\n+\tnfp_net_params_setup(hw);\n+\n+\t/* Enabling the required queues in the device */\n+\tnfp_net_enable_queues(dev);\n+\n+\t/* Enable device */\n+\tnew_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_ENABLE | NFP_NET_CFG_UPDATE_MSIX;\n+\tupdate = NFP_NET_CFG_UPDATE_GEN | NFP_NET_CFG_UPDATE_RING;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_RINGCFG)\n+\t\tnew_ctrl |= NFP_NET_CFG_CTRL_RINGCFG;\n+\n+\tnn_cfg_writel(hw, NFP_NET_CFG_CTRL, new_ctrl);\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn -EIO;\n+\n+\t/*\n+\t * Allocating rte mbuffs for configured rx queues.\n+\t * This requires queues being enabled before\n+\t */\n+\tif (nfp_net_rx_freelist_setup(dev) < 0) {\n+\t\tret = -ENOMEM;\n+\t\tgoto error;\n+\t}\n+\n+\thw->ctrl = new_ctrl;\n+\n+\treturn 0;\n+\n+error:\n+\t/*\n+\t * An error returned by this function should mean the app\n+\t * exiting and then the system releasing all the memory\n+\t * allocated even memory coming from hugepages.\n+\t *\n+\t * The device could be enabled at this point with some queues\n+\t * ready for getting packets. This is true if the call to\n+\t * nfp_net_rx_freelist_setup() succeeds for some queues but\n+\t * fails for subsequent queues.\n+\t *\n+\t * This should make the app exiting but better if we tell the\n+\t * device first.\n+\t */\n+\tnfp_net_disable_queues(dev);\n+\n+\treturn ret;\n+}\n+\n+/* Stop device: disable rx and tx functions to allow for reconfiguring. */\n+static void\n+nfp_net_stop(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Stop\\n\");\n+\n+\tnfp_net_disable_queues(dev);\n+\n+\t/* Clear queues */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tnfp_net_reset_tx_queue(\n+\t\t\t(struct nfp_net_txq *)dev->data->tx_queues[i]);\n+\t}\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tnfp_net_reset_rx_queue(\n+\t\t\t(struct nfp_net_rxq *)dev->data->rx_queues[i]);\n+\t}\n+}\n+\n+/* Reset and stop device. The device can not be restarted. */\n+static void\n+nfp_net_close(struct rte_eth_dev *dev)\n+{\n+\tstruct nfp_net_hw *hw;\n+\n+\tPMD_INIT_LOG(DEBUG, \"Close\\n\");\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/*\n+\t * We assume that the DPDK application is stopping all the\n+\t * threads/queues before calling the device close function.\n+\t */\n+\n+\tnfp_net_stop(dev);\n+\n+\trte_intr_disable(&dev->pci_dev->intr_handle);\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, 0xff);\n+\n+\t/*\n+\t * The ixgbe PMD driver disables the pcie master on the\n+\t * device. The i40e does not...\n+\t */\n+}\n+\n+static void\n+nfp_net_promisc_enable(struct rte_eth_dev *dev)\n+{\n+\tuint32_t new_ctrl, update = 0;\n+\tstruct nfp_net_hw *hw;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Promiscuous mode enable\\n\");\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (!(hw->cap & NFP_NET_CFG_CTRL_PROMISC)) {\n+\t\tPMD_INIT_LOG(INFO, \"Promiscuous mode not supported\\n\");\n+\t\treturn;\n+\t}\n+\n+\tif (hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) {\n+\t\tPMD_DRV_LOG(INFO, \"Promiscuous mode already enabled\\n\");\n+\t\treturn;\n+\t}\n+\n+\tnew_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_PROMISC;\n+\tupdate = NFP_NET_CFG_UPDATE_GEN;\n+\n+\t/*\n+\t * DPDK sets promiscuous mode on just after this call assuming\n+\t * it can not fail ...\n+\t */\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn;\n+\n+\thw->ctrl = new_ctrl;\n+}\n+\n+static void\n+nfp_net_promisc_disable(struct rte_eth_dev *dev)\n+{\n+\tuint32_t new_ctrl, update = 0;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif ((hw->ctrl & NFP_NET_CFG_CTRL_PROMISC) == 0) {\n+\t\tPMD_DRV_LOG(INFO, \"Promiscuous mode already disabled\\n\");\n+\t\treturn;\n+\t}\n+\n+\tnew_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_PROMISC;\n+\tupdate = NFP_NET_CFG_UPDATE_GEN;\n+\n+\t/*\n+\t * DPDK sets promiscuous mode off just before this call\n+\t * assuming it can not fail ...\n+\t */\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn;\n+\n+\thw->ctrl = new_ctrl;\n+}\n+\n+/*\n+ * return 0 means link status changed, -1 means not changed\n+ *\n+ * Wait to complete is needed as it can take up to 9 seconds to get the Link\n+ * status.\n+ */\n+static int\n+nfp_net_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n+{\n+\tstruct nfp_net_hw *hw;\n+\tstruct rte_eth_link link, old;\n+\tuint32_t nn_link_status;\n+\n+\tPMD_DRV_LOG(DEBUG, \"Link update\\n\");\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tmemset(&old, 0, sizeof(old));\n+\tnfp_net_dev_atomic_read_link_status(dev, &old);\n+\n+\tnn_link_status = nn_cfg_readl(hw, NFP_NET_CFG_STS);\n+\n+\tmemset(&link, 0, sizeof(struct rte_eth_link));\n+\n+\tif (nn_link_status & NFP_NET_CFG_STS_LINK)\n+\t\tlink.link_status = 1;\n+\n+\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n+\t/* Other cards can limit the tx and rx rate per VF */\n+\tlink.link_speed = ETH_LINK_SPEED_40G;\n+\n+\tif (old.link_status != link.link_status) {\n+\t\tnfp_net_dev_atomic_write_link_status(dev, &link);\n+\t\tif (link.link_status)\n+\t\t\tPMD_DRV_LOG(INFO, \"NIC Link is Up\\n\");\n+\t\telse\n+\t\t\tPMD_DRV_LOG(INFO, \"NIC Link is Down\\n\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+static void\n+nfp_net_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tint i;\n+\tstruct nfp_net_hw *hw;\n+\tstruct rte_eth_stats nfp_dev_stats;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/* RTE_ETHDEV_QUEUE_STAT_CNTRS default value is 16 */\n+\n+\t/* reading per RX ring stats */\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tif (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)\n+\t\t\tbreak;\n+\n+\t\tnfp_dev_stats.q_ipackets[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));\n+\n+\t\tnfp_dev_stats.q_ipackets[i] -=\n+\t\t\thw->eth_stats_base.q_ipackets[i];\n+\n+\t\tnfp_dev_stats.q_ibytes[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n+\n+\t\tnfp_dev_stats.q_ibytes[i] -=\n+\t\t\thw->eth_stats_base.q_ibytes[i];\n+\t}\n+\n+\t/* reading per TX ring stats */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)\n+\t\t\tbreak;\n+\n+\t\tnfp_dev_stats.q_opackets[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));\n+\n+\t\tnfp_dev_stats.q_opackets[i] -=\n+\t\t\thw->eth_stats_base.q_opackets[i];\n+\n+\t\tnfp_dev_stats.q_obytes[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n+\n+\t\tnfp_dev_stats.q_obytes[i] -=\n+\t\t\thw->eth_stats_base.q_obytes[i];\n+\t}\n+\n+\tnfp_dev_stats.ipackets =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);\n+\n+\tnfp_dev_stats.ipackets -= hw->eth_stats_base.ipackets;\n+\n+\tnfp_dev_stats.ibytes =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);\n+\n+\tnfp_dev_stats.ibytes -= hw->eth_stats_base.ibytes;\n+\n+\tnfp_dev_stats.opackets =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);\n+\n+\tnfp_dev_stats.opackets -= hw->eth_stats_base.opackets;\n+\n+\tnfp_dev_stats.obytes =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);\n+\n+\tnfp_dev_stats.obytes -= hw->eth_stats_base.obytes;\n+\n+\tnfp_dev_stats.imcasts =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);\n+\n+\tnfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;\n+\n+\t/* reading general device stats */\n+\tnfp_dev_stats.ierrors =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);\n+\n+\tnfp_dev_stats.ierrors -= hw->eth_stats_base.ierrors;\n+\n+\tnfp_dev_stats.oerrors =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);\n+\n+\tnfp_dev_stats.oerrors -= hw->eth_stats_base.oerrors;\n+\n+\t/* Multicast frames received */\n+\tnfp_dev_stats.imcasts =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);\n+\n+\tnfp_dev_stats.imcasts -= hw->eth_stats_base.imcasts;\n+\n+\t/* RX ring mbuf allocation failures */\n+\tnfp_dev_stats.rx_nombuf = dev->data->rx_mbuf_alloc_failed;\n+\n+\tnfp_dev_stats.imissed =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);\n+\n+\tnfp_dev_stats.imissed -= hw->eth_stats_base.imissed;\n+\n+\tif (stats)\n+\t\tmemcpy(stats, &nfp_dev_stats, sizeof(*stats));\n+}\n+\n+static void\n+nfp_net_stats_reset(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/*\n+\t * hw->eth_stats_base records the per counter starting point.\n+\t * Lets update it now\n+\t */\n+\n+\t/* reading per RX ring stats */\n+\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\tif (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)\n+\t\t\tbreak;\n+\n+\t\thw->eth_stats_base.q_ipackets[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i));\n+\n+\t\thw->eth_stats_base.q_ibytes[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_RXR_STATS(i) + 0x8);\n+\t}\n+\n+\t/* reading per TX ring stats */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (i == RTE_ETHDEV_QUEUE_STAT_CNTRS)\n+\t\t\tbreak;\n+\n+\t\thw->eth_stats_base.q_opackets[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i));\n+\n+\t\thw->eth_stats_base.q_obytes[i] =\n+\t\t\tnn_cfg_readq(hw, NFP_NET_CFG_TXR_STATS(i) + 0x8);\n+\t}\n+\n+\thw->eth_stats_base.ipackets =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_FRAMES);\n+\n+\thw->eth_stats_base.ibytes =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_OCTETS);\n+\n+\thw->eth_stats_base.opackets =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_FRAMES);\n+\n+\thw->eth_stats_base.obytes =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_OCTETS);\n+\n+\thw->eth_stats_base.imcasts =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);\n+\n+\t/* reading general device stats */\n+\thw->eth_stats_base.ierrors =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_ERRORS);\n+\n+\thw->eth_stats_base.oerrors =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_TX_ERRORS);\n+\n+\t/* Multicast frames received */\n+\thw->eth_stats_base.imcasts =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_MC_FRAMES);\n+\n+\t/* RX ring mbuf allocation failures */\n+\tdev->data->rx_mbuf_alloc_failed = 0;\n+\n+\thw->eth_stats_base.imissed =\n+\t\tnn_cfg_readq(hw, NFP_NET_CFG_STATS_RX_DISCARDS);\n+}\n+\n+static void\n+nfp_net_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tdev_info->driver_name = dev->driver->pci_drv.name;\n+\tdev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;\n+\tdev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;\n+\tdev_info->min_rx_bufsize = ETHER_MIN_MTU;\n+\tdev_info->max_rx_pktlen = hw->max_mtu;\n+\t/* Next should change when PF support is implemented */\n+\tdev_info->max_mac_addrs = 1;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_RXVLAN)\n+\t\tdev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_RXCSUM)\n+\t\tdev_info->rx_offload_capa |= DEV_RX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t\t     DEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t\t     DEV_RX_OFFLOAD_TCP_CKSUM;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)\n+\t\tdev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT;\n+\n+\tif (hw->cap & NFP_NET_CFG_CTRL_TXCSUM)\n+\t\tdev_info->tx_offload_capa |= DEV_TX_OFFLOAD_IPV4_CKSUM |\n+\t\t\t\t\t     DEV_RX_OFFLOAD_UDP_CKSUM |\n+\t\t\t\t\t     DEV_RX_OFFLOAD_TCP_CKSUM;\n+\n+\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n+\t\t.rx_thresh = {\n+\t\t\t.pthresh = DEFAULT_RX_PTHRESH,\n+\t\t\t.hthresh = DEFAULT_RX_HTHRESH,\n+\t\t\t.wthresh = DEFAULT_RX_WTHRESH,\n+\t\t},\n+\t\t.rx_free_thresh = DEFAULT_RX_FREE_THRESH,\n+\t\t.rx_drop_en = 0,\n+\t};\n+\n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_thresh = {\n+\t\t\t.pthresh = DEFAULT_TX_PTHRESH,\n+\t\t\t.hthresh = DEFAULT_TX_HTHRESH,\n+\t\t\t.wthresh = DEFAULT_TX_WTHRESH,\n+\t\t},\n+\t\t.tx_free_thresh = DEFAULT_TX_FREE_THRESH,\n+\t\t.tx_rs_thresh = DEFAULT_TX_RSBIT_THRESH,\n+\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n+\t\t\t     ETH_TXQ_FLAGS_NOOFFLOADS,\n+\t};\n+\n+\tdev_info->reta_size = NFP_NET_CFG_RSS_ITBL_SZ;\n+#if RTE_VER_MAJOR == 2 && RTE_VER_MINOR >= 1\n+\tdev_info->hash_key_size = NFP_NET_CFG_RSS_KEY_SZ;\n+#endif\n+}\n+\n+static uint32_t\n+nfp_net_rx_queue_count(struct rte_eth_dev *dev, uint16_t queue_idx)\n+{\n+\tstruct nfp_net_rxq *rxq;\n+\tstruct nfp_net_rx_desc *rxds;\n+\t__u32 idx;\n+\t__u32 count;\n+\n+\trxq = (struct nfp_net_rxq *)dev->data->rx_queues[queue_idx];\n+\n+\tif (rxq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Bad queue: %u\\n\", queue_idx);\n+\t\treturn 0;\n+\t}\n+\n+\tidx = rxq->rd_p % rxq->rx_count;\n+\trxds = &rxq->rxds[idx];\n+\n+\tcount = 0;\n+\n+\t/*\n+\t * Other PMDs are just checking the DD bit in intervals of 4\n+\t * descriptors and counting all four if the first has the DD\n+\t * bit on. Of course, this is not accurate but can be good for\n+\t * perfomance. But ideally that should be done in descriptors\n+\t * chunks belonging to the same cache line\n+\t */\n+\n+\twhile (count < rxq->rx_count) {\n+\t\trxds = &rxq->rxds[idx];\n+\t\tif ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)\n+\t\t\tbreak;\n+\n+\t\tcount++;\n+\t\tidx++;\n+\n+\t\t/* Wrapping? */\n+\t\tif ((idx) == rxq->rx_count)\n+\t\t\tidx = 0;\n+\t}\n+\n+\treturn count;\n+}\n+\n+static void\n+nfp_net_dev_link_status_print(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_eth_link link;\n+\n+\tmemset(&link, 0, sizeof(link));\n+\tnfp_net_dev_atomic_read_link_status(dev, &link);\n+\tif (link.link_status)\n+\t\tRTE_LOG(INFO, PMD, \"Port %d: Link Up - speed %u Mbps - %s\\n\",\n+\t\t\t(int)(dev->data->port_id), (unsigned)link.link_speed,\n+\t\t\tlink.link_duplex == ETH_LINK_FULL_DUPLEX\n+\t\t\t? \"full-duplex\" : \"half-duplex\");\n+\telse\n+\t\tRTE_LOG(INFO, PMD, \" Port %d: Link Down\\n\",\n+\t\t\t(int)(dev->data->port_id));\n+\n+\tRTE_LOG(INFO, PMD, \"PCI Address: %04d:%02d:%02d:%d\\n\",\n+\t\tdev->pci_dev->addr.domain, dev->pci_dev->addr.bus,\n+\t\tdev->pci_dev->addr.devid, dev->pci_dev->addr.function);\n+}\n+\n+/* Interrupt configuration and handling */\n+\n+/*\n+ * nfp_net_irq_unmask - Unmask an interrupt\n+ *\n+ * If MSI-X auto-masking is enabled clear the mask bit, otherwise\n+ * clear the ICR for the entry.\n+ */\n+static void\n+nfp_net_irq_unmask(struct rte_eth_dev *dev)\n+{\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (hw->ctrl & NFP_NET_CFG_CTRL_MSIXAUTO) {\n+\t\t/* If MSI-X auto-masking is used, clear the entry */\n+\t\trte_wmb();\n+\t\trte_intr_enable(&dev->pci_dev->intr_handle);\n+\t} else {\n+\t\t/* Make sure all updates are written before un-masking */\n+\t\trte_wmb();\n+\t\tnn_cfg_writeb(hw, NFP_NET_CFG_ICR(NFP_NET_IRQ_LSC_IDX),\n+\t\t\t      NFP_NET_CFG_ICR_UNMASKED);\n+\t}\n+}\n+\n+static void\n+nfp_net_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n+\t\t\t      void *param)\n+{\n+\tint64_t timeout;\n+\tstruct rte_eth_link link;\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\n+\tPMD_DRV_LOG(DEBUG, \"We got a LSC interrupt!!!\\n\");\n+\n+\t/* get the link status */\n+\tmemset(&link, 0, sizeof(link));\n+\tnfp_net_dev_atomic_read_link_status(dev, &link);\n+\n+\tnfp_net_link_update(dev, 0);\n+\n+\t/* likely to up */\n+\tif (!link.link_status) {\n+\t\t/* handle it 1 sec later, wait it being stable */\n+\t\ttimeout = NFP_NET_LINK_UP_CHECK_TIMEOUT;\n+\t\t/* likely to down */\n+\t} else {\n+\t\t/* handle it 4 sec later, wait it being stable */\n+\t\ttimeout = NFP_NET_LINK_DOWN_CHECK_TIMEOUT;\n+\t}\n+\n+\tif (rte_eal_alarm_set(timeout * 1000,\n+\t\t\t      nfp_net_dev_interrupt_delayed_handler,\n+\t\t\t      (void *)dev) < 0) {\n+\t\tRTE_LOG(ERR, PMD, \"Error setting alarm\");\n+\t\t/* Unmasking */\n+\t\tnfp_net_irq_unmask(dev);\n+\t}\n+}\n+\n+/*\n+ * Interrupt handler which shall be registered for alarm callback for delayed\n+ * handling specific interrupt to wait for the stable nic state. As the NIC\n+ * interrupt state is not stable for nfp after link is just down, it needs\n+ * to wait 4 seconds to get the stable status.\n+ *\n+ * @param handle   Pointer to interrupt handle.\n+ * @param param    The address of parameter (struct rte_eth_dev *)\n+ *\n+ * @return  void\n+ */\n+static void\n+nfp_net_dev_interrupt_delayed_handler(void *param)\n+{\n+\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n+\n+\tnfp_net_link_update(dev, 0);\n+\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);\n+\n+\tnfp_net_dev_link_status_print(dev);\n+\n+\t/* Unmasking */\n+\tnfp_net_irq_unmask(dev);\n+}\n+\n+static int\n+nfp_net_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n+{\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\t/* check that mtu is within the allowed range */\n+\tif ((mtu < ETHER_MIN_MTU) || ((uint32_t)mtu > hw->max_mtu))\n+\t\treturn -EINVAL;\n+\n+\t/* switch to jumbo mode if needed */\n+\tif ((uint32_t)mtu > ETHER_MAX_LEN)\n+\t\tdev->data->dev_conf.rxmode.jumbo_frame = 1;\n+\telse\n+\t\tdev->data->dev_conf.rxmode.jumbo_frame = 0;\n+\n+\t/* update max frame size */\n+\tdev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)mtu;\n+\n+\t/* writing to configuration space */\n+\tnn_cfg_writel(hw, NFP_NET_CFG_MTU, (uint32_t)mtu);\n+\n+\thw->mtu = mtu;\n+\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_rx_queue_setup(struct rte_eth_dev *dev,\n+\t\t       uint16_t queue_idx, uint16_t nb_desc,\n+\t\t       unsigned int socket_id,\n+\t\t       const struct rte_eth_rxconf *rx_conf,\n+\t\t       struct rte_mempool *mp)\n+{\n+\tconst struct rte_memzone *tz;\n+\tstruct nfp_net_rxq *rxq;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Validating number of descriptors */\n+\tif (((nb_desc * sizeof(struct nfp_net_rx_desc)) % 128) != 0 ||\n+\t    (nb_desc > NFP_NET_MAX_RX_DESC) ||\n+\t    (nb_desc < NFP_NET_MIN_RX_DESC)) {\n+\t\tRTE_LOG(ERR, PMD, \"Wrong nb_desc value\\n\");\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/*\n+\t * Free memory prior to re-allocation if needed. This is the case after\n+\t * calling nfp_net_stop\n+\t */\n+\tif (dev->data->rx_queues[queue_idx]) {\n+\t\tnfp_net_rx_queue_release(dev->data->rx_queues[queue_idx]);\n+\t\tdev->data->rx_queues[queue_idx] = NULL;\n+\t}\n+\n+\t/* Allocating rx queue data structure */\n+\trxq = rte_zmalloc_socket(\"ethdev RX queue\", sizeof(struct nfp_net_rxq),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (rxq == NULL)\n+\t\treturn (-ENOMEM);\n+\n+\t/* Hw queues mapping based on firmware confifguration */\n+\trxq->qidx = queue_idx;\n+\trxq->fl_qcidx = queue_idx * hw->stride_rx;\n+\trxq->rx_qcidx = rxq->fl_qcidx + (hw->stride_rx - 1);\n+\trxq->qcp_fl = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->fl_qcidx);\n+\trxq->qcp_rx = hw->rx_bar + NFP_QCP_QUEUE_OFF(rxq->rx_qcidx);\n+\n+\t/*\n+\t * Tracking mbuf size for detecting a potential mbuf overflow due to\n+\t * NFP_NET_RX_OFFSET\n+\t */\n+\trxq->mem_pool = mp;\n+\trxq->mbuf_size = rxq->mem_pool->elt_size;\n+\trxq->mbuf_size -= (sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM);\n+\thw->flbufsz = rxq->mbuf_size;\n+\n+\trxq->rx_count = nb_desc;\n+\trxq->port_id = dev->data->port_id;\n+\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n+\trxq->drop_en = rx_conf->rx_drop_en;\n+\n+\t/*\n+\t * Allocate RX ring hardware descriptors. A memzone large enough to\n+\t * handle the maximum ring size is allocated in order to allow for\n+\t * resizing in later calls to the queue setup function.\n+\t */\n+\ttz = ring_dma_zone_reserve(dev, \"rx_ring\", queue_idx,\n+\t\t\t\t   sizeof(struct nfp_net_rx_desc) *\n+\t\t\t\t   NFP_NET_MAX_RX_DESC, socket_id);\n+\n+\tif (tz == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"Error allocatig rx dma\\n\");\n+\t\tnfp_net_rx_queue_release(rxq);\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\t/* Saving physical and virtual addresses for the RX ring */\n+\trxq->dma = (uint64_t)tz->phys_addr;\n+\trxq->rxds = (struct nfp_net_rx_desc *)tz->addr;\n+\n+\t/* mbuf pointers array for referencing mbufs linked to RX descriptors */\n+\trxq->rxbufs = rte_zmalloc_socket(\"rxq->rxbufs\",\n+\t\t\t\t\t sizeof(*rxq->rxbufs) * nb_desc,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (rxq->rxbufs == NULL) {\n+\t\tnfp_net_rx_queue_release(rxq);\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\tPMD_RX_LOG(DEBUG, \"rxbufs=%p hw_ring=%p dma_addr=0x%\" PRIx64 \"\\n\",\n+\t\t   rxq->rxbufs, rxq->rxds, (unsigned long int)rxq->dma);\n+\n+\tnfp_net_reset_rx_queue(rxq);\n+\n+\tdev->data->rx_queues[queue_idx] = rxq;\n+\trxq->hw = hw;\n+\n+\t/*\n+\t * Telling the HW about the physical address of the RX ring and number\n+\t * of descriptors in log2 format\n+\t */\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_RXR_ADDR(queue_idx), rxq->dma);\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_RXR_SZ(queue_idx), log2(nb_desc));\n+\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_rx_fill_freelist(struct nfp_net_rxq *rxq)\n+{\n+\tstruct nfp_net_rx_buff *rxe = rxq->rxbufs;\n+\tuint64_t dma_addr;\n+\tunsigned i;\n+\n+\tPMD_RX_LOG(DEBUG, \"nfp_net_rx_fill_freelist for %u descriptors\\n\",\n+\t\t   rxq->rx_count);\n+\n+\tfor (i = 0; i < rxq->rx_count; i++) {\n+\t\tstruct nfp_net_rx_desc *rxd;\n+\t\tstruct rte_mbuf *mbuf = rte_pktmbuf_alloc(rxq->mem_pool);\n+\n+\t\tif (mbuf == NULL) {\n+\t\t\tRTE_LOG(ERR, PMD, \"RX mbuf alloc failed queue_id=%u\\n\",\n+\t\t\t\t(unsigned)rxq->qidx);\n+\t\t\treturn (-ENOMEM);\n+\t\t}\n+\n+\t\tdma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(mbuf));\n+\n+\t\trxd = &rxq->rxds[i];\n+\t\trxd->fld.dd = 0;\n+\t\trxd->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;\n+\t\trxd->fld.dma_addr_lo = dma_addr & 0xffffffff;\n+\t\trxe[i].mbuf = mbuf;\n+\t\tPMD_RX_LOG(DEBUG, \"[%d]: %\" PRIx64 \"\\n\", i, dma_addr);\n+\n+\t\trxq->wr_p++;\n+\t}\n+\n+\t/* Make sure all writes are flushed before telling the hardware */\n+\trte_wmb();\n+\n+\t/* Not advertising the whole ring as the firmware gets confused if so */\n+\tPMD_RX_LOG(DEBUG, \"Increment FL write pointer in %u\\n\",\n+\t\t   rxq->rx_count - 1);\n+\n+\tnfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, rxq->rx_count - 1);\n+\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n+\t\t       uint16_t nb_desc, unsigned int socket_id,\n+\t\t       const struct rte_eth_txconf *tx_conf)\n+{\n+\tconst struct rte_memzone *tz;\n+\tstruct nfp_net_txq *txq;\n+\tuint16_t tx_free_thresh;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Validating number of descriptors */\n+\tif (((nb_desc * sizeof(struct nfp_net_tx_desc)) % 128) != 0 ||\n+\t    (nb_desc > NFP_NET_MAX_TX_DESC) ||\n+\t    (nb_desc < NFP_NET_MIN_TX_DESC)) {\n+\t\tRTE_LOG(ERR, PMD, \"Wrong nb_desc value\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n+\t\t\t\t    tx_conf->tx_free_thresh :\n+\t\t\t\t    DEFAULT_TX_FREE_THRESH);\n+\n+\tif (tx_free_thresh > (nb_desc)) {\n+\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\"tx_free_thresh must be less than the number of TX \"\n+\t\t\t\"descriptors. (tx_free_thresh=%u port=%d \"\n+\t\t\t\"queue=%d)\\n\", (unsigned int)tx_free_thresh,\n+\t\t\t(int)dev->data->port_id, (int)queue_idx);\n+\t\treturn -(EINVAL);\n+\t}\n+\n+\t/*\n+\t * Free memory prior to re-allocation if needed. This is the case after\n+\t * calling nfp_net_stop\n+\t */\n+\tif (dev->data->tx_queues[queue_idx]) {\n+\t\tPMD_TX_LOG(DEBUG, \"Freeing memory prior to re-allocation %d\\n\",\n+\t\t\t   queue_idx);\n+\t\tnfp_net_tx_queue_release(dev->data->tx_queues[queue_idx]);\n+\t\tdev->data->tx_queues[queue_idx] = NULL;\n+\t}\n+\n+\t/* Allocating tx queue data structure */\n+\ttxq = rte_zmalloc_socket(\"ethdev TX queue\", sizeof(struct nfp_net_txq),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"Error allocating tx dma\\n\");\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\t/*\n+\t * Allocate TX ring hardware descriptors. A memzone large enough to\n+\t * handle the maximum ring size is allocated in order to allow for\n+\t * resizing in later calls to the queue setup function.\n+\t */\n+\ttz = ring_dma_zone_reserve(dev, \"tx_ring\", queue_idx,\n+\t\t\t\t   sizeof(struct nfp_net_tx_desc) *\n+\t\t\t\t   NFP_NET_MAX_TX_DESC, socket_id);\n+\tif (tz == NULL) {\n+\t\tRTE_LOG(ERR, PMD, \"Error allocating tx dma\\n\");\n+\t\tnfp_net_tx_queue_release(txq);\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\ttxq->tx_count = nb_desc;\n+\ttxq->tx_free_thresh = tx_free_thresh;\n+\ttxq->tx_pthresh = tx_conf->tx_thresh.pthresh;\n+\ttxq->tx_hthresh = tx_conf->tx_thresh.hthresh;\n+\ttxq->tx_wthresh = tx_conf->tx_thresh.wthresh;\n+\n+\t/* queue mapping based on firmware configuration */\n+\ttxq->qidx = queue_idx;\n+\ttxq->tx_qcidx = queue_idx * hw->stride_tx;\n+\ttxq->qcp_q = hw->tx_bar + NFP_QCP_QUEUE_OFF(txq->tx_qcidx);\n+\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->txq_flags = tx_conf->txq_flags;\n+\n+\t/* Saving physical and virtual addresses for the TX ring */\n+\ttxq->dma = (uint64_t)tz->phys_addr;\n+\ttxq->txds = (struct nfp_net_tx_desc *)tz->addr;\n+\n+\t/* mbuf pointers array for referencing mbufs linked to TX descriptors */\n+\ttxq->txbufs = rte_zmalloc_socket(\"txq->txbufs\",\n+\t\t\t\t\t sizeof(*txq->txbufs) * nb_desc,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->txbufs == NULL) {\n+\t\tnfp_net_tx_queue_release(txq);\n+\t\treturn (-ENOMEM);\n+\t}\n+\tPMD_TX_LOG(DEBUG, \"txbufs=%p hw_ring=%p dma_addr=0x%\" PRIx64 \"\\n\",\n+\t\t   txq->txbufs, txq->txds, (unsigned long int)txq->dma);\n+\n+\tnfp_net_reset_tx_queue(txq);\n+\n+\tdev->data->tx_queues[queue_idx] = txq;\n+\ttxq->hw = hw;\n+\n+\t/*\n+\t * Telling the HW about the physical address of the TX ring and number\n+\t * of descriptors in log2 format\n+\t */\n+\tnn_cfg_writeq(hw, NFP_NET_CFG_TXR_ADDR(queue_idx), txq->dma);\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_TXR_SZ(queue_idx), log2(nb_desc));\n+\n+\treturn 0;\n+}\n+\n+/* nfp_net_tx_cksum - Set TX CSUM offload flags in TX descriptor */\n+static inline void\n+nfp_net_tx_cksum(struct nfp_net_txq *txq, struct nfp_net_tx_desc *txd,\n+\t\t struct rte_mbuf *mb)\n+{\n+\tuint16_t ol_flags;\n+\tstruct nfp_net_hw *hw = txq->hw;\n+\n+\tif (!(hw->cap & NFP_NET_CFG_CTRL_TXCSUM))\n+\t\treturn;\n+\n+\tol_flags = mb->ol_flags;\n+\n+\t/* IPv6 does not need checksum */\n+\tif (ol_flags & PKT_TX_IP_CKSUM)\n+\t\ttxd->flags |= PCIE_DESC_TX_IP4_CSUM;\n+\n+\tswitch (ol_flags & PKT_TX_L4_MASK) {\n+\tcase PKT_TX_UDP_CKSUM:\n+\t\ttxd->flags |= PCIE_DESC_TX_UDP_CSUM;\n+\t\tbreak;\n+\tcase PKT_TX_TCP_CKSUM:\n+\t\ttxd->flags |= PCIE_DESC_TX_TCP_CSUM;\n+\t\tbreak;\n+\t}\n+\n+\ttxd->flags |= PCIE_DESC_TX_CSUM;\n+}\n+\n+/* nfp_net_rx_cksum - set mbuf checksum flags based on RX descriptor flags */\n+static inline void\n+nfp_net_rx_cksum(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,\n+\t\t struct rte_mbuf *mb)\n+{\n+\tstruct nfp_net_hw *hw = rxq->hw;\n+\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RXCSUM))\n+\t\treturn;\n+\n+\t/* If IPv4 and IP checksum error, fail */\n+\tif ((rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM) &&\n+\t    !(rxd->rxd.flags & PCIE_DESC_RX_IP4_CSUM_OK))\n+\t\tmb->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n+\n+\t/* If neither UDP nor TCP return */\n+\tif (!(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&\n+\t    !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM))\n+\t\treturn;\n+\n+\tif ((rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM) &&\n+\t    !(rxd->rxd.flags & PCIE_DESC_RX_TCP_CSUM_OK))\n+\t\tmb->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n+\n+\tif ((rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM) &&\n+\t    !(rxd->rxd.flags & PCIE_DESC_RX_UDP_CSUM_OK))\n+\t\tmb->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n+}\n+\n+#define NFP_HASH_OFFSET      ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 4)\n+#define NFP_HASH_TYPE_OFFSET ((uint8_t *)mbuf->buf_addr + mbuf->data_off - 8)\n+\n+/*\n+ * nfp_net_set_hash - Set mbuf hash data\n+ *\n+ * The RSS hash and hash-type are pre-pended to the packet data.\n+ * Extract and decode it and set the mbuf fields.\n+ */\n+static inline void\n+nfp_net_set_hash(struct nfp_net_rxq *rxq, struct nfp_net_rx_desc *rxd,\n+\t\t struct rte_mbuf *mbuf)\n+{\n+\tuint32_t hash;\n+\tuint32_t hash_type;\n+\tstruct nfp_net_hw *hw = rxq->hw;\n+\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))\n+\t\treturn;\n+\n+\tif (!(rxd->rxd.flags & PCIE_DESC_RX_RSS))\n+\t\treturn;\n+\n+\thash = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_OFFSET);\n+\thash_type = rte_be_to_cpu_32(*(uint32_t *)NFP_HASH_TYPE_OFFSET);\n+\n+\t/*\n+\t * hash type is sharing the same word with input port info\n+\t * 31-8: input port\n+\t * 7:0: hash type\n+\t */\n+\thash_type &= 0xff;\n+\tmbuf->hash.rss = hash;\n+\tmbuf->ol_flags |= PKT_RX_RSS_HASH;\n+\n+\tswitch (hash_type) {\n+\tcase NFP_NET_RSS_IPV4:\n+\t\tmbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV4;\n+\t\tbreak;\n+\tcase NFP_NET_RSS_IPV6:\n+\t\tmbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6;\n+\t\tbreak;\n+\tcase NFP_NET_RSS_IPV6_EX:\n+\t\tmbuf->packet_type |= RTE_PTYPE_INNER_L3_IPV6_EXT;\n+\t\tbreak;\n+\tdefault:\n+\t\tmbuf->packet_type |= RTE_PTYPE_INNER_L4_MASK;\n+\t}\n+}\n+\n+/* nfp_net_check_port - Set mbuf in_port field */\n+static void\n+nfp_net_check_port(struct nfp_net_rx_desc *rxd, struct rte_mbuf *mbuf)\n+{\n+\tuint32_t port;\n+\n+\tif (!(rxd->rxd.flags & PCIE_DESC_RX_INGRESS_PORT)) {\n+\t\tmbuf->port = 0;\n+\t\treturn;\n+\t}\n+\n+\tport = rte_be_to_cpu_32(*(uint32_t *)((uint8_t *)mbuf->buf_addr +\n+\t\t\t\t\t      mbuf->data_off - 8));\n+\n+\t/*\n+\t * hash type is sharing the same word with input port info\n+\t * 31-8: input port\n+\t * 7:0: hash type\n+\t */\n+\tport = (uint8_t)(port >> 8);\n+\tmbuf->port = port;\n+}\n+\n+static inline void\n+nfp_net_mbuf_alloc_failed(struct nfp_net_rxq *rxq)\n+{\n+\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n+}\n+\n+#define NFP_DESC_META_LEN(d) (d->rxd.meta_len_dd & PCIE_DESC_RX_META_LEN_MASK)\n+\n+/*\n+ * RX path design:\n+ *\n+ * There are some decissions to take:\n+ * 1) How to check DD RX descriptors bit\n+ * 2) How and when to allocate new mbufs\n+ *\n+ * Current implementation checks just one single DD bit each loop. As each\n+ * descriptor is 8 bytes, it is likely a good idea to check descriptors in\n+ * a single cache line instead. Tests with this change have not shown any\n+ * performance improvement but it requires further investigation. For example,\n+ * depending on which descriptor is next, the number of descriptors could be\n+ * less than 8 for just checking those in the same cache line. This implies\n+ * extra work which could be counterproductive by itself. Indeed, last firmware\n+ * changes are just doing this: writing several descriptors with the DD bit\n+ * for saving PCIe bandwidth and DMA operations from the NFP.\n+ *\n+ * Mbuf allocation is done when a new packet is received. Then the descriptor\n+ * is automatically linked with the new mbuf and the old one is given to the\n+ * user. The main drawback with this design is mbuf allocation is heavier than\n+ * using bulk allocations allowed by DPDK with rte_mempool_get_bulk. From the\n+ * cache point of view it does not seem allocating the mbuf early on as we are\n+ * doing now have any benefit at all. Again, tests with this change have not\n+ * shown any improvement. Also, rte_mempool_get_bulk returns all or nothing\n+ * so looking at the implications of this type of allocation should be studied\n+ * deeply\n+ */\n+\n+static uint16_t\n+nfp_net_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct nfp_net_rxq *rxq;\n+\tstruct nfp_net_rx_desc *rxds;\n+\tstruct nfp_net_rx_buff *rxb;\n+\tstruct nfp_net_hw *hw;\n+\tstruct rte_mbuf *mb;\n+\tstruct rte_mbuf *new_mb;\n+\tint idx;\n+\tuint16_t nb_hold;\n+\tuint64_t dma_addr;\n+\tint avail;\n+\n+\trxq = rx_queue;\n+\tif (unlikely(rxq == NULL)) {\n+\t\t/*\n+\t\t * DPDK just checks the queue is lower than max queues\n+\t\t * enabled. But the queue needs to be configured\n+\t\t */\n+\t\tRTE_LOG(ERR, PMD, \"RX Bad queue\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\thw = rxq->hw;\n+\tavail = 0;\n+\tnb_hold = 0;\n+\n+\twhile (avail < nb_pkts) {\n+\t\tidx = rxq->rd_p % rxq->rx_count;\n+\n+\t\trxb = &rxq->rxbufs[idx];\n+\t\tif (unlikely(rxb == NULL)) {\n+\t\t\tRTE_LOG(ERR, PMD, \"rxb does not exist!\\n\");\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/*\n+\t\t * Memory barrier to ensure that we won't do other\n+\t\t * reads before the DD bit.\n+\t\t */\n+\t\trte_rmb();\n+\n+\t\trxds = &rxq->rxds[idx];\n+\t\tif ((rxds->rxd.meta_len_dd & PCIE_DESC_RX_DD) == 0)\n+\t\t\tbreak;\n+\n+\t\t/*\n+\t\t * We got a packet. Let's alloc a new mbuff for refilling the\n+\t\t * free descriptor ring as soon as possible\n+\t\t */\n+\t\tnew_mb = rte_pktmbuf_alloc(rxq->mem_pool);\n+\t\tif (unlikely(new_mb == NULL)) {\n+\t\t\tRTE_LOG(DEBUG, PMD, \"RX mbuf alloc failed port_id=%u \"\n+\t\t\t\t\"queue_id=%u\\n\", (unsigned)rxq->port_id,\n+\t\t\t\t(unsigned)rxq->qidx);\n+\t\t\tnfp_net_mbuf_alloc_failed(rxq);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tnb_hold++;\n+\n+\t\t/*\n+\t\t * Grab the mbuff and refill the descriptor with the\n+\t\t * previously allocated mbuff\n+\t\t */\n+\t\tmb = rxb->mbuf;\n+\t\trxb->mbuf = new_mb;\n+\n+\t\tPMD_RX_LOG(DEBUG, \"Packet len: %u, mbuf_size: %u\\n\",\n+\t\t\t   rxds->rxd.data_len, rxq->mbuf_size);\n+\n+\t\t/* Size of this segment */\n+\t\tmb->data_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);\n+\t\t/* Size of the whole packet. We just support 1 segment */\n+\t\tmb->pkt_len = rxds->rxd.data_len - NFP_DESC_META_LEN(rxds);\n+\n+\t\tif (unlikely((mb->data_len + NFP_NET_RX_OFFSET) >\n+\t\t\t     rxq->mbuf_size)) {\n+\t\t\t/*\n+\t\t\t * This should not happen and the user has the\n+\t\t\t * responsibility of avoiding it. But we have\n+\t\t\t * to give some info about the error\n+\t\t\t */\n+\t\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\t\"mbuf overflow likely due to NFP_NET_RX_OFFSET\\n\"\n+\t\t\t\t\"\\t\\tYour mbuf size should have extra space for\"\n+\t\t\t\t\" NFP_NET_RX_OFFSET=%u bytes.\\n\"\n+\t\t\t\t\"\\t\\tCurrently you just have %u bytes available\"\n+\t\t\t\t\" but the received packet is %u bytes long\",\n+\t\t\t\tNFP_NET_RX_OFFSET,\n+\t\t\t\trxq->mbuf_size - NFP_NET_RX_OFFSET,\n+\t\t\t\tmb->data_len);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t/* Filling the received mbuff with packet info */\n+\t\tmb->data_off = RTE_PKTMBUF_HEADROOM + NFP_NET_RX_OFFSET;\n+\n+\t\t/* No scatter mode supported */\n+\t\tmb->nb_segs = 1;\n+\t\tmb->next = NULL;\n+\n+\t\t/* Checking the RSS flag */\n+\t\tnfp_net_set_hash(rxq, rxds, mb);\n+\n+\t\t/* Checking the checksum flag */\n+\t\tnfp_net_rx_cksum(rxq, rxds, mb);\n+\n+\t\t/* Checking the port flag */\n+\t\tnfp_net_check_port(rxds, mb);\n+\n+\t\tif ((rxds->rxd.flags & PCIE_DESC_RX_VLAN) &&\n+\t\t    (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN)) {\n+\t\t\tmb->vlan_tci = rte_cpu_to_le_32(rxds->rxd.vlan);\n+\t\t\tmb->ol_flags |= PKT_RX_VLAN_PKT;\n+\t\t}\n+\n+\t\t/* Adding the mbuff to the mbuff array passed by the app */\n+\t\trx_pkts[avail++] = mb;\n+\n+\t\t/* Now resetting and updating the descriptor */\n+\t\trxds->vals[0] = 0;\n+\t\trxds->vals[1] = 0;\n+\t\tdma_addr = rte_cpu_to_le_64(RTE_MBUF_DMA_ADDR_DEFAULT(new_mb));\n+\t\trxds->fld.dd = 0;\n+\t\trxds->fld.dma_addr_hi = (dma_addr >> 32) & 0xff;\n+\t\trxds->fld.dma_addr_lo = dma_addr & 0xffffffff;\n+\n+\t\trxq->rd_p++;\n+\t}\n+\n+\tif (nb_hold == 0)\n+\t\treturn nb_hold;\n+\n+\tPMD_RX_LOG(DEBUG, \"RX  port_id=%u queue_id=%u, %d packets received\\n\",\n+\t\t   (unsigned)rxq->port_id, (unsigned)rxq->qidx, nb_hold);\n+\n+\tnb_hold += rxq->nb_rx_hold;\n+\n+\t/*\n+\t * FL descriptors needs to be written before incrementing the\n+\t * FL queue WR pointer\n+\t */\n+\trte_wmb();\n+\tif (nb_hold > rxq->rx_free_thresh) {\n+\t\tPMD_RX_LOG(DEBUG, \"port=%u queue=%u nb_hold=%u avail=%u\\n\",\n+\t\t\t   (unsigned)rxq->port_id, (unsigned)rxq->qidx,\n+\t\t\t   (unsigned)nb_hold, (unsigned)avail);\n+\t\tnfp_qcp_ptr_add(rxq->qcp_fl, NFP_QCP_WRITE_PTR, nb_hold);\n+\t\tnb_hold = 0;\n+\t}\n+\trxq->nb_rx_hold = nb_hold;\n+\n+\treturn avail;\n+}\n+\n+/*\n+ * nfp_net_tx_free_bufs - Check for descriptors with a complete\n+ * status\n+ * @txq: TX queue to work with\n+ * Returns number of descriptors freed\n+ */\n+int\n+nfp_net_tx_free_bufs(struct nfp_net_txq *txq)\n+{\n+\t__u32 qcp_rd_p;\n+\tint todo;\n+\n+\tPMD_TX_LOG(DEBUG, \"queue %u. Check for descriptor with a complete\"\n+\t\t   \" status\\n\", txq->qidx);\n+\n+\t/* Work out how many packets have been sent */\n+\tqcp_rd_p = nfp_qcp_read(txq->qcp_q, NFP_QCP_READ_PTR);\n+\n+\tif (qcp_rd_p == txq->qcp_rd_p) {\n+\t\tPMD_TX_LOG(DEBUG, \"queue %u: It seems harrier is not sending \"\n+\t\t\t   \"packets (%u, %u)\\n\", txq->qidx,\n+\t\t\t   qcp_rd_p, txq->qcp_rd_p);\n+\t\treturn 0;\n+\t}\n+\n+\tif (qcp_rd_p > txq->qcp_rd_p)\n+\t\ttodo = qcp_rd_p - txq->qcp_rd_p;\n+\telse\n+\t\ttodo = qcp_rd_p + txq->tx_count - txq->qcp_rd_p;\n+\n+\tPMD_TX_LOG(DEBUG, \"qcp_rd_p %u, txq->qcp_rd_p: %u, qcp->rd_p: %u\\n\",\n+\t\t   qcp_rd_p, txq->qcp_rd_p, txq->rd_p);\n+\n+\tif (todo == 0)\n+\t\treturn todo;\n+\n+\ttxq->qcp_rd_p += todo;\n+\ttxq->qcp_rd_p %= txq->tx_count;\n+\ttxq->rd_p += todo;\n+\n+\treturn todo;\n+}\n+\n+/* Leaving always free descriptors for avoiding wrapping confusion */\n+#define NFP_FREE_TX_DESC(t) (t->tx_count - (t->wr_p - t->rd_p) - 8)\n+\n+/*\n+ * nfp_net_txq_full - Check if the TX queue free descriptors\n+ * is below tx_free_threshold\n+ *\n+ * @txq: TX queue to check\n+ *\n+ * This function uses the host copy* of read/write pointers\n+ */\n+static inline\n+int nfp_net_txq_full(struct nfp_net_txq *txq)\n+{\n+\treturn NFP_FREE_TX_DESC(txq) < txq->tx_free_thresh;\n+}\n+\n+static uint16_t\n+nfp_net_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct nfp_net_txq *txq;\n+\tstruct nfp_net_hw *hw;\n+\tstruct nfp_net_tx_desc *txds;\n+\tstruct rte_mbuf *pkt;\n+\tuint64_t dma_addr;\n+\tint pkt_size, dma_size;\n+\tuint16_t free_descs, issued_descs;\n+\tstruct rte_mbuf **lmbuf;\n+\tint i;\n+\n+\ttxq = tx_queue;\n+\thw = txq->hw;\n+\ttxds = &txq->txds[txq->tail];\n+\n+\tPMD_TX_LOG(DEBUG, \"working for queue %u at pos %d and %u packets\\n\",\n+\t\t   txq->qidx, wr_idx, nb_pkts);\n+\n+\tif ((NFP_FREE_TX_DESC(txq) < nb_pkts) || (nfp_net_txq_full(txq)))\n+\t\tnfp_net_tx_free_bufs(txq);\n+\n+\tfree_descs = (uint16_t)NFP_FREE_TX_DESC(txq);\n+\tif (unlikely(free_descs == 0))\n+\t\treturn 0;\n+\n+\tpkt = *tx_pkts;\n+\n+\ti = 0;\n+\tissued_descs = 0;\n+\tPMD_TX_LOG(DEBUG, \"queue: %u. Sending %u packets\\n\",\n+\t\t   txq->qidx, nb_pkts);\n+\t/* Sending packets */\n+\twhile ((i < nb_pkts) && free_descs) {\n+\t\t/* Grabbing the mbuf linked to the current descriptor */\n+\t\tlmbuf = &txq->txbufs[txq->tail].mbuf;\n+\t\t/* Warming the cache for releasing the mbuf later on */\n+\t\tRTE_MBUF_PREFETCH_TO_FREE(*lmbuf);\n+\n+\t\tpkt = *(tx_pkts + i);\n+\n+\t\tif (unlikely((pkt->nb_segs > 1) &&\n+\t\t\t     !(hw->cap & NFP_NET_CFG_CTRL_GATHER))) {\n+\t\t\tPMD_INIT_LOG(INFO, \"NFP_NET_CFG_CTRL_GATHER not set\\n\");\n+\t\t\trte_panic(\"Multisegment packet unsupported\\n\");\n+\t\t}\n+\n+\t\t/* Checking if we have enough descriptors */\n+\t\tif (unlikely(pkt->nb_segs > free_descs))\n+\t\t\tgoto xmit_end;\n+\n+\t\t/*\n+\t\t * Checksum and VLAN flags just in the first descriptor for a\n+\t\t * multisegment packet\n+\t\t */\n+\t\tnfp_net_tx_cksum(txq, txds, pkt);\n+\n+\t\tif ((pkt->ol_flags & PKT_TX_VLAN_PKT) &&\n+\t\t    (hw->cap & NFP_NET_CFG_CTRL_TXVLAN)) {\n+\t\t\ttxds->flags |= PCIE_DESC_TX_VLAN;\n+\t\t\ttxds->vlan = pkt->vlan_tci;\n+\t\t}\n+\n+\t\tif (pkt->ol_flags & PKT_TX_TCP_SEG)\n+\t\t\trte_panic(\"TSO is not supported\\n\");\n+\n+\t\t/*\n+\t\t * mbuf data_len is the data in one segment and pkt_len data\n+\t\t * in the whole packet. When the packet is just one segment,\n+\t\t * then data_len = pkt_len\n+\t\t */\n+\t\tpkt_size = pkt->pkt_len;\n+\n+\t\twhile (pkt_size) {\n+\t\t\t/* Releasing mbuf which was prefetched above */\n+\t\t\tif (*lmbuf)\n+\t\t\t\trte_pktmbuf_free_seg(*lmbuf);\n+\n+\t\t\tdma_size = pkt->data_len;\n+\t\t\tdma_addr = RTE_MBUF_DATA_DMA_ADDR(pkt);\n+\t\t\tPMD_TX_LOG(DEBUG, \"Working with mbuf at dma address:\"\n+\t\t\t\t   \"%\" PRIx64 \"\\n\", dma_addr);\n+\n+\t\t\t/* Filling descriptors fields */\n+\t\t\ttxds->dma_len = dma_size;\n+\t\t\ttxds->data_len = pkt->pkt_len;\n+\t\t\ttxds->dma_addr_hi = (dma_addr >> 32) & 0xff;\n+\t\t\ttxds->dma_addr_lo = (dma_addr & 0xffffffff);\n+\t\t\tASSERT(free_descs > 0);\n+\t\t\tfree_descs--;\n+\n+\t\t\t/*\n+\t\t\t * Linking mbuf with descriptor for being released\n+\t\t\t * next time descriptor is used\n+\t\t\t */\n+\t\t\t*lmbuf = pkt;\n+\n+\t\t\ttxq->wr_p++;\n+\t\t\ttxq->tail++;\n+\t\t\tif (unlikely(txq->tail == txq->tx_count)) /* wrapping?*/\n+\t\t\t\ttxq->tail = 0;\n+\n+\t\t\tpkt_size -= dma_size;\n+\t\t\tif (!pkt_size) {\n+\t\t\t\t/* End of packet */\n+\t\t\t\ttxds->offset_eop |= PCIE_DESC_TX_EOP;\n+\t\t\t} else {\n+\t\t\t\ttxds->offset_eop &= PCIE_DESC_TX_OFFSET_MASK;\n+\t\t\t\tpkt = pkt->next;\n+\t\t\t}\n+\t\t\t/* Referencing next free TX descriptor */\n+\t\t\ttxds = &txq->txds[txq->tail];\n+\t\t\tissued_descs++;\n+\t\t}\n+\t\ti++;\n+\t}\n+\n+xmit_end:\n+\t/* Increment write pointers. Force memory write before we let HW know */\n+\trte_wmb();\n+\tnfp_qcp_ptr_add(txq->qcp_q, NFP_QCP_WRITE_PTR, issued_descs);\n+\n+\treturn i;\n+}\n+\n+static void\n+nfp_net_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n+{\n+\tuint32_t new_ctrl, update;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tnew_ctrl = 0;\n+\n+\tif ((mask & ETH_VLAN_FILTER_OFFLOAD) ||\n+\t    (mask & ETH_VLAN_FILTER_OFFLOAD))\n+\t\tRTE_LOG(INFO, PMD, \"Not support for ETH_VLAN_FILTER_OFFLOAD or\"\n+\t\t\t\" ETH_VLAN_FILTER_EXTEND\");\n+\n+\t/* Enable vlan strip if it is not configured yet */\n+\tif ((mask & ETH_VLAN_STRIP_OFFLOAD) &&\n+\t    !(hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))\n+\t\tnew_ctrl = hw->ctrl | NFP_NET_CFG_CTRL_RXVLAN;\n+\n+\t/* Disable vlan strip just if it is configured */\n+\tif (!(mask & ETH_VLAN_STRIP_OFFLOAD) &&\n+\t    (hw->ctrl & NFP_NET_CFG_CTRL_RXVLAN))\n+\t\tnew_ctrl = hw->ctrl & ~NFP_NET_CFG_CTRL_RXVLAN;\n+\n+\tif (new_ctrl == 0)\n+\t\treturn;\n+\n+\tupdate = NFP_NET_CFG_UPDATE_GEN;\n+\n+\tif (nfp_net_reconfig(hw, new_ctrl, update) < 0)\n+\t\treturn;\n+\n+\thw->ctrl = new_ctrl;\n+}\n+\n+/* Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device */\n+static int\n+nfp_net_reta_update(struct rte_eth_dev *dev,\n+\t\t    struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t    uint16_t reta_size)\n+{\n+\tuint32_t reta, mask;\n+\tint i, j;\n+\tint idx, shift;\n+\tuint32_t update;\n+\tstruct nfp_net_hw *hw =\n+\t\tNFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))\n+\t\treturn -EINVAL;\n+\n+\tif (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {\n+\t\tRTE_LOG(ERR, PMD, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\\n\", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Update Redirection Table. There are 128 8bit-entries which can be\n+\t * manage as 32 32bit-entries\n+\t */\n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\t/* Handling 4 RSS entries per loop */\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);\n+\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\treta = 0;\n+\t\t/* If all 4 entries were set, don't need read RETA register */\n+\t\tif (mask != 0xF)\n+\t\t\treta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + i);\n+\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (!(mask & (0x1 << j)))\n+\t\t\t\tcontinue;\n+\t\t\tif (mask != 0xF)\n+\t\t\t\t/* Clearing the entry bits */\n+\t\t\t\treta &= ~(0xFF << (8 * j));\n+\t\t\treta |= reta_conf[idx].reta[shift + j] << (8 * j);\n+\t\t}\n+\t\tnn_cfg_writel(hw, NFP_NET_CFG_RSS_ITBL + shift, reta);\n+\t}\n+\n+\tupdate = NFP_NET_CFG_UPDATE_RSS;\n+\n+\tif (nfp_net_reconfig(hw, hw->ctrl, update) < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+ /* Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device. */\n+static int\n+nfp_net_reta_query(struct rte_eth_dev *dev,\n+\t\t   struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t   uint16_t reta_size)\n+{\n+\tuint8_t i, j, mask;\n+\tint idx, shift;\n+\tuint32_t reta;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))\n+\t\treturn -EINVAL;\n+\n+\tif (reta_size != NFP_NET_CFG_RSS_ITBL_SZ) {\n+\t\tRTE_LOG(ERR, PMD, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\\n\", reta_size, NFP_NET_CFG_RSS_ITBL_SZ);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Reading Redirection Table. There are 128 8bit-entries which can be\n+\t * manage as 32 32bit-entries\n+\t */\n+\tfor (i = 0; i < reta_size; i += 4) {\n+\t\t/* Handling 4 RSS entries per loop */\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) & 0xF);\n+\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\treta = nn_cfg_readl(hw, NFP_NET_CFG_RSS_ITBL + shift);\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (!(mask & (0x1 << j)))\n+\t\t\t\tcontinue;\n+\t\t\treta_conf->reta[shift + j] =\n+\t\t\t\t(uint8_t)((reta >> (8 * j)) & 0xF);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_conf *rss_conf)\n+{\n+\tuint32_t update;\n+\tuint32_t cfg_rss_ctrl = 0;\n+\tuint8_t key;\n+\tuint64_t rss_hf;\n+\tint i;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\trss_hf = rss_conf->rss_hf;\n+\n+\t/* Checking if RSS is enabled */\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS)) {\n+\t\tif (rss_hf != 0) { /* Enable RSS? */\n+\t\t\tRTE_LOG(ERR, PMD, \"RSS unsupported\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\treturn 0; /* Nothing to do */\n+\t}\n+\n+\tif (rss_conf->rss_key_len > NFP_NET_CFG_RSS_KEY_SZ) {\n+\t\tRTE_LOG(ERR, PMD, \"hash key too long\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (rss_hf & ETH_RSS_IPV4)\n+\t\tcfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV4 |\n+\t\t\t\tNFP_NET_CFG_RSS_IPV4_TCP |\n+\t\t\t\tNFP_NET_CFG_RSS_IPV4_UDP;\n+\n+\tif (rss_hf & ETH_RSS_IPV6)\n+\t\tcfg_rss_ctrl |= NFP_NET_CFG_RSS_IPV6 |\n+\t\t\t\tNFP_NET_CFG_RSS_IPV6_TCP |\n+\t\t\t\tNFP_NET_CFG_RSS_IPV6_UDP;\n+\n+\t/* configuring where to apply the RSS hash */\n+\tnn_cfg_writel(hw, NFP_NET_CFG_RSS_CTRL, cfg_rss_ctrl);\n+\n+\t/* Writing the key byte a byte */\n+\tfor (i = 0; i < rss_conf->rss_key_len; i++) {\n+\t\tmemcpy(&key, &rss_conf->rss_key[i], 1);\n+\t\tnn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY + i, key);\n+\t}\n+\n+\t/* Writing the key size */\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_RSS_KEY_SZ, rss_conf->rss_key_len);\n+\n+\tupdate = NFP_NET_CFG_UPDATE_RSS;\n+\n+\tif (nfp_net_reconfig(hw, hw->ctrl, update) < 0)\n+\t\treturn -EIO;\n+\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\t  struct rte_eth_rss_conf *rss_conf)\n+{\n+\tuint64_t rss_hf;\n+\tuint32_t cfg_rss_ctrl;\n+\tuint8_t key;\n+\tint i;\n+\tstruct nfp_net_hw *hw;\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (!(hw->ctrl & NFP_NET_CFG_CTRL_RSS))\n+\t\treturn -EINVAL;\n+\n+\trss_hf = rss_conf->rss_hf;\n+\tcfg_rss_ctrl = nn_cfg_readl(hw, NFP_NET_CFG_RSS_CTRL);\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP;\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_TCP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_TCP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV4_UDP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6_UDP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;\n+\n+\tif (cfg_rss_ctrl & NFP_NET_CFG_RSS_IPV6)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP;\n+\n+\t/* Reading the key size */\n+\trss_conf->rss_key_len = nn_cfg_readl(hw, NFP_NET_CFG_RSS_KEY_SZ);\n+\n+\t/* Reading the key byte a byte */\n+\tfor (i = 0; i < rss_conf->rss_key_len; i++) {\n+\t\tkey = nn_cfg_readb(hw, NFP_NET_CFG_RSS_KEY + i);\n+\t\tmemcpy(&rss_conf->rss_key[i], &key, 1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Initialise and register driver with DPDK Application */\n+static struct eth_dev_ops nfp_net_eth_dev_ops = {\n+\t.dev_configure\t\t= nfp_net_configure,\n+\t.dev_start\t\t= nfp_net_start,\n+\t.dev_stop\t\t= nfp_net_stop,\n+\t.dev_close\t\t= nfp_net_close,\n+\t.promiscuous_enable\t= nfp_net_promisc_enable,\n+\t.promiscuous_disable\t= nfp_net_promisc_disable,\n+\t.link_update\t\t= nfp_net_link_update,\n+\t.stats_get\t\t= nfp_net_stats_get,\n+\t.stats_reset\t\t= nfp_net_stats_reset,\n+\t.dev_infos_get\t\t= nfp_net_infos_get,\n+\t.mtu_set\t\t= nfp_net_dev_mtu_set,\n+\t.vlan_offload_set\t= nfp_net_vlan_offload_set,\n+\t.reta_update\t\t= nfp_net_reta_update,\n+\t.reta_query\t\t= nfp_net_reta_query,\n+\t.rss_hash_update\t= nfp_net_rss_hash_update,\n+\t.rss_hash_conf_get\t= nfp_net_rss_hash_conf_get,\n+\t.rx_queue_setup\t\t= nfp_net_rx_queue_setup,\n+\t.rx_queue_release\t= nfp_net_rx_queue_release,\n+\t.rx_queue_count\t\t= nfp_net_rx_queue_count,\n+\t.tx_queue_setup\t\t= nfp_net_tx_queue_setup,\n+\t.tx_queue_release\t= nfp_net_tx_queue_release,\n+\t.mac_addr_add\t\t= NULL,\n+\t.mac_addr_remove\t= NULL,\n+};\n+\n+static int\n+__nfp_net_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct nfp_net_hw *hw;\n+\n+\tuint32_t tx_bar_off, rx_bar_off;\n+\tuint32_t start_q;\n+\tint stride = 4;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\thw = NFP_NET_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n+\n+\teth_dev->dev_ops = &nfp_net_eth_dev_ops;\n+\teth_dev->rx_pkt_burst = &nfp_net_recv_pkts;\n+\teth_dev->tx_pkt_burst = &nfp_net_xmit_pkts;\n+\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tpci_dev = eth_dev->pci_dev;\n+\thw->device_id = pci_dev->id.device_id;\n+\thw->vendor_id = pci_dev->id.vendor_id;\n+\thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n+\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n+\n+\tPMD_INIT_LOG(DEBUG, \"nfp_net: device (%u:%u) %u:%u:%u:%u\\n\",\n+\t\t     pci_dev->id.vendor_id, pci_dev->id.device_id,\n+\t\t     pci_dev->addr.domain, pci_dev->addr.bus,\n+\t\t     pci_dev->addr.devid, pci_dev->addr.function);\n+\n+\thw->ctrl_bar = (uint8_t *)pci_dev->mem_resource[0].addr;\n+\tif (hw->ctrl_bar == NULL) {\n+\t\tRTE_LOG(ERR, PMD,\n+\t\t\t\"hw->ctrl_bar is NULL. BAR0 not configured\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\thw->max_rx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_RXRINGS);\n+\thw->max_tx_queues = nn_cfg_readl(hw, NFP_NET_CFG_MAX_TXRINGS);\n+\n+\t/* Work out where in the BAR the queues start. */\n+\tswitch (pci_dev->id.device_id) {\n+\tcase PCI_DEVICE_ID_NFP6000_VF_NIC:\n+\t\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_TXQ);\n+\t\ttx_bar_off = NFP_PCIE_QUEUE(start_q);\n+\t\tstart_q = nn_cfg_readl(hw, NFP_NET_CFG_START_RXQ);\n+\t\trx_bar_off = NFP_PCIE_QUEUE(start_q);\n+\t\tbreak;\n+\tdefault:\n+\t\tRTE_LOG(ERR, PMD, \"nfp_net: no device ID matching\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tPMD_INIT_LOG(DEBUG, \"tx_bar_off: 0x%08x\\n\", tx_bar_off);\n+\tPMD_INIT_LOG(DEBUG, \"rx_bar_off: 0x%08x\\n\", rx_bar_off);\n+\n+\thw->tx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + tx_bar_off;\n+\thw->rx_bar = (uint8_t *)pci_dev->mem_resource[2].addr + rx_bar_off;\n+\n+\tPMD_INIT_LOG(DEBUG, \"ctrl_bar: %p, tx_bar: %p, rx_bar: %p\\n\",\n+\t\t     hw->ctrl_bar, hw->tx_bar, hw->rx_bar);\n+\n+\tnfp_net_cfg_queue_setup(hw);\n+\n+\t/* Get some of the read-only fields from the config BAR */\n+\thw->ver = nn_cfg_readl(hw, NFP_NET_CFG_VERSION);\n+\thw->cap = nn_cfg_readl(hw, NFP_NET_CFG_CAP);\n+\thw->max_mtu = nn_cfg_readl(hw, NFP_NET_CFG_MAX_MTU);\n+\thw->mtu = hw->max_mtu;\n+\n+\tPMD_INIT_LOG(INFO, \"VER: %#x, Maximum supported MTU: %d\\n\",\n+\t\t     hw->ver, hw->max_mtu);\n+\tPMD_INIT_LOG(INFO, \"CAP: %#x, %s%s%s%s%s%s%s%s%s\\n\", hw->cap,\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_PROMISC ? \"PROMISC \" : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_RXCSUM  ? \"RXCSUM \"  : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_TXCSUM  ? \"TXCSUM \"  : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_RXVLAN  ? \"RXVLAN \"  : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_TXVLAN  ? \"TXVLAN \"  : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_SCATTER ? \"SCATTER \" : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_GATHER  ? \"GATHER \"  : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_LSO     ? \"TSO \"     : \"\",\n+\t\t     hw->cap & NFP_NET_CFG_CTRL_RSS     ? \"RSS \"     : \"\");\n+\n+\tpci_dev = eth_dev->pci_dev;\n+\thw->ctrl = 0;\n+\n+\thw->stride_rx = stride;\n+\thw->stride_tx = stride;\n+\n+\tPMD_INIT_LOG(INFO, \"max_rx_queues: %u, max_tx_queues: %u\\n\",\n+\t\t     hw->max_rx_queues, hw->max_tx_queues);\n+\n+\t/* Allocating memory for mac addr */\n+\teth_dev->data->mac_addrs = rte_zmalloc(\"mac_addr\", ETHER_ADDR_LEN, 0);\n+\tif (eth_dev->data->mac_addrs == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to space for MAC address\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Using random mac addresses for VFs */\n+\teth_random_addr(&hw->mac_addr[0]);\n+\n+\t/* Copying mac address to DPDK eth_dev struct */\n+\tether_addr_copy(&eth_dev->data->mac_addrs[0],\n+\t\t\t(struct ether_addr *)hw->mac_addr);\n+\n+\tPMD_INIT_LOG(INFO, \"port %d VendorID=0x%x DeviceID=0x%x \"\n+\t\t     \"mac=%02x:%02x:%02x:%02x:%02x:%02x\",\n+\t\t     eth_dev->data->port_id, pci_dev->id.vendor_id,\n+\t\t     pci_dev->id.device_id,\n+\t\t     hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],\n+\t\t     hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);\n+\n+\t/* Registering LSC interrupt handler */\n+\trte_intr_callback_register(&pci_dev->intr_handle,\n+\t\t\t\t   nfp_net_dev_interrupt_handler,\n+\t\t\t\t   (void *)eth_dev);\n+\n+\t/* enable uio intr after callback register */\n+\trte_intr_enable(&pci_dev->intr_handle);\n+\n+\t/* Telling the firmware about the LSC interrupt entry */\n+\tnn_cfg_writeb(hw, NFP_NET_CFG_LSC, NFP_NET_IRQ_LSC_IDX);\n+\n+\t/* Recording current stats counters values */\n+\tnfp_net_stats_reset(eth_dev);\n+\n+\treturn 0;\n+}\n+\n+static int\n+nfp_net_init(struct rte_eth_dev *eth_dev)\n+{\n+\treturn __nfp_net_init(eth_dev);\n+}\n+\n+static struct rte_pci_id pci_id_nfp_net_map[] = {\n+\t{\n+\t\t.vendor_id = PCI_VENDOR_ID_NETRONOME,\n+\t\t.device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,\n+\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t.subsystem_device_id = PCI_ANY_ID,\n+\t},\n+\t{\n+\t\t.vendor_id = PCI_VENDOR_ID_NETRONOME,\n+\t\t.device_id = PCI_DEVICE_ID_NFP6000_VF_NIC,\n+\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t.subsystem_device_id = PCI_ANY_ID,\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct eth_driver rte_nfp_net_pmd = {\n+\t{\n+\t\t.name = \"rte_nfp_net_pmd\",\n+\t\t.id_table = pci_id_nfp_net_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t},\n+\t.eth_dev_init = nfp_net_init,\n+\t.dev_private_size = sizeof(struct nfp_net_adapter),\n+};\n+\n+static int\n+nfp_net_pmd_init(const char *name __rte_unused,\n+\t\t const char *params __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tPMD_INIT_LOG(INFO, \"librte_pmd_nfp_net version %s\\n\",\n+\t\t     NFP_NET_PMD_VERSION);\n+\n+\trte_eth_driver_register(&rte_nfp_net_pmd);\n+\treturn 0;\n+}\n+\n+static struct rte_driver rte_nfp_net_driver = {\n+\t.type = PMD_PDEV,\n+\t.init = nfp_net_pmd_init,\n+};\n+\n+PMD_REGISTER_DRIVER(rte_nfp_net_driver);\n+\n+/*\n+ * Local variables:\n+ * c-file-style: \"Linux\"\n+ * indent-tabs-mode: t\n+ * End:\n+ */\ndiff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h\nnew file mode 100644\nindex 0000000..8342500\n--- /dev/null\n+++ b/drivers/net/nfp/nfp_net_ctrl.h\n@@ -0,0 +1,290 @@\n+/*\n+ * Copyright (c) 2014, 2015 Netronome Systems, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *  this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *  notice, this list of conditions and the following disclaimer in the\n+ *  documentation and/or other materials provided with the distribution\n+ *\n+ * 3. Neither the name of the copyright holder nor the names of its\n+ *  contributors may be used to endorse or promote products derived from this\n+ *  software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/*\n+ * vim:shiftwidth=8:noexpandtab\n+ *\n+ * Netronome network device driver: Control BAR layout\n+ */\n+#ifndef _NFP_NET_CTRL_H_\n+#define _NFP_NET_CTRL_H_\n+\n+/*\n+ * Configuration BAR size.\n+ *\n+ * The configuration BAR is 8K in size, but on the NFP6000, due to\n+ * THB-350, 32k needs to be reserved.\n+ */\n+#ifdef __NFP_IS_6000\n+#define NFP_NET_CFG_BAR_SZ              (32 * 1024)\n+#else\n+#define NFP_NET_CFG_BAR_SZ              (8 * 1024)\n+#endif\n+\n+/* Offset in Freelist buffer where packet starts on RX */\n+#define NFP_NET_RX_OFFSET               32\n+\n+/* Hash type pre-pended when a RSS hash was computed */\n+#define NFP_NET_RSS_NONE                0\n+#define NFP_NET_RSS_IPV4                1\n+#define NFP_NET_RSS_IPV6                2\n+#define NFP_NET_RSS_IPV6_EX             3\n+#define NFP_NET_RSS_IPV4_TCP            4\n+#define NFP_NET_RSS_IPV6_TCP            5\n+#define NFP_NET_RSS_IPV6_EX_TCP         6\n+#define NFP_NET_RSS_IPV4_UDP            7\n+#define NFP_NET_RSS_IPV6_UDP            8\n+#define NFP_NET_RSS_IPV6_EX_UDP         9\n+\n+/*\n+ * @NFP_NET_TXR_MAX:         Maximum number of TX rings\n+ * @NFP_NET_TXR_MASK:        Mask for TX rings\n+ * @NFP_NET_RXR_MAX:         Maximum number of RX rings\n+ * @NFP_NET_RXR_MASK:        Mask for RX rings\n+ */\n+#define NFP_NET_TXR_MAX                 64\n+#define NFP_NET_TXR_MASK                (NFP_NET_TXR_MAX - 1)\n+#define NFP_NET_RXR_MAX                 64\n+#define NFP_NET_RXR_MASK                (NFP_NET_RXR_MAX - 1)\n+\n+/*\n+ * Read/Write config words (0x0000 - 0x002c)\n+ * @NFP_NET_CFG_CTRL:        Global control\n+ * @NFP_NET_CFG_UPDATE:      Indicate which fields are updated\n+ * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings\n+ * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings\n+ * @NFP_NET_CFG_MTU:         Set MTU size\n+ * @NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)\n+ * @NFP_NET_CFG_EXN:         MSI-X table entry for exceptions\n+ * @NFP_NET_CFG_LSC:         MSI-X table entry for link state changes\n+ * @NFP_NET_CFG_MACADDR:     MAC address\n+ *\n+ * TODO:\n+ * - define Error details in UPDATE\n+ */\n+#define NFP_NET_CFG_CTRL                0x0000\n+#define   NFP_NET_CFG_CTRL_ENABLE         (0x1 <<  0) /* Global enable */\n+#define   NFP_NET_CFG_CTRL_PROMISC        (0x1 <<  1) /* Enable Promisc mode */\n+#define   NFP_NET_CFG_CTRL_L2BC           (0x1 <<  2) /* Allow L2 Broadcast */\n+#define   NFP_NET_CFG_CTRL_L2MC           (0x1 <<  3) /* Allow L2 Multicast */\n+#define   NFP_NET_CFG_CTRL_RXCSUM         (0x1 <<  4) /* Enable RX Checksum */\n+#define   NFP_NET_CFG_CTRL_TXCSUM         (0x1 <<  5) /* Enable TX Checksum */\n+#define   NFP_NET_CFG_CTRL_RXVLAN         (0x1 <<  6) /* Enable VLAN strip */\n+#define   NFP_NET_CFG_CTRL_TXVLAN         (0x1 <<  7) /* Enable VLAN insert */\n+#define   NFP_NET_CFG_CTRL_SCATTER        (0x1 <<  8) /* Scatter DMA */\n+#define   NFP_NET_CFG_CTRL_GATHER         (0x1 <<  9) /* Gather DMA */\n+#define   NFP_NET_CFG_CTRL_LSO            (0x1 << 10) /* LSO/TSO */\n+#define   NFP_NET_CFG_CTRL_RINGCFG        (0x1 << 16) /* Ring runtime changes */\n+#define   NFP_NET_CFG_CTRL_RSS            (0x1 << 17) /* RSS */\n+#define   NFP_NET_CFG_CTRL_IRQMOD         (0x1 << 18) /* Interrupt moderation */\n+#define   NFP_NET_CFG_CTRL_RINGPRIO       (0x1 << 19) /* Ring priorities */\n+#define   NFP_NET_CFG_CTRL_MSIXAUTO       (0x1 << 20) /* MSI-X auto-masking */\n+#define   NFP_NET_CFG_CTRL_TXRWB          (0x1 << 21) /* Write-back of TX ring*/\n+#define   NFP_NET_CFG_CTRL_L2SWITCH       (0x1 << 22) /* L2 Switch */\n+#define   NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */\n+#define   NFP_NET_CFG_CTRL_VXLANO         (0x1 << 24) /* Enable VXLAN */\n+#define   NFP_NET_CFG_CTRL_NVGREO         (0x1 << 25) /* Enable NVGRE */\n+#define NFP_NET_CFG_UPDATE              0x0004\n+#define   NFP_NET_CFG_UPDATE_GEN          (0x1 <<  0) /* General update */\n+#define   NFP_NET_CFG_UPDATE_RING         (0x1 <<  1) /* Ring config change */\n+#define   NFP_NET_CFG_UPDATE_RSS          (0x1 <<  2) /* RSS config change */\n+#define   NFP_NET_CFG_UPDATE_TXRPRIO      (0x1 <<  3) /* TX Ring prio change */\n+#define   NFP_NET_CFG_UPDATE_RXRPRIO      (0x1 <<  4) /* RX Ring prio change */\n+#define   NFP_NET_CFG_UPDATE_MSIX         (0x1 <<  5) /* MSI-X change */\n+#define   NFP_NET_CFG_UPDATE_L2SWITCH     (0x1 <<  6) /* Switch changes */\n+#define   NFP_NET_CFG_UPDATE_RESET        (0x1 <<  7) /* Update due to FLR */\n+#define   NFP_NET_CFG_UPDATE_IRQMOD       (0x1 <<  8) /* IRQ mod change */\n+#define   NFP_NET_CFG_UPDATE_ERR          (0x1 << 31) /* A error occurred */\n+#define NFP_NET_CFG_TXRS_ENABLE         0x0008\n+#define NFP_NET_CFG_RXRS_ENABLE         0x0010\n+#define NFP_NET_CFG_MTU                 0x0018\n+#define NFP_NET_CFG_FLBUFSZ             0x001c\n+#define NFP_NET_CFG_EXN                 0x001f\n+#define NFP_NET_CFG_LSC                 0x0020\n+#define NFP_NET_CFG_MACADDR             0x0024\n+\n+/*\n+ * Read-only words (0x0030 - 0x0050):\n+ * @NFP_NET_CFG_VERSION:     Firmware version number\n+ * @NFP_NET_CFG_STS:         Status\n+ * @NFP_NET_CFG_CAP:         Capabilities (same bits as @NFP_NET_CFG_CTRL)\n+ * @NFP_NET_MAX_TXRINGS:     Maximum number of TX rings\n+ * @NFP_NET_MAX_RXRINGS:     Maximum number of RX rings\n+ * @NFP_NET_MAX_MTU:         Maximum support MTU\n+ * @NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)\n+ * @NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)\n+ *\n+ * TODO:\n+ * - define more STS bits\n+ */\n+#define NFP_NET_CFG_VERSION             0x0030\n+#define NFP_NET_CFG_STS                 0x0034\n+#define   NFP_NET_CFG_STS_LINK            (0x1 << 0) /* Link up or down */\n+#define NFP_NET_CFG_CAP                 0x0038\n+#define NFP_NET_CFG_MAX_TXRINGS         0x003c\n+#define NFP_NET_CFG_MAX_RXRINGS         0x0040\n+#define NFP_NET_CFG_MAX_MTU             0x0044\n+/* Next two words are being used by VFs for solving THB350 issue */\n+#define NFP_NET_CFG_START_TXQ           0x0048\n+#define NFP_NET_CFG_START_RXQ           0x004c\n+\n+/*\n+ * NFP-3200 workaround (0x0050 - 0x0058)\n+ * @NFP_NET_CFG_SPARE_ADDR:  DMA address for ME code to use (e.g. YDS-155 fix)\n+ */\n+#define NFP_NET_CFG_SPARE_ADDR          0x0050\n+\n+/* 64B reserved for future use (0x0080 - 0x00c0) */\n+#define NFP_NET_CFG_RESERVED            0x0080\n+#define NFP_NET_CFG_RESERVED_SZ         0x0040\n+\n+/*\n+ * RSS configuration (0x0100 - 0x01ac):\n+ * Used only when NFP_NET_CFG_CTRL_RSS is enabled\n+ * @NFP_NET_CFG_RSS_CFG:     RSS configuration word\n+ * @NFP_NET_CFG_RSS_KEY:     RSS \"secret\" key\n+ * @NFP_NET_CFG_RSS_ITBL:    RSS indirection table\n+ */\n+#define NFP_NET_CFG_RSS_BASE            0x0100\n+#define NFP_NET_CFG_RSS_CTRL            NFP_NET_CFG_RSS_BASE\n+#define   NFP_NET_CFG_RSS_MASK            (0x7f)\n+#define   NFP_NET_CFG_RSS_MASK_of(_x)     ((_x) & 0x7f)\n+#define   NFP_NET_CFG_RSS_IPV4            (1 <<  8) /* RSS for IPv4 */\n+#define   NFP_NET_CFG_RSS_IPV6            (1 <<  9) /* RSS for IPv6 */\n+#define   NFP_NET_CFG_RSS_IPV4_TCP        (1 << 10) /* RSS for IPv4/TCP */\n+#define   NFP_NET_CFG_RSS_IPV4_UDP        (1 << 11) /* RSS for IPv4/UDP */\n+#define   NFP_NET_CFG_RSS_IPV6_TCP        (1 << 12) /* RSS for IPv6/TCP */\n+#define   NFP_NET_CFG_RSS_IPV6_UDP        (1 << 13) /* RSS for IPv6/UDP */\n+#define   NFP_NET_CFG_RSS_TOEPLITZ        (1 << 24) /* Use Toeplitz hash */\n+#define NFP_NET_CFG_RSS_KEY             (NFP_NET_CFG_RSS_BASE + 0x4)\n+#define NFP_NET_CFG_RSS_KEY_SZ          0x28\n+#define NFP_NET_CFG_RSS_ITBL            (NFP_NET_CFG_RSS_BASE + 0x4 + \\\n+\t\t\t\t\t NFP_NET_CFG_RSS_KEY_SZ)\n+#define NFP_NET_CFG_RSS_ITBL_SZ         0x80\n+\n+/*\n+ * TX ring configuration (0x200 - 0x800)\n+ * @NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration\n+ * @NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)\n+ * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)\n+ * @NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)\n+ * @NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)\n+ * @NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)\n+ * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n+ */\n+#define NFP_NET_CFG_TXR_BASE            0x0200\n+#define NFP_NET_CFG_TXR_ADDR(_x)        (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))\n+#define NFP_NET_CFG_TXR_WB_ADDR(_x)     (NFP_NET_CFG_TXR_BASE + 0x200 + \\\n+\t\t\t\t\t ((_x) * 0x8))\n+#define NFP_NET_CFG_TXR_SZ(_x)          (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))\n+#define NFP_NET_CFG_TXR_VEC(_x)         (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))\n+#define NFP_NET_CFG_TXR_PRIO(_x)        (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))\n+#define NFP_NET_CFG_TXR_IRQ_MOD(_x)     (NFP_NET_CFG_TXR_BASE + 0x500 + \\\n+\t\t\t\t\t ((_x) * 0x4))\n+\n+/*\n+ * RX ring configuration (0x0800 - 0x0c00)\n+ * @NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration\n+ * @NFP_NET_CFG_RXR_ADDR:    Per TX ring DMA address (8B entries)\n+ * @NFP_NET_CFG_RXR_SZ:      Per TX ring ring size (1B entries)\n+ * @NFP_NET_CFG_RXR_VEC:     Per TX ring MSI-X table entry (1B entries)\n+ * @NFP_NET_CFG_RXR_PRIO:    Per TX ring priority (1B entries)\n+ * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n+ */\n+#define NFP_NET_CFG_RXR_BASE            0x0800\n+#define NFP_NET_CFG_RXR_ADDR(_x)        (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))\n+#define NFP_NET_CFG_RXR_SZ(_x)          (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))\n+#define NFP_NET_CFG_RXR_VEC(_x)         (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))\n+#define NFP_NET_CFG_RXR_PRIO(_x)        (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))\n+#define NFP_NET_CFG_RXR_IRQ_MOD(_x)     (NFP_NET_CFG_RXR_BASE + 0x300 + \\\n+\t\t\t\t\t ((_x) * 0x4))\n+\n+/*\n+ * Interrupt Control/Cause registers (0x0c00 - 0x0d00)\n+ * These registers are only used when MSI-X auto-masking is not\n+ * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index\n+ * by MSI-X entry and are 1B in size.  If an entry is zero, the\n+ * corresponding entry is enabled.  If the FW generates an interrupt,\n+ * it writes a cause into the corresponding field.  This also masks\n+ * the MSI-X entry and the host driver must clear the register to\n+ * re-enable the interrupt.\n+ */\n+#define NFP_NET_CFG_ICR_BASE            0x0c00\n+#define NFP_NET_CFG_ICR(_x)             (NFP_NET_CFG_ICR_BASE + (_x))\n+#define   NFP_NET_CFG_ICR_UNMASKED      0x0\n+#define   NFP_NET_CFG_ICR_RXTX          0x1\n+#define   NFP_NET_CFG_ICR_LSC           0x2\n+\n+/*\n+ * General device stats (0x0d00 - 0x0d90)\n+ * all counters are 64bit.\n+ */\n+#define NFP_NET_CFG_STATS_BASE          0x0d00\n+#define NFP_NET_CFG_STATS_RX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x00)\n+#define NFP_NET_CFG_STATS_RX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x08)\n+#define NFP_NET_CFG_STATS_RX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x10)\n+#define NFP_NET_CFG_STATS_RX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x18)\n+#define NFP_NET_CFG_STATS_RX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x20)\n+#define NFP_NET_CFG_STATS_RX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x28)\n+#define NFP_NET_CFG_STATS_RX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x30)\n+#define NFP_NET_CFG_STATS_RX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x38)\n+#define NFP_NET_CFG_STATS_RX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x40)\n+\n+#define NFP_NET_CFG_STATS_TX_DISCARDS   (NFP_NET_CFG_STATS_BASE + 0x48)\n+#define NFP_NET_CFG_STATS_TX_ERRORS     (NFP_NET_CFG_STATS_BASE + 0x50)\n+#define NFP_NET_CFG_STATS_TX_OCTETS     (NFP_NET_CFG_STATS_BASE + 0x58)\n+#define NFP_NET_CFG_STATS_TX_UC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x60)\n+#define NFP_NET_CFG_STATS_TX_MC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x68)\n+#define NFP_NET_CFG_STATS_TX_BC_OCTETS  (NFP_NET_CFG_STATS_BASE + 0x70)\n+#define NFP_NET_CFG_STATS_TX_FRAMES     (NFP_NET_CFG_STATS_BASE + 0x78)\n+#define NFP_NET_CFG_STATS_TX_MC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x80)\n+#define NFP_NET_CFG_STATS_TX_BC_FRAMES  (NFP_NET_CFG_STATS_BASE + 0x88)\n+\n+/*\n+ * Per ring stats (0x1000 - 0x1800)\n+ * options, 64bit per entry\n+ * @NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)\n+ * @NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)\n+ */\n+#define NFP_NET_CFG_TXR_STATS_BASE      0x1000\n+#define NFP_NET_CFG_TXR_STATS(_x)       (NFP_NET_CFG_TXR_STATS_BASE + \\\n+\t\t\t\t\t ((_x) * 0x10))\n+#define NFP_NET_CFG_RXR_STATS_BASE      0x1400\n+#define NFP_NET_CFG_RXR_STATS(_x)       (NFP_NET_CFG_RXR_STATS_BASE + \\\n+\t\t\t\t\t ((_x) * 0x10))\n+\n+#endif /* _NFP_NET_CTRL_H_ */\n+/*\n+ * Local variables:\n+ * c-file-style: \"Linux\"\n+ * indent-tabs-mode: t\n+ * End:\n+ */\ndiff --git a/drivers/net/nfp/nfp_net_logs.h b/drivers/net/nfp/nfp_net_logs.h\nnew file mode 100644\nindex 0000000..0b966e4\n--- /dev/null\n+++ b/drivers/net/nfp/nfp_net_logs.h\n@@ -0,0 +1,75 @@\n+/*\n+ * Copyright (c) 2014, 2015 Netronome Systems, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *  this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *  notice, this list of conditions and the following disclaimer in the\n+ *  documentation and/or other materials provided with the distribution\n+ *\n+ * 3. Neither the name of the copyright holder nor the names of its\n+ *  contributors may be used to endorse or promote products derived from this\n+ *  software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _NFP_NET_LOGS_H_\n+#define _NFP_NET_LOGS_H_\n+\n+#include <rte_log.h>\n+\n+#define RTE_LIBRTE_NFP_NET_DEBUG_INIT 1\n+\n+#ifdef RTE_LIBRTE_NFP_NET_DEBUG_INIT\n+#define PMD_INIT_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n+#else\n+#define PMD_INIT_LOG(level, fmt, args...) do { } while (0)\n+#define PMD_INIT_FUNC_TRACE() do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_NFP_NET_DEBUG_RX\n+#define PMD_RX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s() rx: \" fmt, __func__, ## args)\n+#else\n+#define PMD_RX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_NFP_NET_DEBUG_TX\n+#define PMD_TX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s() tx: \" fmt, __func__, ## args)\n+#else\n+#define PMD_TX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_NFP_NET_DEBUG_DRIVER\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n+#else\n+#define PMD_DRV_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_NFP_NET_DEBUG_INIT\n+#define ASSERT(x) if (!(x)) rte_panic(\"NFP_NET: x\")\n+#else\n+#define ASSERT(x) do { } while (0)\n+#endif\n+\n+#endif /* _NFP_NET_LOGS_H_ */\ndiff --git a/drivers/net/nfp/nfp_net_pmd.h b/drivers/net/nfp/nfp_net_pmd.h\nnew file mode 100644\nindex 0000000..3f9fef2\n--- /dev/null\n+++ b/drivers/net/nfp/nfp_net_pmd.h\n@@ -0,0 +1,434 @@\n+/*\n+ * Copyright (c) 2014, 2015 Netronome Systems, Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ *  this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright\n+ *  notice, this list of conditions and the following disclaimer in the\n+ *  documentation and/or other materials provided with the distribution\n+ *\n+ * 3. Neither the name of the copyright holder nor the names of its\n+ *  contributors may be used to endorse or promote products derived from this\n+ *  software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/*\n+ * vim:shiftwidth=8:noexpandtab\n+ *\n+ * @file dpdk/pmd/nfp_net_pmd.h\n+ *\n+ * Netronome NFP_NET PDM driver\n+ */\n+\n+#ifndef _NFP_NET_PMD_H_\n+#define _NFP_NET_PMD_H_\n+\n+#define NFP_NET_PMD_VERSION \"0.1\"\n+#define PCI_VENDOR_ID_NETRONOME         0x19ee\n+#define PCI_DEVICE_ID_NFP6000_PF_NIC    0x6000\n+#define PCI_DEVICE_ID_NFP6000_VF_NIC    0x6003\n+\n+/* Forward declaration */\n+struct nfp_net_adapter;\n+\n+/*\n+ * The maximum number of descriptors is limited by design as\n+ * DPDK uses uint16_t variables for these values\n+ */\n+#define NFP_NET_MAX_TX_DESC (32 * 1024)\n+#define NFP_NET_MIN_TX_DESC 64\n+\n+#define NFP_NET_MAX_RX_DESC (32 * 1024)\n+#define NFP_NET_MIN_RX_DESC 64\n+\n+/* Bar allocation */\n+#define NFP_NET_CRTL_BAR        0\n+#define NFP_NET_TX_BAR          2\n+#define NFP_NET_RX_BAR          2\n+\n+/* Macros for accessing the Queue Controller Peripheral 'CSRs' */\n+#define NFP_QCP_QUEUE_OFF(_x)                 ((_x) * 0x800)\n+#define NFP_QCP_QUEUE_ADD_RPTR                  0x0000\n+#define NFP_QCP_QUEUE_ADD_WPTR                  0x0004\n+#define NFP_QCP_QUEUE_STS_LO                    0x0008\n+#define NFP_QCP_QUEUE_STS_LO_READPTR_mask     (0x3ffff)\n+#define NFP_QCP_QUEUE_STS_HI                    0x000c\n+#define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask    (0x3ffff)\n+\n+/* Interrupt definitions */\n+#define NFP_NET_IRQ_LSC_IDX             0\n+\n+#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n+\t((uint64_t)((mb)->buf_physaddr + (mb)->data_off))\n+\n+/* Default values for RX/TX configuration */\n+#define DEFAULT_RX_FREE_THRESH  32\n+#define DEFAULT_RX_PTHRESH      8\n+#define DEFAULT_RX_HTHRESH      8\n+#define DEFAULT_RX_WTHRESH      0\n+\n+#define DEFAULT_TX_RS_THRESH\t32\n+#define DEFAULT_TX_FREE_THRESH  32\n+#define DEFAULT_TX_PTHRESH      32\n+#define DEFAULT_TX_HTHRESH      0\n+#define DEFAULT_TX_WTHRESH      0\n+#define DEFAULT_TX_RSBIT_THRESH 32\n+\n+/* Alignment for dma zones */\n+#define NFP_MEMZONE_ALIGN\t128\n+\n+/*\n+ * This is used by the reconfig protocol. It sets the maximum time waiting in\n+ * milliseconds before a reconfig timeout happens.\n+ */\n+#define NFP_NET_POLL_TIMEOUT    5000\n+\n+#define NFP_QCP_QUEUE_ADDR_SZ   (0x800)\n+\n+#define NFP_NET_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */\n+#define NFP_NET_LINK_UP_CHECK_TIMEOUT   1000 /* ms */\n+\n+#include <linux/types.h>\n+\n+static inline uint8_t nn_readb(volatile void *addr)\n+{\n+\treturn *((volatile uint8_t *)(addr));\n+}\n+\n+static inline void nn_writeb(__u8 val, volatile void *addr)\n+{\n+\t*((volatile uint8_t *)(addr)) = val;\n+}\n+\n+static inline uint32_t nn_readl(volatile const void *addr)\n+{\n+\treturn *((volatile const uint32_t *)(addr));\n+}\n+\n+static inline void nn_writel(__u32 val, volatile void *addr)\n+{\n+\t*((volatile uint32_t *)(addr)) = val;\n+}\n+\n+static inline uint64_t nn_readq(volatile void *addr)\n+{\n+\tconst volatile __u32 *p = addr;\n+\t__u32 low, high;\n+\n+\thigh = nn_readl((volatile const void *)(p + 1));\n+\tlow = nn_readl((volatile const void *)p);\n+\n+\treturn low + ((__u64)high << 32);\n+}\n+\n+static inline void nn_writeq(__u64 val, volatile void *addr)\n+{\n+\tnn_writel(val >> 32, (volatile char *)addr + 4);\n+\tnn_writel(val, addr);\n+}\n+\n+/* TX descriptor format */\n+#define PCIE_DESC_TX_EOP                (1 << 7)\n+#define PCIE_DESC_TX_OFFSET_MASK        (0x7f)\n+\n+/* Flags in the host TX descriptor */\n+#define PCIE_DESC_TX_CSUM               (1 << 7)\n+#define PCIE_DESC_TX_IP4_CSUM           (1 << 6)\n+#define PCIE_DESC_TX_TCP_CSUM           (1 << 5)\n+#define PCIE_DESC_TX_UDP_CSUM           (1 << 4)\n+#define PCIE_DESC_TX_VLAN               (1 << 3)\n+#define PCIE_DESC_TX_LSO                (1 << 2)\n+#define PCIE_DESC_TX_ENCAP_NONE         (0)\n+#define PCIE_DESC_TX_ENCAP_VXLAN        (1 << 1)\n+#define PCIE_DESC_TX_ENCAP_GRE          (1 << 0)\n+\n+struct nfp_net_tx_desc {\n+\tunion {\n+\t\tstruct {\n+\t\t\t__u8 dma_addr_hi;   /* High bits of host buf address */\n+\t\t\t__le16 dma_len;     /* Length to DMA for this desc */\n+\t\t\t__u8 offset_eop;    /* Offset in buf where pkt starts +\n+\t\t\t\t\t     * highest bit is eop flag.\n+\t\t\t\t\t     */\n+\t\t\t__le32 dma_addr_lo; /* Low 32bit of host buf addr */\n+\n+\t\t\t__le16 lso;         /* MSS to be used for LSO */\n+\t\t\t__u8 l4_offset;     /* LSO, where the L4 data starts */\n+\t\t\t__u8 flags;         /* TX Flags, see @PCIE_DESC_TX_* */\n+\n+\t\t\t__le16 vlan;        /* VLAN tag to add if indicated */\n+\t\t\t__le16 data_len;    /* Length of frame + meta data */\n+\t\t} __attribute__((__packed__));\n+\t\t__le32 vals[4];\n+\t};\n+};\n+\n+struct nfp_net_txq {\n+\tstruct nfp_net_hw *hw; /* Backpointer to nfp_net structure */\n+\n+\t/*\n+\t * Queue information: @qidx is the queue index from Linux's\n+\t * perspective.  @tx_qcidx is the index of the Queue\n+\t * Controller Peripheral queue relative to the TX queue BAR.\n+\t * @cnt is the size of the queue in number of\n+\t * descriptors. @qcp_q is a pointer to the base of the queue\n+\t * structure on the NFP\n+\t */\n+\t__u8 *qcp_q;\n+\n+\t/*\n+\t * Read and Write pointers.  @wr_p and @rd_p are host side pointer,\n+\t * they are free running and have little relation to the QCP pointers *\n+\t * @qcp_rd_p is a local copy queue controller peripheral read pointer\n+\t */\n+\n+\t__u32 wr_p;\n+\t__u32 rd_p;\n+\t__u32 qcp_rd_p;\n+\n+\t__u32 tx_count;\n+\n+\t__u32 tx_free_thresh;\n+\t__u32 tail;\n+\n+\t/*\n+\t * For each descriptor keep a reference to the mbuff and\n+\t * DMA address used until completion is signalled.\n+\t */\n+\tstruct {\n+\t\tstruct rte_mbuf *mbuf;\n+\t} *txbufs;\n+\n+\t/*\n+\t * Information about the host side queue location. @txds is\n+\t * the virtual address for the queue, @dma is the DMA address\n+\t * of the queue and @size is the size in bytes for the queue\n+\t * (needed for free)\n+\t */\n+\tstruct nfp_net_tx_desc *txds;\n+\n+\t/*\n+\t * At this point 56 bytes have been used for all the fields in the\n+\t * TX critical path. We have room for 8 bytes and still all placed\n+\t * in a cache line. We are not using the threshold values below nor\n+\t * the txq_flags but if we need to, we can add the most used in the\n+\t * remaining bytes.\n+\t */\n+\t__u32 tx_rs_thresh; /* not used by now. Future? */\n+\t__u32 tx_pthresh;   /* not used by now. Future? */\n+\t__u32 tx_hthresh;   /* not used by now. Future? */\n+\t__u32 tx_wthresh;   /* not used by now. Future? */\n+\t__u32 txq_flags;    /* not used by now. Future? */\n+\t__u8  port_id;\n+\tint qidx;\n+\tint tx_qcidx;\n+\t__le64 dma;\n+} __attribute__ ((__aligned__(64)));\n+\n+/* RX and freelist descriptor format */\n+#define PCIE_DESC_RX_DD                 (1 << 7)\n+#define PCIE_DESC_RX_META_LEN_MASK      (0x7f)\n+\n+/* Flags in the RX descriptor */\n+#define PCIE_DESC_RX_RSS                (1 << 15)\n+#define PCIE_DESC_RX_I_IP4_CSUM         (1 << 14)\n+#define PCIE_DESC_RX_I_IP4_CSUM_OK      (1 << 13)\n+#define PCIE_DESC_RX_I_TCP_CSUM         (1 << 12)\n+#define PCIE_DESC_RX_I_TCP_CSUM_OK      (1 << 11)\n+#define PCIE_DESC_RX_I_UDP_CSUM         (1 << 10)\n+#define PCIE_DESC_RX_I_UDP_CSUM_OK      (1 <<  9)\n+#define PCIE_DESC_RX_INGRESS_PORT       (1 <<  8)\n+#define PCIE_DESC_RX_EOP                (1 <<  7)\n+#define PCIE_DESC_RX_IP4_CSUM           (1 <<  6)\n+#define PCIE_DESC_RX_IP4_CSUM_OK        (1 <<  5)\n+#define PCIE_DESC_RX_TCP_CSUM           (1 <<  4)\n+#define PCIE_DESC_RX_TCP_CSUM_OK        (1 <<  3)\n+#define PCIE_DESC_RX_UDP_CSUM           (1 <<  2)\n+#define PCIE_DESC_RX_UDP_CSUM_OK        (1 <<  1)\n+#define PCIE_DESC_RX_VLAN               (1 <<  0)\n+\n+struct nfp_net_rx_desc {\n+\tunion {\n+\t\t/* Freelist descriptor */\n+\t\tstruct {\n+\t\t\t__u8 dma_addr_hi;\n+\t\t\t__le16 spare;\n+\t\t\t__u8 dd;\n+\n+\t\t\t__le32 dma_addr_lo;\n+\t\t} __attribute__((__packed__)) fld;\n+\n+\t\t/* RX descriptor */\n+\t\tstruct {\n+\t\t\t__le16 data_len;\n+\t\t\t__u8 reserved;\n+\t\t\t__u8 meta_len_dd;\n+\n+\t\t\t__le16 flags;\n+\t\t\t__le16 vlan;\n+\t\t} __attribute__((__packed__)) rxd;\n+\n+\t\t__le32 vals[2];\n+\t};\n+};\n+\n+struct nfp_net_rx_buff {\n+\tstruct rte_mbuf *mbuf;\n+};\n+\n+struct nfp_net_rxq {\n+\tstruct nfp_net_hw *hw;\t/* Backpointer to nfp_net structure */\n+\n+\t /*\n+\t  * @qcp_fl and @qcp_rx are pointers to the base addresses of the\n+\t  * freelist and RX queue controller peripheral queue structures on the\n+\t  * NFP\n+\t  */\n+\t__u8 *qcp_fl;\n+\t__u8 *qcp_rx;\n+\n+\t/*\n+\t * Read and Write pointers.  @wr_p and @rd_p are host side\n+\t * pointer, they are free running and have little relation to\n+\t * the QCP pointers. @wr_p is where the driver adds new\n+\t * freelist descriptors and @rd_p is where the driver start\n+\t * reading descriptors for newly arrive packets from.\n+\t */\n+\t__u32 wr_p;\n+\t__u32 rd_p;\n+\n+\t/*\n+\t * For each buffer placed on the freelist, record the\n+\t * associated SKB\n+\t */\n+\tstruct nfp_net_rx_buff *rxbufs;\n+\n+\t/*\n+\t * Information about the host side queue location.  @rxds is\n+\t * the virtual address for the queue\n+\t */\n+\tstruct nfp_net_rx_desc *rxds;\n+\n+\t/*\n+\t * The mempool is created by the user specifying a mbuf size.\n+\t * We save here the reference of the mempool needed in the RX\n+\t * path and the mbuf size for checking received packets can be\n+\t * safely copied to the mbuf using the NFP_NET_RX_OFFSET\n+\t */\n+\tstruct rte_mempool *mem_pool;\n+\tuint16_t mbuf_size;\n+\n+\t/*\n+\t * Next two fields are used for giving more free descriptors\n+\t * to the NFP\n+\t */\n+\tuint16_t rx_free_thresh;\n+\tuint16_t nb_rx_hold;\n+\n+\t /* the size of the queue in number of descriptors */\n+\tuint16_t rx_count;\n+\n+\t/*\n+\t * Fields above this point fit in a single cache line and are all used\n+\t * in the RX critical path. Fields below this point are just used\n+\t * during queue configuration or not used at all (yet)\n+\t */\n+\n+\t/* referencing dev->data->port_id */\n+\tuint16_t port_id;\n+\n+\tuint8_t  crc_len; /* Not used by now */\n+\tuint8_t  drop_en; /* Not used by now */\n+\n+\t/* DMA address of the queue */\n+\t__le64 dma;\n+\n+\t/*\n+\t * Queue information: @qidx is the queue index from Linux's\n+\t * perspective.  @fl_qcidx is the index of the Queue\n+\t * Controller peripheral queue relative to the RX queue BAR\n+\t * used for the freelist and @rx_qcidx is the Queue Controller\n+\t * Peripheral index for the RX queue.\n+\t */\n+\tint qidx;\n+\tint fl_qcidx;\n+\tint rx_qcidx;\n+} __attribute__ ((__aligned__(64)));\n+\n+struct nfp_net_hw {\n+\t/* Info from the firmware */\n+\tuint32_t ver;\n+\tuint32_t cap;\n+\tuint32_t max_mtu;\n+\tuint32_t mtu;\n+\n+\t/* Current values for control */\n+\tuint32_t ctrl;\n+\n+\tuint8_t *ctrl_bar;\n+\tuint8_t *tx_bar;\n+\tuint8_t *rx_bar;\n+\n+\tint stride_rx;\n+\tint stride_tx;\n+\n+\t__u8 *qcp_cfg;\n+\n+\tuint32_t max_tx_queues;\n+\tuint32_t max_rx_queues;\n+\tuint16_t flbufsz;\n+\tuint16_t device_id;\n+\tuint16_t vendor_id;\n+\tuint16_t subsystem_device_id;\n+\tuint16_t subsystem_vendor_id;\n+#if defined(DSTQ_SELECTION)\n+#if DSTQ_SELECTION\n+\tuint16_t device_function;\n+#endif\n+#endif\n+\n+\tuint8_t mac_addr[ETHER_ADDR_LEN];\n+\n+\t/* Records starting point for counters */\n+\tstruct rte_eth_stats eth_stats_base;\n+\n+#ifdef NFP_NET_LIBNFP\n+\tstruct nfp_cpp *cpp;\n+\tstruct nfp_cpp_area *ctrl_area;\n+\tstruct nfp_cpp_area *tx_area;\n+\tstruct nfp_cpp_area *rx_area;\n+\tstruct nfp_cpp_area *msix_area;\n+#endif\n+};\n+\n+struct nfp_net_adapter {\n+\tstruct nfp_net_hw hw;\n+};\n+\n+#define NFP_NET_DEV_PRIVATE_TO_HW(adapter)\\\n+\t(&((struct nfp_net_adapter *)adapter)->hw)\n+\n+#endif /* _NFP_NET_PMD_H_ */\n+/*\n+ * Local variables:\n+ * c-file-style: \"Linux\"\n+ * indent-tabs-mode: t\n+ * End:\n+ */\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 9e1909e..4a00f0f 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -142,6 +142,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_RING)       += -lrte_pmd_ring\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP)       += -lrte_pmd_pcap\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET)  += -lrte_pmd_af_packet\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL)       += -lrte_pmd_null\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_NFP_PMD)        += -lrte_pmd_nfp\n \n endif # ! $(CONFIG_RTE_BUILD_SHARED_LIB)\n \n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "1/4"
    ]
}