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[ { "id": 116374, "web_url": "https://patches.dpdk.org/comment/116374/", "msgid": "<6FD6A7610D20924F885A4ECF34E8AC910463D264@CDSMSX102.ccr.corp.intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/6FD6A7610D20924F885A4ECF34E8AC910463D264@CDSMSX102.ccr.corp.intel.com", "date": "2020-07-21T06:41:45", "subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "submitter": { "id": 1686, "url": "https://patches.dpdk.org/api/people/1686/?format=api", "name": "Xie, WeiX", "email": "weix.xie@intel.com" }, "content": "Tested-by: Zhang, XiX <xix.zhang@intel.com>\n\nRegards,\nXie Wei\n\n\n-----Original Message-----\nFrom: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shougang Wang\nSent: Tuesday, July 21, 2020 1:49 PM\nTo: dev@dpdk.org\nCc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Wang, ShougangX <shougangx.wang@intel.com>; stable@dpdk.org\nSubject: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table\n\nThe hash look up table(LUT) will not be initializing when starting testpmd with --disable-rss. So that some invalid queue indexes may still in the LUT. When enable RSS by creating RSS rule, some packets will not be into the valid queues.\nThis patch fixes this issue by initializing the LUT when creating an RSS rule.\n\nFixes: feaae285b342 (\"net/i40e: support hash configuration in RSS flow\")\nCc: stable@dpdk.org\n\nSigned-off-by: Shougang Wang <shougangx.wang@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 134 ++++++++++++++++-----------------\n 1 file changed, 63 insertions(+), 71 deletions(-)\n\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 393b5320f..e56543393 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -13070,6 +13070,55 @@ i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,\n \treturn 0;\n }\n \n+/* If conf is NULL, function will init hash LUT with default \n+configration*/ static int i40e_rss_set_lut(struct i40e_pf *pf,\n+\t\t struct i40e_rte_flow_rss_conf *conf) {\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tuint32_t lut = 0;\n+\tuint16_t j, num;\n+\tuint32_t i;\n+\n+\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n+\t * It's necessary to calculate the actual PF queues that are configured.\n+\t */\n+\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n+\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n+\telse\n+\t\tnum = pf->dev_data->nb_rx_queues;\n+\n+\tif (conf == NULL)\n+\t\tnum = RTE_MIN(num, I40E_MAX_Q_PER_TC);\n+\telse\n+\t\tnum = RTE_MIN(num, conf->conf.queue_num);\n+\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n+\t\t\tnum);\n+\n+\tif (num == 0) {\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n+\t\t\tpf->dev_data->port_id);\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\t/* Fill in redirection table */\n+\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n+\t\tif (j == num)\n+\t\t\tj = 0;\n+\t\tif (conf == NULL)\n+\t\t\tlut = (lut << 8) | (j & ((0x1 <<\n+\t\t\t\thw->func_caps.rss_table_entry_width) - 1));\n+\t\telse\n+\t\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n+\t\t\thw->func_caps.rss_table_entry_width) - 1));\n+\t\tif ((i & 3) == 3)\n+\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Write HENA register to enable hash */ static int i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf) @@ -13318,12 +13367,24 @@ static int i40e_rss_enable_hash(struct i40e_pf *pf,\n \t\tstruct i40e_rte_flow_rss_conf *conf)\n {\n+\tenum rte_eth_rx_mq_mode mq_mode = \n+pf->dev_data->dev_conf.rxmode.mq_mode;\n \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n \tstruct i40e_rte_flow_rss_conf rss_conf;\n+\tint ret;\n \n \tif (!(conf->conf.types & pf->adapter->flow_types_mask))\n \t\treturn -ENOTSUP;\n \n+\t/* If the RSS is disabled before this, the LUT is uninitialized. \n+\t * So it is necessary to initialize it here.\n+\t */\n+\tif (!(mq_mode & ETH_MQ_RX_RSS_FLAG) && !pf->rss_info.conf.queue_num &&\n+\t !pf->adapter->rss_reta_updated) {\n+\t\tret = i40e_rss_set_lut(pf, NULL);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tmemset(&rss_conf, 0, sizeof(rss_conf));\n \trte_memcpy(&rss_conf, conf, sizeof(rss_conf));\n \n@@ -13362,39 +13423,7 @@ static int\n i40e_rss_config_queue_region(struct i40e_pf *pf,\n \t\tstruct i40e_rte_flow_rss_conf *conf)\n {\n-\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n-\tuint32_t lut = 0;\n-\tuint16_t j, num;\n-\tuint32_t i;\n-\n-\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n-\t * It's necessary to calculate the actual PF queues that are configured.\n-\t */\n-\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n-\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n-\telse\n-\t\tnum = pf->dev_data->nb_rx_queues;\n-\n-\tnum = RTE_MIN(num, conf->conf.queue_num);\n-\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n-\t\t\tnum);\n-\n-\tif (num == 0) {\n-\t\tPMD_DRV_LOG(ERR,\n-\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n-\t\t\tpf->dev_data->port_id);\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\t/* Fill in redirection table */\n-\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n-\t\tif (j == num)\n-\t\t\tj = 0;\n-\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n-\t\t\thw->func_caps.rss_table_entry_width) - 1));\n-\t\tif ((i & 3) == 3)\n-\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n-\t}\n+\ti40e_rss_set_lut(pf, conf);\n \n \ti40e_rss_mark_invalid_rule(pf, conf);\n \n@@ -13491,46 +13520,9 @@ i40e_rss_disable_hash(struct i40e_pf *pf, static int i40e_rss_clear_queue_region(struct i40e_pf *pf) {\n-\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n-\tuint16_t queue[I40E_MAX_Q_PER_TC];\n-\tuint32_t num_rxq, i;\n-\tuint32_t lut = 0;\n-\tuint16_t j, num;\n-\n-\tnum_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);\n \n-\tfor (j = 0; j < num_rxq; j++)\n-\t\tqueue[j] = j;\n-\n-\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n-\t * It's necessary to calculate the actual PF queues that are configured.\n-\t */\n-\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n-\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n-\telse\n-\t\tnum = pf->dev_data->nb_rx_queues;\n-\n-\tnum = RTE_MIN(num, num_rxq);\n-\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n-\t\t\tnum);\n-\n-\tif (num == 0) {\n-\t\tPMD_DRV_LOG(ERR,\n-\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n-\t\t\tpf->dev_data->port_id);\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\t/* Fill in redirection table */\n-\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n-\t\tif (j == num)\n-\t\t\tj = 0;\n-\t\tlut = (lut << 8) | (queue[j] & ((0x1 <<\n-\t\t\thw->func_caps.rss_table_entry_width) - 1));\n-\t\tif ((i & 3) == 3)\n-\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n-\t}\n+\ti40e_rss_set_lut(pf, NULL);\n \n \trss_info->conf.queue_num = 0;\n \tmemset(&rss_info->conf.queue, 0, sizeof(uint16_t));\n--\n2.17.1", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D363BA0526;\n\tTue, 21 Jul 2020 08:41:56 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 78BA91BFFF;\n\tTue, 21 Jul 2020 08:41:55 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id 072CB1BFFE;\n Tue, 21 Jul 2020 08:41:51 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Jul 2020 23:41:50 -0700", "from fmsmsx105.amr.corp.intel.com ([10.18.124.203])\n by fmsmga002.fm.intel.com with ESMTP; 20 Jul 2020 23:41:50 -0700", "from fmsmsx114.amr.corp.intel.com (10.18.116.8) by\n FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS)\n id 14.3.439.0; Mon, 20 Jul 2020 23:41:50 -0700", "from cdsmsx103.ccr.corp.intel.com (172.17.3.37) by\n FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS)\n id 14.3.439.0; Mon, 20 Jul 2020 23:41:49 -0700", "from cdsmsx102.ccr.corp.intel.com ([169.254.2.201]) by\n CDSMSX103.ccr.corp.intel.com ([169.254.5.225]) with mapi id 14.03.0439.000;\n Tue, 21 Jul 2020 14:41:46 +0800" ], "IronPort-SDR": [ "\n MAu8ZQUkPw2kukxR3j5/TVc3JMMnwCyPsmS/ISs1slU1rpclUC1C8kpfduEbGUskEN9p/ZyF6f\n 4W1E/YKDJJZw==", "\n colI+XRXKPtZNP1hw1B7XGL+dgWTo77lNQklrRzVshzsgiFEPBzNyD2+IPPsYKPZIqaOZaevBu\n 7A1NB1mdqv3Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9688\"; a=\"211623482\"", "E=Sophos;i=\"5.75,377,1589266800\"; d=\"scan'208\";a=\"211623482\"", "E=Sophos;i=\"5.75,377,1589266800\"; d=\"scan'208\";a=\"319799674\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "\"Xie, WeiX\" <weix.xie@intel.com>", "To": "\"Wang, ShougangX\" <shougangx.wang@intel.com>,\n \"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Xing, Beilei\" <beilei.xing@intel.com>, \"Guo, Jia\" <jia.guo@intel.com>,\n \"Wang, ShougangX\" <shougangx.wang@intel.com>, \"stable@dpdk.org\"\n <stable@dpdk.org>", "Thread-Topic": "[dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "Thread-Index": "AQHWXySrAslY/DhCGU2jcPdEARPwAakRlUHA", "Date": "Tue, 21 Jul 2020 06:41:45 +0000", "Message-ID": "\n <6FD6A7610D20924F885A4ECF34E8AC910463D264@CDSMSX102.ccr.corp.intel.com>", "References": "<20200715063515.9262-1-shougangx.wang@intel.com>\n <20200721054920.29749-1-shougangx.wang@intel.com>", "In-Reply-To": "<20200721054920.29749-1-shougangx.wang@intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[172.17.6.105]", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "MIME-Version": "1.0", "Subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 116468, "web_url": "https://patches.dpdk.org/comment/116468/", "msgid": "<039ED4275CED7440929022BC67E7061154863E7D@SHSMSX103.ccr.corp.intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/039ED4275CED7440929022BC67E7061154863E7D@SHSMSX103.ccr.corp.intel.com", "date": "2020-07-22T05:31:01", "subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "content": "> -----Original Message-----\n> From: dev <dev-bounces@dpdk.org> On Behalf Of Shougang Wang\n> Sent: Tuesday, July 21, 2020 1:49 PM\n> To: dev@dpdk.org\n> Cc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Wang,\n> ShougangX <shougangx.wang@intel.com>; stable@dpdk.org\n> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table\n> \n> The hash look up table(LUT) will not be initializing when starting testpmd with\n> --disable-rss. So that some invalid queue indexes may still in the LUT. When\n> enable RSS by creating RSS rule, some packets will not be into the valid queues.\n> This patch fixes this issue by initializing the LUT when creating an RSS rule.\n\nCould you explain why you only initialize the LUT when creating an RSS rule but not at dev_init or dev_start?\nWhat if user configure LUT table before create a RSS rule? Does that mean the LUT table will be flushed?\n\n> \n> Fixes: feaae285b342 (\"net/i40e: support hash configuration in RSS flow\")\n> Cc: stable@dpdk.org\n> \n> Signed-off-by: Shougang Wang <shougangx.wang@intel.com>\n> ---\n> drivers/net/i40e/i40e_ethdev.c | 134 ++++++++++++++++-----------------\n> 1 file changed, 63 insertions(+), 71 deletions(-)\n> \n> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\n> index 393b5320f..e56543393 100644\n> --- a/drivers/net/i40e/i40e_ethdev.c\n> +++ b/drivers/net/i40e/i40e_ethdev.c\n> @@ -13070,6 +13070,55 @@ i40e_rss_conf_init(struct i40e_rte_flow_rss_conf\n> *out,\n> \treturn 0;\n> }\n> \n> +/* If conf is NULL, function will init hash LUT with default\n> +configration*/ static int i40e_rss_set_lut(struct i40e_pf *pf,\n> +\t\t struct i40e_rte_flow_rss_conf *conf) {\n> +\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> +\tuint32_t lut = 0;\n> +\tuint16_t j, num;\n> +\tuint32_t i;\n> +\n> +\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> +\t * It's necessary to calculate the actual PF queues that are configured.\n> +\t */\n> +\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> +\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> +\telse\n> +\t\tnum = pf->dev_data->nb_rx_queues;\n> +\n> +\tif (conf == NULL)\n> +\t\tnum = RTE_MIN(num, I40E_MAX_Q_PER_TC);\n> +\telse\n> +\t\tnum = RTE_MIN(num, conf->conf.queue_num);\n> +\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> +\t\t\tnum);\n> +\n> +\tif (num == 0) {\n> +\t\tPMD_DRV_LOG(ERR,\n> +\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> +\t\t\tpf->dev_data->port_id);\n> +\t\treturn -ENOTSUP;\n> +\t}\n> +\n> +\t/* Fill in redirection table */\n> +\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> +\t\tif (j == num)\n> +\t\t\tj = 0;\n> +\t\tif (conf == NULL)\n> +\t\t\tlut = (lut << 8) | (j & ((0x1 <<\n> +\t\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> +\t\telse\n> +\t\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> +\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> +\t\tif ((i & 3) == 3)\n> +\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> /* Write HENA register to enable hash */ static int\n> i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)\n> @@ -13318,12 +13367,24 @@ static int i40e_rss_enable_hash(struct i40e_pf\n> *pf,\n> \t\tstruct i40e_rte_flow_rss_conf *conf)\n> {\n> +\tenum rte_eth_rx_mq_mode mq_mode =\n> +pf->dev_data->dev_conf.rxmode.mq_mode;\n> \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> \tstruct i40e_rte_flow_rss_conf rss_conf;\n> +\tint ret;\n> \n> \tif (!(conf->conf.types & pf->adapter->flow_types_mask))\n> \t\treturn -ENOTSUP;\n> \n> +\t/* If the RSS is disabled before this, the LUT is uninitialized.\n> +\t * So it is necessary to initialize it here.\n> +\t */\n> +\tif (!(mq_mode & ETH_MQ_RX_RSS_FLAG)\n> && !pf->rss_info.conf.queue_num &&\n> +\t !pf->adapter->rss_reta_updated) {\n> +\t\tret = i40e_rss_set_lut(pf, NULL);\n> +\t\tif (ret)\n> +\t\t\treturn ret;\n> +\t}\n> +\n> \tmemset(&rss_conf, 0, sizeof(rss_conf));\n> \trte_memcpy(&rss_conf, conf, sizeof(rss_conf));\n> \n> @@ -13362,39 +13423,7 @@ static int\n> i40e_rss_config_queue_region(struct i40e_pf *pf,\n> \t\tstruct i40e_rte_flow_rss_conf *conf)\n> {\n> -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> -\tuint32_t lut = 0;\n> -\tuint16_t j, num;\n> -\tuint32_t i;\n> -\n> -\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> -\t * It's necessary to calculate the actual PF queues that are configured.\n> -\t */\n> -\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> -\telse\n> -\t\tnum = pf->dev_data->nb_rx_queues;\n> -\n> -\tnum = RTE_MIN(num, conf->conf.queue_num);\n> -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> -\t\t\tnum);\n> -\n> -\tif (num == 0) {\n> -\t\tPMD_DRV_LOG(ERR,\n> -\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> -\t\t\tpf->dev_data->port_id);\n> -\t\treturn -ENOTSUP;\n> -\t}\n> -\n> -\t/* Fill in redirection table */\n> -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> -\t\tif (j == num)\n> -\t\t\tj = 0;\n> -\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> -\t\tif ((i & 3) == 3)\n> -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> -\t}\n> +\ti40e_rss_set_lut(pf, conf);\n> \n> \ti40e_rss_mark_invalid_rule(pf, conf);\n> \n> @@ -13491,46 +13520,9 @@ i40e_rss_disable_hash(struct i40e_pf *pf, static\n> int i40e_rss_clear_queue_region(struct i40e_pf *pf) {\n> -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> -\tuint16_t queue[I40E_MAX_Q_PER_TC];\n> -\tuint32_t num_rxq, i;\n> -\tuint32_t lut = 0;\n> -\tuint16_t j, num;\n> -\n> -\tnum_rxq = RTE_MIN(pf->dev_data->nb_rx_queues,\n> I40E_MAX_Q_PER_TC);\n> \n> -\tfor (j = 0; j < num_rxq; j++)\n> -\t\tqueue[j] = j;\n> -\n> -\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> -\t * It's necessary to calculate the actual PF queues that are configured.\n> -\t */\n> -\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> -\telse\n> -\t\tnum = pf->dev_data->nb_rx_queues;\n> -\n> -\tnum = RTE_MIN(num, num_rxq);\n> -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> -\t\t\tnum);\n> -\n> -\tif (num == 0) {\n> -\t\tPMD_DRV_LOG(ERR,\n> -\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> -\t\t\tpf->dev_data->port_id);\n> -\t\treturn -ENOTSUP;\n> -\t}\n> -\n> -\t/* Fill in redirection table */\n> -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> -\t\tif (j == num)\n> -\t\t\tj = 0;\n> -\t\tlut = (lut << 8) | (queue[j] & ((0x1 <<\n> -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> -\t\tif ((i & 3) == 3)\n> -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> -\t}\n> +\ti40e_rss_set_lut(pf, NULL);\n> \n> \trss_info->conf.queue_num = 0;\n> \tmemset(&rss_info->conf.queue, 0, sizeof(uint16_t));\n> --\n> 2.17.1", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AECBFA0526;\n\tWed, 22 Jul 2020 07:31:10 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 547221BFE4;\n\tWed, 22 Jul 2020 07:31:09 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id DA24E1BFD1;\n Wed, 22 Jul 2020 07:31:07 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 22:31:06 -0700", "from fmsmsx602.amr.corp.intel.com ([10.18.126.82])\n by orsmga003.jf.intel.com with ESMTP; 21 Jul 2020 22:31:06 -0700", "from fmsmsx602.amr.corp.intel.com (10.18.126.82) by\n fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.1713.5; Tue, 21 Jul 2020 22:31:05 -0700", "from shsmsx154.ccr.corp.intel.com (10.239.6.54) by\n fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5\n via Frontend Transport; Tue, 21 Jul 2020 22:31:05 -0700", "from shsmsx103.ccr.corp.intel.com ([169.254.4.22]) by\n SHSMSX154.ccr.corp.intel.com ([169.254.7.32]) with mapi id 14.03.0439.000;\n Wed, 22 Jul 2020 13:31:02 +0800" ], "IronPort-SDR": [ "\n gDfOF3ivZwh2VxvSIuFfMLXNpX+oFr2SY4uU8hqonPt+CF+jJqgrZy1ePixIsqIhAo0k48mMvu\n vr2bwQoTO9cQ==", "\n w4ZUkejN/3xyRT5nhY+ytEFC7b4kdeZBaySPnUoVFLVhIB9wC+CX5Jnl5CT111vyZ/jigaT8Rg\n A+DF12Eqjm3g==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9689\"; a=\"129841857\"", "E=Sophos;i=\"5.75,381,1589266800\"; d=\"scan'208\";a=\"129841857\"", "E=Sophos;i=\"5.75,381,1589266800\"; d=\"scan'208\";a=\"284107555\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "\"Zhang, Qi Z\" <qi.z.zhang@intel.com>", "To": "\"Wang, ShougangX\" <shougangx.wang@intel.com>,\n \"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Xing, Beilei\" <beilei.xing@intel.com>, \"Guo, Jia\" <jia.guo@intel.com>,\n \"Wang, ShougangX\" <shougangx.wang@intel.com>, \"stable@dpdk.org\"\n <stable@dpdk.org>", "Thread-Topic": "[dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "Thread-Index": "AQHWXySqA49xOEYFTkiaJTOKcGomf6kTE8og", "Date": "Wed, 22 Jul 2020 05:31:01 +0000", "Message-ID": "\n <039ED4275CED7440929022BC67E7061154863E7D@SHSMSX103.ccr.corp.intel.com>", "References": "<20200715063515.9262-1-shougangx.wang@intel.com>\n <20200721054920.29749-1-shougangx.wang@intel.com>", "In-Reply-To": "<20200721054920.29749-1-shougangx.wang@intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "dlp-product": "dlpe-windows", "dlp-version": "11.2.0.6", "dlp-reaction": "no-action", "x-originating-ip": "[10.239.127.40]", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "MIME-Version": "1.0", "Subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 116469, "web_url": "https://patches.dpdk.org/comment/116469/", "msgid": "<334f916e-1aad-264f-e073-6e737e78c767@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/334f916e-1aad-264f-e073-6e737e78c767@intel.com", "date": "2020-07-22T05:50:46", "subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "submitter": { "id": 507, "url": "https://patches.dpdk.org/api/people/507/?format=api", "name": "Guo, Jia", "email": "jia.guo@intel.com" }, "content": "hi, shougang\n\nOn 7/21/2020 2:41 PM, Xie, WeiX wrote:\n> Tested-by: Zhang, XiX <xix.zhang@intel.com>\n>\n> Regards,\n> Xie Wei\n>\n>\n> -----Original Message-----\n> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shougang Wang\n> Sent: Tuesday, July 21, 2020 1:49 PM\n> To: dev@dpdk.org\n> Cc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Wang, ShougangX <shougangx.wang@intel.com>; stable@dpdk.org\n> Subject: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table\n>\n> The hash look up table(LUT) will not be initializing when starting testpmd with --disable-rss. So that some invalid queue indexes may still in the LUT. When enable RSS by creating RSS rule, some packets will not be into the valid queues.\n> This patch fixes this issue by initializing the LUT when creating an RSS rule.\n>\n> Fixes: feaae285b342 (\"net/i40e: support hash configuration in RSS flow\")\n> Cc: stable@dpdk.org\n>\n> Signed-off-by: Shougang Wang <shougangx.wang@intel.com>\n> ---\n> drivers/net/i40e/i40e_ethdev.c | 134 ++++++++++++++++-----------------\n> 1 file changed, 63 insertions(+), 71 deletions(-)\n>\n> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 393b5320f..e56543393 100644\n> --- a/drivers/net/i40e/i40e_ethdev.c\n> +++ b/drivers/net/i40e/i40e_ethdev.c\n> @@ -13070,6 +13070,55 @@ i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,\n> \treturn 0;\n> }\n> \n> +/* If conf is NULL, function will init hash LUT with default\n> +configration*/\n\n\nPlease fix the checkpatch issue here.\n\n\n> static int i40e_rss_set_lut(struct i40e_pf *pf,\n\n\nIn order to eliminate any confuse with current i40e_set_rss_lut, please \nchange the name, such as \"i40e_rss_lut_init\" or other better naming.\n\n\n> +\t\t struct i40e_rte_flow_rss_conf *conf) {\n> +\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> +\tuint32_t lut = 0;\n> +\tuint16_t j, num;\n> +\tuint32_t i;\n> +\n> +\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> +\t * It's necessary to calculate the actual PF queues that are configured.\n> +\t */\n> +\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n> +\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> +\telse\n> +\t\tnum = pf->dev_data->nb_rx_queues;\n> +\n> +\tif (conf == NULL)\n> +\t\tnum = RTE_MIN(num, I40E_MAX_Q_PER_TC);\n> +\telse\n> +\t\tnum = RTE_MIN(num, conf->conf.queue_num);\n> +\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> +\t\t\tnum);\n\n\nAlignment should match open parenthesis.\n\n\n> +\n> +\tif (num == 0) {\n> +\t\tPMD_DRV_LOG(ERR,\n> +\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> +\t\t\tpf->dev_data->port_id);\n> +\t\treturn -ENOTSUP;\n> +\t}\n> +\n> +\t/* Fill in redirection table */\n> +\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> +\t\tif (j == num)\n> +\t\t\tj = 0;\n> +\t\tif (conf == NULL)\n> +\t\t\tlut = (lut << 8) | (j & ((0x1 <<\n> +\t\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> +\t\telse\n> +\t\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> +\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> +\t\tif ((i & 3) == 3)\n> +\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> /* Write HENA register to enable hash */ static int i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf) @@ -13318,12 +13367,24 @@ static int i40e_rss_enable_hash(struct i40e_pf *pf,\n> \t\tstruct i40e_rte_flow_rss_conf *conf)\n> {\n> +\tenum rte_eth_rx_mq_mode mq_mode =\n> +pf->dev_data->dev_conf.rxmode.mq_mode;\n> \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> \tstruct i40e_rte_flow_rss_conf rss_conf;\n> +\tint ret;\n\n\nSuggest set the 0 to ret and return ret at the end of this function, so \nret could be use in all part.\n\n\n> \n> \tif (!(conf->conf.types & pf->adapter->flow_types_mask))\n> \t\treturn -ENOTSUP;\n> \n> +\t/* If the RSS is disabled before this, the LUT is uninitialized.\n> +\t * So it is necessary to initialize it here.\n> +\t */\n> +\tif (!(mq_mode & ETH_MQ_RX_RSS_FLAG) && !pf->rss_info.conf.queue_num &&\n> +\t !pf->adapter->rss_reta_updated) {\n> +\t\tret = i40e_rss_set_lut(pf, NULL);\n> +\t\tif (ret)\n> +\t\t\treturn ret;\n> +\t}\n> +\n> \tmemset(&rss_conf, 0, sizeof(rss_conf));\n> \trte_memcpy(&rss_conf, conf, sizeof(rss_conf));\n> \n> @@ -13362,39 +13423,7 @@ static int\n> i40e_rss_config_queue_region(struct i40e_pf *pf,\n> \t\tstruct i40e_rte_flow_rss_conf *conf)\n> {\n> -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> -\tuint32_t lut = 0;\n> -\tuint16_t j, num;\n> -\tuint32_t i;\n> -\n> -\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> -\t * It's necessary to calculate the actual PF queues that are configured.\n> -\t */\n> -\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n> -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> -\telse\n> -\t\tnum = pf->dev_data->nb_rx_queues;\n> -\n> -\tnum = RTE_MIN(num, conf->conf.queue_num);\n> -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> -\t\t\tnum);\n> -\n> -\tif (num == 0) {\n> -\t\tPMD_DRV_LOG(ERR,\n> -\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> -\t\t\tpf->dev_data->port_id);\n> -\t\treturn -ENOTSUP;\n> -\t}\n> -\n> -\t/* Fill in redirection table */\n> -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> -\t\tif (j == num)\n> -\t\t\tj = 0;\n> -\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> -\t\tif ((i & 3) == 3)\n> -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> -\t}\n> +\ti40e_rss_set_lut(pf, conf);\n> \n> \ti40e_rss_mark_invalid_rule(pf, conf);\n> \n> @@ -13491,46 +13520,9 @@ i40e_rss_disable_hash(struct i40e_pf *pf, static int i40e_rss_clear_queue_region(struct i40e_pf *pf) {\n> -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> -\tuint16_t queue[I40E_MAX_Q_PER_TC];\n> -\tuint32_t num_rxq, i;\n> -\tuint32_t lut = 0;\n> -\tuint16_t j, num;\n> -\n> -\tnum_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);\n> \n> -\tfor (j = 0; j < num_rxq; j++)\n> -\t\tqueue[j] = j;\n> -\n> -\t/* If both VMDQ and RSS enabled, not all of PF queues are configured.\n> -\t * It's necessary to calculate the actual PF queues that are configured.\n> -\t */\n> -\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)\n> -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> -\telse\n> -\t\tnum = pf->dev_data->nb_rx_queues;\n> -\n> -\tnum = RTE_MIN(num, num_rxq);\n> -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n> -\t\t\tnum);\n> -\n> -\tif (num == 0) {\n> -\t\tPMD_DRV_LOG(ERR,\n> -\t\t\t\"No PF queues are configured to enable RSS for port %u\",\n> -\t\t\tpf->dev_data->port_id);\n> -\t\treturn -ENOTSUP;\n> -\t}\n> -\n> -\t/* Fill in redirection table */\n> -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> -\t\tif (j == num)\n> -\t\t\tj = 0;\n> -\t\tlut = (lut << 8) | (queue[j] & ((0x1 <<\n> -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> -\t\tif ((i & 3) == 3)\n> -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> -\t}\n> +\ti40e_rss_set_lut(pf, NULL);\n\n\nNeed to check return value.\n\n\n> \n> \trss_info->conf.queue_num = 0;\n> \tmemset(&rss_info->conf.queue, 0, sizeof(uint16_t));\n> --\n> 2.17.1\n>", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 019CDA0526;\n\tWed, 22 Jul 2020 07:50:54 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9CE991BFBB;\n\tWed, 22 Jul 2020 07:50:53 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 2F16C1BFBA;\n Wed, 22 Jul 2020 07:50:50 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 22:50:49 -0700", "from jguo15x-mobl.ccr.corp.intel.com (HELO [10.67.68.153])\n ([10.67.68.153])\n by orsmga003.jf.intel.com with ESMTP; 21 Jul 2020 22:50:47 -0700" ], "IronPort-SDR": [ "\n SGvXY7PkI/d7hdBJPp/mYm+dV01I5yBDEdUcf5b7xfmL3kJ0xCqgGaBNRydktoHkud2nernn7m\n LY4ADzQg+DlQ==", "\n 9e9da1m8YG+lsByGuawj9mJmYZOncYCKoYWDTqu5MOgkuUtjjX9ArkZn6VyWBzsZjlSy4HzDmo\n gD0gvdh3C1NQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9689\"; a=\"149440517\"", "E=Sophos;i=\"5.75,381,1589266800\"; d=\"scan'208\";a=\"149440517\"", "E=Sophos;i=\"5.75,381,1589266800\"; d=\"scan'208\";a=\"284111485\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "To": "\"Xie, WeiX\" <weix.xie@intel.com>,\n \"Wang, ShougangX\" <shougangx.wang@intel.com>, \"dev@dpdk.org\" <dev@dpdk.org>", "Cc": "\"Xing, Beilei\" <beilei.xing@intel.com>,\n \"stable@dpdk.org\" <stable@dpdk.org>", "References": "<20200715063515.9262-1-shougangx.wang@intel.com>\n <20200721054920.29749-1-shougangx.wang@intel.com>\n <6FD6A7610D20924F885A4ECF34E8AC910463D264@CDSMSX102.ccr.corp.intel.com>", "From": "Jeff Guo <jia.guo@intel.com>", "Message-ID": "<334f916e-1aad-264f-e073-6e737e78c767@intel.com>", "Date": "Wed, 22 Jul 2020 13:50:46 +0800", "User-Agent": "Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101\n Thunderbird/68.10.0", "MIME-Version": "1.0", "In-Reply-To": "\n <6FD6A7610D20924F885A4ECF34E8AC910463D264@CDSMSX102.ccr.corp.intel.com>", "Content-Type": "text/plain; charset=utf-8; format=flowed", "Content-Transfer-Encoding": "7bit", "Content-Language": "en-US", "Subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 116470, "web_url": "https://patches.dpdk.org/comment/116470/", "msgid": "<BYAPR11MB3477B09C896A40E914B4579F88790@BYAPR11MB3477.namprd11.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/BYAPR11MB3477B09C896A40E914B4579F88790@BYAPR11MB3477.namprd11.prod.outlook.com", "date": "2020-07-22T06:20:41", "subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "submitter": { "id": 1418, "url": "https://patches.dpdk.org/api/people/1418/?format=api", "name": "Shougang Wang", "email": "shougangx.wang@intel.com" }, "content": "Hi, Qi\n\n> -----Original Message-----\n> From: Zhang, Qi Z <qi.z.zhang@intel.com>\n> Sent: Wednesday, July 22, 2020 1:31 PM\n> To: Wang, ShougangX <shougangx.wang@intel.com>; dev@dpdk.org\n> Cc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia <jia.guo@intel.com>; Wang,\n> ShougangX <shougangx.wang@intel.com>; stable@dpdk.org\n> Subject: RE: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table\n> \n> \n> \n> > -----Original Message-----\n> > From: dev <dev-bounces@dpdk.org> On Behalf Of Shougang Wang\n> > Sent: Tuesday, July 21, 2020 1:49 PM\n> > To: dev@dpdk.org\n> > Cc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia\n> > <jia.guo@intel.com>; Wang, ShougangX <shougangx.wang@intel.com>;\n> > stable@dpdk.org\n> > Subject: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up\n> > table\n> >\n> > The hash look up table(LUT) will not be initializing when starting\n> > testpmd with --disable-rss. So that some invalid queue indexes may\n> > still in the LUT. When enable RSS by creating RSS rule, some packets will not\n> be into the valid queues.\n> > This patch fixes this issue by initializing the LUT when creating an RSS rule.\n> \n> Could you explain why you only initialize the LUT when creating an RSS rule\n> but not at dev_init or dev_start?\nIt is good to initialize the LUT at dev_start, I will fix it.\n\n> What if user configure LUT table before create a RSS rule? Does that mean\n> the LUT table will be flushed?\nYes.\n\nThanks.\nShougang", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 92384A0526;\n\tWed, 22 Jul 2020 08:20:51 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4A6E21BFBA;\n\tWed, 22 Jul 2020 08:20:50 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id B87B3199BC;\n Wed, 22 Jul 2020 08:20:48 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 23:20:47 -0700", "from orsmsx603.amr.corp.intel.com ([10.22.229.16])\n by fmsmga002.fm.intel.com with ESMTP; 21 Jul 2020 23:20:47 -0700", "from orsmsx603.amr.corp.intel.com (10.22.229.16) by\n ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id\n 15.1.1713.5; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;\n dkim=pass header.d=intel.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com;\n s=selector2-intel-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=BtpgWq66QBKDRUjDKs4IE2vKnR2shgcwdGihuAGrUOk=;\n b=mUUaTILP+Zr0dck6VqmWtgQtmGtGJeZFklhJCHDswHsFHleSbZ8ZkErajlAyHsekR0yZfWwUWOSx3g+tsM+awWAwCL3wTkFfJryBHk3mnHxQpzfJQTsYEW66VVlwtVqmaVvnnoK8NmFS845kzlCl6GfD1M4TNDF4Zi28WTkaucc=", "From": "\"Wang, ShougangX\" <shougangx.wang@intel.com>", "To": "\"Zhang, Qi Z\" <qi.z.zhang@intel.com>, \"dev@dpdk.org\" <dev@dpdk.org>", "CC": "\"Xing, Beilei\" <beilei.xing@intel.com>, \"Guo, Jia\" <jia.guo@intel.com>,\n \"stable@dpdk.org\" <stable@dpdk.org>, \"Di, ChenxuX\" <chenxux.di@intel.com>", "Thread-Topic": "[dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "Thread-Index": "AQHWXySgbaCuNyO260KHkTx8V6T7nKkTFEiAgAAKb4A=", "Date": "Wed, 22 Jul 2020 06:20:41 +0000", "Message-ID": "\n <BYAPR11MB3477B09C896A40E914B4579F88790@BYAPR11MB3477.namprd11.prod.outlook.com>", "References": "<20200715063515.9262-1-shougangx.wang@intel.com>\n <20200721054920.29749-1-shougangx.wang@intel.com>\n <039ED4275CED7440929022BC67E7061154863E7D@SHSMSX103.ccr.corp.intel.com>", "In-Reply-To": "\n <039ED4275CED7440929022BC67E7061154863E7D@SHSMSX103.ccr.corp.intel.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": "intel.com; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "BYAPR11MB3477.namprd11.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 381169d8-46dd-499d-664e-08d82e075bfc", "X-MS-Exchange-CrossTenant-originalarrivaltime": "22 Jul 2020 06:20:41.3823 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "46c98d88-e344-4ed4-8496-4ed7712e255d", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n 7NoNVBsBqGLMmDzMKVBp+xcNrdvagWkCsqFilfYuPTfZiAVwiDwRBZP1kjiRU9knCbjlmqb+ECEJ2oJRLrE33CW9I/sTswVDaJhWj14LIlI=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR11MB3400", "X-OriginatorOrg": "intel.com", "Subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "addressed": null }, { "id": 116472, "web_url": "https://patches.dpdk.org/comment/116472/", "msgid": "<BYAPR11MB3477353AB01BE785DCD9F52D88790@BYAPR11MB3477.namprd11.prod.outlook.com>", "list_archive_url": "https://inbox.dpdk.org/dev/BYAPR11MB3477353AB01BE785DCD9F52D88790@BYAPR11MB3477.namprd11.prod.outlook.com", "date": "2020-07-22T06:39:49", "subject": "Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table", "submitter": { "id": 1418, "url": "https://patches.dpdk.org/api/people/1418/?format=api", "name": "Shougang Wang", "email": "shougangx.wang@intel.com" }, "content": "Hi, Jeff\n\n> -----Original Message-----\n> From: Guo, Jia <jia.guo@intel.com>\n> Sent: Wednesday, July 22, 2020 1:51 PM\n> To: Xie, WeiX <weix.xie@intel.com>; Wang, ShougangX\n> <shougangx.wang@intel.com>; dev@dpdk.org\n> Cc: Xing, Beilei <beilei.xing@intel.com>; stable@dpdk.org\n> Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up table\n> \n> hi, shougang\n> \n> On 7/21/2020 2:41 PM, Xie, WeiX wrote:\n> > Tested-by: Zhang, XiX <xix.zhang@intel.com>\n> >\n> > Regards,\n> > Xie Wei\n> >\n> >\n> > -----Original Message-----\n> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shougang Wang\n> > Sent: Tuesday, July 21, 2020 1:49 PM\n> > To: dev@dpdk.org\n> > Cc: Xing, Beilei <beilei.xing@intel.com>; Guo, Jia\n> > <jia.guo@intel.com>; Wang, ShougangX <shougangx.wang@intel.com>;\n> > stable@dpdk.org\n> > Subject: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect hash look up\n> > table\n> >\n> > The hash look up table(LUT) will not be initializing when starting testpmd\n> with --disable-rss. So that some invalid queue indexes may still in the LUT.\n> When enable RSS by creating RSS rule, some packets will not be into the valid\n> queues.\n> > This patch fixes this issue by initializing the LUT when creating an RSS rule.\n> >\n> > Fixes: feaae285b342 (\"net/i40e: support hash configuration in RSS\n> > flow\")\n> > Cc: stable@dpdk.org\n> >\n> > Signed-off-by: Shougang Wang <shougangx.wang@intel.com>\n> > ---\n> > drivers/net/i40e/i40e_ethdev.c | 134 ++++++++++++++++-----------------\n> > 1 file changed, 63 insertions(+), 71 deletions(-)\n> >\n> > diff --git a/drivers/net/i40e/i40e_ethdev.c\n> > b/drivers/net/i40e/i40e_ethdev.c index 393b5320f..e56543393 100644\n> > --- a/drivers/net/i40e/i40e_ethdev.c\n> > +++ b/drivers/net/i40e/i40e_ethdev.c\n> > @@ -13070,6 +13070,55 @@ i40e_rss_conf_init(struct\n> i40e_rte_flow_rss_conf *out,\n> > \treturn 0;\n> > }\n> >\n> > +/* If conf is NULL, function will init hash LUT with default\n> > +configration*/\n> \n> \n> Please fix the checkpatch issue here.\n> \n> \n> > static int i40e_rss_set_lut(struct i40e_pf *pf,\n> \n> \n> In order to eliminate any confuse with current i40e_set_rss_lut, please\n> change the name, such as \"i40e_rss_lut_init\" or other better naming.\n> \nQi also gave me some comments. I will define i40e_rss_lut_init() to initialize the LUT.\n\n> \n> > +\t\t struct i40e_rte_flow_rss_conf *conf) {\n> > +\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> > +\tuint32_t lut = 0;\n> > +\tuint16_t j, num;\n> > +\tuint32_t i;\n> > +\n> > +\t/* If both VMDQ and RSS enabled, not all of PF queues are\n> configured.\n> > +\t * It's necessary to calculate the actual PF queues that are configured.\n> > +\t */\n> > +\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> > +\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> > +\telse\n> > +\t\tnum = pf->dev_data->nb_rx_queues;\n> > +\n> > +\tif (conf == NULL)\n> > +\t\tnum = RTE_MIN(num, I40E_MAX_Q_PER_TC);\n> > +\telse\n> > +\t\tnum = RTE_MIN(num, conf->conf.queue_num);\n> > +\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are\n> configured\",\n> > +\t\t\tnum);\n> \n> \n> Alignment should match open parenthesis.\n> \n> \n> > +\n> > +\tif (num == 0) {\n> > +\t\tPMD_DRV_LOG(ERR,\n> > +\t\t\t\"No PF queues are configured to enable RSS for\n> port %u\",\n> > +\t\t\tpf->dev_data->port_id);\n> > +\t\treturn -ENOTSUP;\n> > +\t}\n> > +\n> > +\t/* Fill in redirection table */\n> > +\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> > +\t\tif (j == num)\n> > +\t\t\tj = 0;\n> > +\t\tif (conf == NULL)\n> > +\t\t\tlut = (lut << 8) | (j & ((0x1 <<\n> > +\t\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> > +\t\telse\n> > +\t\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> > +\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> > +\t\tif ((i & 3) == 3)\n> > +\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> > +\t}\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > /* Write HENA register to enable hash */ static int\n> i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf\n> *rss_conf) @@ -13318,12 +13367,24 @@ static int\n> i40e_rss_enable_hash(struct i40e_pf *pf,\n> > \t\tstruct i40e_rte_flow_rss_conf *conf)\n> > {\n> > +\tenum rte_eth_rx_mq_mode mq_mode =\n> > +pf->dev_data->dev_conf.rxmode.mq_mode;\n> > \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> > \tstruct i40e_rte_flow_rss_conf rss_conf;\n> > +\tint ret;\n> \n> \n> Suggest set the 0 to ret and return ret at the end of this function, so\n> ret could be use in all part.\n> \n> \n> >\n> > \tif (!(conf->conf.types & pf->adapter->flow_types_mask))\n> > \t\treturn -ENOTSUP;\n> >\n> > +\t/* If the RSS is disabled before this, the LUT is uninitialized.\n> > +\t * So it is necessary to initialize it here.\n> > +\t */\n> > +\tif (!(mq_mode & ETH_MQ_RX_RSS_FLAG) && !pf-\n> >rss_info.conf.queue_num &&\n> > +\t !pf->adapter->rss_reta_updated) {\n> > +\t\tret = i40e_rss_set_lut(pf, NULL);\n> > +\t\tif (ret)\n> > +\t\t\treturn ret;\n> > +\t}\n> > +\n> > \tmemset(&rss_conf, 0, sizeof(rss_conf));\n> > \trte_memcpy(&rss_conf, conf, sizeof(rss_conf));\n> >\n> > @@ -13362,39 +13423,7 @@ static int\n> > i40e_rss_config_queue_region(struct i40e_pf *pf,\n> > \t\tstruct i40e_rte_flow_rss_conf *conf)\n> > {\n> > -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> > -\tuint32_t lut = 0;\n> > -\tuint16_t j, num;\n> > -\tuint32_t i;\n> > -\n> > -\t/* If both VMDQ and RSS enabled, not all of PF queues are\n> configured.\n> > -\t * It's necessary to calculate the actual PF queues that are configured.\n> > -\t */\n> > -\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> > -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> > -\telse\n> > -\t\tnum = pf->dev_data->nb_rx_queues;\n> > -\n> > -\tnum = RTE_MIN(num, conf->conf.queue_num);\n> > -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are\n> configured\",\n> > -\t\t\tnum);\n> > -\n> > -\tif (num == 0) {\n> > -\t\tPMD_DRV_LOG(ERR,\n> > -\t\t\t\"No PF queues are configured to enable RSS for\n> port %u\",\n> > -\t\t\tpf->dev_data->port_id);\n> > -\t\treturn -ENOTSUP;\n> > -\t}\n> > -\n> > -\t/* Fill in redirection table */\n> > -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> > -\t\tif (j == num)\n> > -\t\t\tj = 0;\n> > -\t\tlut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<\n> > -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> > -\t\tif ((i & 3) == 3)\n> > -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> > -\t}\n> > +\ti40e_rss_set_lut(pf, conf);\n> >\n> > \ti40e_rss_mark_invalid_rule(pf, conf);\n> >\n> > @@ -13491,46 +13520,9 @@ i40e_rss_disable_hash(struct i40e_pf *pf,\n> static int i40e_rss_clear_queue_region(struct i40e_pf *pf) {\n> > -\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n> > \tstruct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;\n> > -\tuint16_t queue[I40E_MAX_Q_PER_TC];\n> > -\tuint32_t num_rxq, i;\n> > -\tuint32_t lut = 0;\n> > -\tuint16_t j, num;\n> > -\n> > -\tnum_rxq = RTE_MIN(pf->dev_data->nb_rx_queues,\n> I40E_MAX_Q_PER_TC);\n> >\n> > -\tfor (j = 0; j < num_rxq; j++)\n> > -\t\tqueue[j] = j;\n> > -\n> > -\t/* If both VMDQ and RSS enabled, not all of PF queues are\n> configured.\n> > -\t * It's necessary to calculate the actual PF queues that are configured.\n> > -\t */\n> > -\tif (pf->dev_data->dev_conf.rxmode.mq_mode &\n> ETH_MQ_RX_VMDQ_FLAG)\n> > -\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n> > -\telse\n> > -\t\tnum = pf->dev_data->nb_rx_queues;\n> > -\n> > -\tnum = RTE_MIN(num, num_rxq);\n> > -\tPMD_DRV_LOG(INFO, \"Max of contiguous %u PF queues are\n> configured\",\n> > -\t\t\tnum);\n> > -\n> > -\tif (num == 0) {\n> > -\t\tPMD_DRV_LOG(ERR,\n> > -\t\t\t\"No PF queues are configured to enable RSS for\n> port %u\",\n> > -\t\t\tpf->dev_data->port_id);\n> > -\t\treturn -ENOTSUP;\n> > -\t}\n> > -\n> > -\t/* Fill in redirection table */\n> > -\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n> > -\t\tif (j == num)\n> > -\t\t\tj = 0;\n> > -\t\tlut = (lut << 8) | (queue[j] & ((0x1 <<\n> > -\t\t\thw->func_caps.rss_table_entry_width) - 1));\n> > -\t\tif ((i & 3) == 3)\n> > -\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n> > -\t}\n> > +\ti40e_rss_set_lut(pf, NULL);\n> \n> \n> Need to check return value.\n> \n> \n> >\n> > \trss_info->conf.queue_num = 0;\n> > \tmemset(&rss_info->conf.queue, 0, sizeof(uint16_t));\n> > --\n> > 2.17.1\n> >", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 145C7A0526;\n\tWed, 22 Jul 2020 08:39:57 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AA2B81BFD1;\n\tWed, 22 Jul 2020 08:39:55 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id A595711A2;\n Wed, 22 Jul 2020 08:39:53 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 21 Jul 2020 23:39:52 -0700", "from orsmsx109.amr.corp.intel.com ([10.22.240.7])\n by orsmga002.jf.intel.com with ESMTP; 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