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GET /api/patches/7380/?format=api
{ "id": 7380, "url": "https://patches.dpdk.org/api/patches/7380/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443826867-21004-3-git-send-email-declan.doherty@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443826867-21004-3-git-send-email-declan.doherty@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443826867-21004-3-git-send-email-declan.doherty@intel.com", "date": "2015-10-02T23:01:03", "name": "[dpdk-dev,2/6] qat_crypto_pmd: Addition of a new QAT DPDK PMD.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "014fcff659fbdceb52bc06bc715e6b557a71b01b", "submitter": { "id": 11, "url": "https://patches.dpdk.org/api/people/11/?format=api", "name": "Doherty, Declan", "email": "declan.doherty@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443826867-21004-3-git-send-email-declan.doherty@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7380/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7380/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5E2E28E80;\n\tSat, 3 Oct 2015 00:54:21 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 3590E8E7E\n\tfor <dev@dpdk.org>; Sat, 3 Oct 2015 00:54:19 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga103.jf.intel.com with ESMTP; 02 Oct 2015 15:54:18 -0700", "from unknown (HELO dwdohert-dpdk-fedora-20.ir.intel.com)\n\t([163.33.213.96])\n\tby orsmga001.jf.intel.com with ESMTP; 02 Oct 2015 15:54:17 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,625,1437462000\"; d=\"scan'208\";a=\"783186043\"", "From": "Declan Doherty <declan.doherty@intel.com>", "To": "dev@dpdk.org", "Date": "Sat, 3 Oct 2015 00:01:03 +0100", "Message-Id": "<1443826867-21004-3-git-send-email-declan.doherty@intel.com>", "X-Mailer": "git-send-email 2.4.3", "In-Reply-To": "<1443826867-21004-1-git-send-email-declan.doherty@intel.com>", "References": "<1443826867-21004-1-git-send-email-declan.doherty@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/6] qat_crypto_pmd: Addition of a new QAT DPDK\n\tPMD.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: John Griffin <john.griffin@intel.com>\n\nCo-authored-by: Des O Dea <des.j.o.dea@intel.com>\nCo-authored-by: Fiona Trahe <fiona.trahe@intel.com>\n\nThis patch adds a PMD for the Intel Quick Assist Technology DH895xxC\nhardware accelerator.\n\nThis patch depends on a QAT PF driver which may be downloaded from\n01.org (please see the file docs/guides/cryptodevs/qat.rst contained in\nthis a subsquent patch in this patchset).\n\nThis is a limited patchset which has support for a chain of cipher and\nhash the following algorithms are supported:\n\nCipher algorithms:\n - RTE_CRYPTO_SYM_CIPHER_AES128_CBC\n - RTE_CRYPTO_SYM_CIPHER_AES256_CBC\n - RTE_CRYPTO_SYM_CIPHER_AES512_CBC\n\nHash algorithms:\n - RTE_CRYPTO_SYM_HASH_SHA1_HMAC\n - RTE_CRYPTO_SYM_HASH_SHA256_HMAC\n - RTE_CRYPTO_SYM_HASH_SHA512_HMAC\n\nSome limitation on this patchset which shall be contributed in a\nsubsequent release:\n - Chained mbufs are not supported.\n - Hash only is not supported.\n - Cipher only is not supported.\n - Only in-place is currently supported (destination address is\n the same as source address).\n - Only supports session-oriented API implementation (session-less\n APIs are not supported).\n\nSigned-off-by: Declan Doherty <declan.doherty@intel.com>\n---\n config/common_bsdapp | 16 +-\n config/common_linuxapp | 14 +\n drivers/Makefile | 1 +\n drivers/crypto/Makefile | 37 ++\n drivers/crypto/qat/Makefile | 63 +++\n .../qat/qat_adf/adf_transport_access_macros.h | 173 +++++++\n drivers/crypto/qat/qat_adf/icp_qat_fw.h | 316 +++++++++++\n drivers/crypto/qat/qat_adf/icp_qat_fw_la.h | 404 +++++++++++++++\n drivers/crypto/qat/qat_adf/icp_qat_hw.h | 306 +++++++++++\n drivers/crypto/qat/qat_adf/qat_algs.h | 125 +++++\n drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 576 +++++++++++++++++++++\n drivers/crypto/qat/qat_crypto.c | 505 ++++++++++++++++++\n drivers/crypto/qat/qat_crypto.h | 111 ++++\n drivers/crypto/qat/qat_logs.h | 78 +++\n drivers/crypto/qat/qat_qp.c | 372 +++++++++++++\n drivers/crypto/qat/rte_pmd_qat_version.map | 5 +\n drivers/crypto/qat/rte_qat_cryptodev.c | 130 +++++\n mk/rte.app.mk | 3 +\n 18 files changed, 3234 insertions(+), 1 deletion(-)\n create mode 100644 drivers/crypto/Makefile\n create mode 100644 drivers/crypto/qat/Makefile\n create mode 100644 drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\n create mode 100644 drivers/crypto/qat/qat_adf/icp_qat_fw.h\n create mode 100644 drivers/crypto/qat/qat_adf/icp_qat_fw_la.h\n create mode 100644 drivers/crypto/qat/qat_adf/icp_qat_hw.h\n create mode 100644 drivers/crypto/qat/qat_adf/qat_algs.h\n create mode 100644 drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n create mode 100644 drivers/crypto/qat/qat_crypto.c\n create mode 100644 drivers/crypto/qat/qat_crypto.h\n create mode 100644 drivers/crypto/qat/qat_logs.h\n create mode 100644 drivers/crypto/qat/qat_qp.c\n create mode 100644 drivers/crypto/qat/rte_pmd_qat_version.map\n create mode 100644 drivers/crypto/qat/rte_qat_cryptodev.c", "diff": "diff --git a/config/common_bsdapp b/config/common_bsdapp\nindex 3313a8e..a9ac5cb 100644\n--- a/config/common_bsdapp\n+++ b/config/common_bsdapp\n@@ -1,6 +1,6 @@\n # BSD LICENSE\n #\n-# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n # All rights reserved.\n #\n # Redistribution and use in source and binary forms, with or without\n@@ -154,6 +154,20 @@ CONFIG_RTE_LIBRTE_CRYPTODEV_DEBUG=y\n CONFIG_RTE_MAX_CRYPTOPORTS=32\n \n #\n+# Compile PMD for QuickAssist based devices\n+#\n+CONFIG_RTE_LIBRTE_PMD_QAT=y\n+CONFIG_RTE_LIBRTE_QAT_DEBUG_INIT=n\n+CONFIG_RTE_LIBRTE_QAT_DEBUG_TX=y\n+CONFIG_RTE_LIBRTE_QAT_DEBUG_RX=y\n+CONFIG_RTE_LIBRTE_QAT_DEBUG_DRIVER=y\n+#\n+# Number of sessions to create in the session memory pool\n+# on a single QuickAssist device.\n+#\n+CONFIG_RTE_MAX_QAT_SESSIONS=200\n+\n+#\n # Support NIC bypass logic\n #\n CONFIG_RTE_NIC_BYPASS=n\ndiff --git a/config/common_linuxapp b/config/common_linuxapp\nindex 4ba0299..be38822 100644\n--- a/config/common_linuxapp\n+++ b/config/common_linuxapp\n@@ -153,6 +153,20 @@ CONFIG_RTE_CRYPTO_MAX_DEVS=64\n CONFIG_RTE_CRYPTO_MAX_XFORM_CHAIN_LENGTH=2\n \n #\n+# Compile PMD for QuickAssist based devices\n+#\n+CONFIG_RTE_LIBRTE_PMD_QAT=y\n+CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_INIT=n\n+CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_TX=n\n+CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_RX=n\n+CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_DRIVER=n\n+#\n+# Number of sessions to create in the session memory pool\n+# on a single QuickAssist device.\n+#\n+CONFIG_RTE_LIBRTE_PMD_QAT_MAX_SESSIONS=2048\n+\n+#\n # Support NIC bypass logic\n #\n CONFIG_RTE_NIC_BYPASS=n\ndiff --git a/drivers/Makefile b/drivers/Makefile\nindex b60eb5e..6ec67f6 100644\n--- a/drivers/Makefile\n+++ b/drivers/Makefile\n@@ -32,5 +32,6 @@\n include $(RTE_SDK)/mk/rte.vars.mk\n \n DIRS-y += net\n+DIRS-y += crypto\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nnew file mode 100644\nindex 0000000..9529f30\n--- /dev/null\n+++ b/drivers/crypto/Makefile\n@@ -0,0 +1,37 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+# All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat\n+\n+include $(RTE_SDK)/mk/rte.sharelib.mk\n+include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/crypto/qat/Makefile b/drivers/crypto/qat/Makefile\nnew file mode 100644\nindex 0000000..e027ff9\n--- /dev/null\n+++ b/drivers/crypto/qat/Makefile\n@@ -0,0 +1,63 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2015 Intel Corporation. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_qat.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+\n+# external library include paths\n+CFLAGS += -I$(SRCDIR)/qat_adf\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_crypto.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_qp.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += qat_adf/qat_algs_build_desc.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += rte_qat_cryptodev.c\n+\n+# export include files\n+SYMLINK-y-include +=\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_qat_version.map\n+\n+# library dependencies\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += lib/librte_eal\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += lib/librte_mbuf\n+DEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += lib/librte_cryptodev\n+\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\nnew file mode 100644\nindex 0000000..d2b79c6\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/adf_transport_access_macros.h\n@@ -0,0 +1,173 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Intel Corporation nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+#ifndef ADF_TRANSPORT_ACCESS_MACROS_H\n+#define ADF_TRANSPORT_ACCESS_MACROS_H\n+\n+/* CSR write macro */\n+#define ADF_CSR_WR(csrAddr, csrOffset, val) \\\n+\t(void)((*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)) = (val)))\n+\n+/* CSR read macro */\n+#define ADF_CSR_RD(csrAddr, csrOffset) \\\n+\t(*((volatile uint32_t *)(((uint8_t *)csrAddr) + csrOffset)))\n+\n+#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL\n+#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL\n+#define ADF_RING_CSR_RING_CONFIG 0x000\n+#define ADF_RING_CSR_RING_LBASE 0x040\n+#define ADF_RING_CSR_RING_UBASE 0x080\n+#define ADF_RING_CSR_RING_HEAD 0x0C0\n+#define ADF_RING_CSR_RING_TAIL 0x100\n+#define ADF_RING_CSR_E_STAT 0x14C\n+#define ADF_RING_CSR_INT_SRCSEL 0x174\n+#define ADF_RING_CSR_INT_SRCSEL_2 0x178\n+#define ADF_RING_CSR_INT_COL_EN 0x17C\n+#define ADF_RING_CSR_INT_COL_CTL 0x180\n+#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184\n+#define ADF_RING_CSR_INT_COL_CTL_ENABLE\t0x80000000\n+#define ADF_RING_BUNDLE_SIZE 0x1000\n+#define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A\n+#define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05\n+#define ADF_COALESCING_MIN_TIME 0x1FF\n+#define ADF_COALESCING_MAX_TIME 0xFFFFF\n+#define ADF_COALESCING_DEF_TIME 0x27FF\n+#define ADF_RING_NEAR_WATERMARK_512 0x08\n+#define ADF_RING_NEAR_WATERMARK_0 0x00\n+#define ADF_RING_EMPTY_SIG 0x7F7F7F7F\n+\n+/* Valid internal ring size values */\n+#define ADF_RING_SIZE_128 0x01\n+#define ADF_RING_SIZE_256 0x02\n+#define ADF_RING_SIZE_512 0x03\n+#define ADF_RING_SIZE_4K 0x06\n+#define ADF_RING_SIZE_16K 0x08\n+#define ADF_RING_SIZE_4M 0x10\n+#define ADF_MIN_RING_SIZE ADF_RING_SIZE_128\n+#define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M\n+#define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K\n+\n+#define ADF_NUM_BUNDLES_PER_DEV 1\n+#define ADF_NUM_SYM_QPS_PER_BUNDLE 2\n+\n+/* Valid internal msg size values */\n+#define ADF_MSG_SIZE_32 0x01\n+#define ADF_MSG_SIZE_64 0x02\n+#define ADF_MSG_SIZE_128 0x04\n+#define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32\n+#define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128\n+\n+/* Size to bytes conversion macros for ring and msg size values */\n+#define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)\n+#define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)\n+#define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)\n+#define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)\n+\n+/* Minimum ring bufer size for memory allocation */\n+#define ADF_RING_SIZE_BYTES_MIN(SIZE) ((SIZE < ADF_RING_SIZE_4K) ? \\\n+\t\t\t\tADF_RING_SIZE_4K : SIZE)\n+#define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)\n+#define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \\\n+\t\t\t\tSIZE) & ~0x4)\n+/* Max outstanding requests */\n+#define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \\\n+\t((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)\n+#define BUILD_RING_CONFIG(size)\t\\\n+\t((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \\\n+\t| (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \\\n+\t| size)\n+#define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \\\n+\t((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM)\t\\\n+\t| (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \\\n+\t| size)\n+#define BUILD_RING_BASE_ADDR(addr, size) \\\n+\t((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))\n+#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \\\n+\tADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_RING_HEAD + (ring << 2))\n+#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \\\n+\tADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_RING_TAIL + (ring << 2))\n+#define READ_CSR_E_STAT(csr_base_addr, bank) \\\n+\tADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_E_STAT)\n+#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\tADF_RING_CSR_RING_CONFIG + (ring << 2), value)\n+#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \\\n+do { \\\n+\tuint32_t l_base = 0, u_base = 0; \\\n+\tl_base = (uint32_t)(value & 0xFFFFFFFF); \\\n+\tu_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\tADF_RING_CSR_RING_LBASE + (ring << 2), l_base);\t\\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\tADF_RING_CSR_RING_UBASE + (ring << 2), u_base);\t\\\n+} while (0)\n+#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\tADF_RING_CSR_RING_HEAD + (ring << 2), value)\n+#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\tADF_RING_CSR_RING_TAIL + (ring << 2), value)\n+#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \\\n+do { \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0);\t\\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \\\n+} while (0)\n+#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_INT_COL_EN, value)\n+#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_INT_COL_CTL, \\\n+\t\t\tADF_RING_CSR_INT_COL_CTL_ENABLE | value)\n+#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \\\n+\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\t\t\tADF_RING_CSR_INT_FLAG_AND_COL, value)\n+#endif\ndiff --git a/drivers/crypto/qat/qat_adf/icp_qat_fw.h b/drivers/crypto/qat/qat_adf/icp_qat_fw.h\nnew file mode 100644\nindex 0000000..cc96d45\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/icp_qat_fw.h\n@@ -0,0 +1,316 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Intel Corporation nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+#ifndef _ICP_QAT_FW_H_\n+#define _ICP_QAT_FW_H_\n+#include <linux/types.h>\n+#include \"icp_qat_hw.h\"\n+\n+#define QAT_FIELD_SET(flags, val, bitpos, mask) \\\n+{ (flags) = (((flags) & (~((mask) << (bitpos)))) | \\\n+\t\t(((val) & (mask)) << (bitpos))) ; }\n+\n+#define QAT_FIELD_GET(flags, bitpos, mask) \\\n+\t(((flags) >> (bitpos)) & (mask))\n+\n+#define ICP_QAT_FW_REQ_DEFAULT_SZ 128\n+#define ICP_QAT_FW_RESP_DEFAULT_SZ 32\n+#define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8\n+#define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF\n+#define ICP_QAT_FW_NUM_LONGWORDS_1 1\n+#define ICP_QAT_FW_NUM_LONGWORDS_2 2\n+#define ICP_QAT_FW_NUM_LONGWORDS_3 3\n+#define ICP_QAT_FW_NUM_LONGWORDS_4 4\n+#define ICP_QAT_FW_NUM_LONGWORDS_5 5\n+#define ICP_QAT_FW_NUM_LONGWORDS_6 6\n+#define ICP_QAT_FW_NUM_LONGWORDS_7 7\n+#define ICP_QAT_FW_NUM_LONGWORDS_10 10\n+#define ICP_QAT_FW_NUM_LONGWORDS_13 13\n+#define ICP_QAT_FW_NULL_REQ_SERV_ID 1\n+\n+enum icp_qat_fw_comn_resp_serv_id {\n+\tICP_QAT_FW_COMN_RESP_SERV_NULL,\n+\tICP_QAT_FW_COMN_RESP_SERV_CPM_FW,\n+\tICP_QAT_FW_COMN_RESP_SERV_DELIMITER\n+};\n+\n+enum icp_qat_fw_comn_request_id {\n+\tICP_QAT_FW_COMN_REQ_NULL = 0,\n+\tICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,\n+\tICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,\n+\tICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,\n+\tICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,\n+\tICP_QAT_FW_COMN_REQ_DELIMITER\n+};\n+\n+struct icp_qat_fw_comn_req_hdr_cd_pars {\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t content_desc_addr;\n+\t\t\tuint16_t content_desc_resrvd1;\n+\t\t\tuint8_t content_desc_params_sz;\n+\t\t\tuint8_t content_desc_hdr_resrvd2;\n+\t\t\tuint32_t content_desc_resrvd3;\n+\t\t} s;\n+\t\tstruct {\n+\t\t\tuint32_t serv_specif_fields[4];\n+\t\t} s1;\n+\t} u;\n+};\n+\n+struct icp_qat_fw_comn_req_mid {\n+\tuint64_t opaque_data;\n+\tuint64_t src_data_addr;\n+\tuint64_t dest_data_addr;\n+\tuint32_t src_length;\n+\tuint32_t dst_length;\n+};\n+\n+struct icp_qat_fw_comn_req_cd_ctrl {\n+\tuint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];\n+};\n+\n+struct icp_qat_fw_comn_req_hdr {\n+\tuint8_t resrvd1;\n+\tuint8_t service_cmd_id;\n+\tuint8_t service_type;\n+\tuint8_t hdr_flags;\n+\tuint16_t serv_specif_flags;\n+\tuint16_t comn_req_flags;\n+};\n+\n+struct icp_qat_fw_comn_req_rqpars {\n+\tuint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];\n+};\n+\n+struct icp_qat_fw_comn_req {\n+\tstruct icp_qat_fw_comn_req_hdr comn_hdr;\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;\n+\tstruct icp_qat_fw_comn_req_mid comn_mid;\n+\tstruct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;\n+\tstruct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;\n+};\n+\n+struct icp_qat_fw_comn_error {\n+\tuint8_t xlat_err_code;\n+\tuint8_t cmp_err_code;\n+};\n+\n+struct icp_qat_fw_comn_resp_hdr {\n+\tuint8_t resrvd1;\n+\tuint8_t service_id;\n+\tuint8_t response_type;\n+\tuint8_t hdr_flags;\n+\tstruct icp_qat_fw_comn_error comn_error;\n+\tuint8_t comn_status;\n+\tuint8_t cmd_id;\n+};\n+\n+struct icp_qat_fw_comn_resp {\n+\tstruct icp_qat_fw_comn_resp_hdr comn_hdr;\n+\tuint64_t opaque_data;\n+\tuint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];\n+};\n+\n+#define ICP_QAT_FW_COMN_REQ_FLAG_SET 1\n+#define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0\n+#define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7\n+#define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1\n+#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F\n+\n+#define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \\\n+\ticp_qat_fw_comn_req_hdr_t.service_type\n+\n+#define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \\\n+\ticp_qat_fw_comn_req_hdr_t.service_type = val\n+\n+#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \\\n+\ticp_qat_fw_comn_req_hdr_t.service_cmd_id\n+\n+#define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \\\n+\ticp_qat_fw_comn_req_hdr_t.service_cmd_id = val\n+\n+#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)\n+\n+#define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)\n+\n+#define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \\\n+\tQAT_FIELD_GET(hdr_flags, \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_MASK)\n+\n+#define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \\\n+\t(hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)\n+\n+#define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \\\n+\tQAT_FIELD_SET((hdr_t.hdr_flags), (val), \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \\\n+\tICP_QAT_FW_COMN_VALID_FLAG_MASK)\n+\n+#define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \\\n+\t(((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \\\n+\t ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)\n+\n+#define QAT_COMN_PTR_TYPE_BITPOS 0\n+#define QAT_COMN_PTR_TYPE_MASK 0x1\n+#define QAT_COMN_CD_FLD_TYPE_BITPOS 1\n+#define QAT_COMN_CD_FLD_TYPE_MASK 0x1\n+#define QAT_COMN_PTR_TYPE_FLAT 0x0\n+#define QAT_COMN_PTR_TYPE_SGL 0x1\n+#define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0\n+#define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1\n+\n+#define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \\\n+\t((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \\\n+\t | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))\n+\n+#define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)\n+\n+#define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \\\n+\t\t\tQAT_COMN_CD_FLD_TYPE_MASK)\n+\n+#define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \\\n+\t\t\tQAT_COMN_PTR_TYPE_MASK)\n+\n+#define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \\\n+\t\t\tQAT_COMN_CD_FLD_TYPE_MASK)\n+\n+#define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4\n+#define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0\n+#define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0\n+#define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F\n+\n+#define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \\\n+\t>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))\n+\n+#define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \\\n+\t{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \\\n+\t& ICP_QAT_FW_COMN_CURR_ID_MASK) | \\\n+\t((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \\\n+\t & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }\n+\n+#define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \\\n+\t(((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)\n+\n+#define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \\\n+\t{ ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \\\n+\t& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \\\n+\t((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }\n+\n+#define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7\n+#define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1\n+#define QAT_COMN_RESP_CMP_STATUS_BITPOS 5\n+#define QAT_COMN_RESP_CMP_STATUS_MASK 0x1\n+#define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4\n+#define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1\n+#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3\n+#define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1\n+\n+#define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \\\n+\t((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \\\n+\tQAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \\\n+\t(((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \\\n+\tQAT_COMN_RESP_CMP_STATUS_BITPOS) | \\\n+\t(((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \\\n+\tQAT_COMN_RESP_XLAT_STATUS_BITPOS) | \\\n+\t(((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \\\n+\tQAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))\n+\n+#define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \\\n+\tQAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \\\n+\tQAT_COMN_RESP_CRYPTO_STATUS_MASK)\n+\n+#define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \\\n+\tQAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \\\n+\tQAT_COMN_RESP_CMP_STATUS_MASK)\n+\n+#define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \\\n+\tQAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \\\n+\tQAT_COMN_RESP_XLAT_STATUS_MASK)\n+\n+#define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \\\n+\tQAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \\\n+\tQAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)\n+\n+#define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0\n+#define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1\n+#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0\n+#define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1\n+#define ERR_CODE_NO_ERROR 0\n+#define ERR_CODE_INVALID_BLOCK_TYPE -1\n+#define ERR_CODE_NO_MATCH_ONES_COMP -2\n+#define ERR_CODE_TOO_MANY_LEN_OR_DIS -3\n+#define ERR_CODE_INCOMPLETE_LEN -4\n+#define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5\n+#define ERR_CODE_RPT_GT_SPEC_LEN -6\n+#define ERR_CODE_INV_LIT_LEN_CODE_LEN -7\n+#define ERR_CODE_INV_DIS_CODE_LEN -8\n+#define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9\n+#define ERR_CODE_DIS_TOO_FAR_BACK -10\n+#define ERR_CODE_OVERFLOW_ERROR -11\n+#define ERR_CODE_SOFT_ERROR -12\n+#define ERR_CODE_FATAL_ERROR -13\n+#define ERR_CODE_SSM_ERROR -14\n+#define ERR_CODE_ENDPOINT_ERROR -15\n+\n+enum icp_qat_fw_slice {\n+\tICP_QAT_FW_SLICE_NULL = 0,\n+\tICP_QAT_FW_SLICE_CIPHER = 1,\n+\tICP_QAT_FW_SLICE_AUTH = 2,\n+\tICP_QAT_FW_SLICE_DRAM_RD = 3,\n+\tICP_QAT_FW_SLICE_DRAM_WR = 4,\n+\tICP_QAT_FW_SLICE_COMP = 5,\n+\tICP_QAT_FW_SLICE_XLAT = 6,\n+\tICP_QAT_FW_SLICE_DELIMITER\n+};\n+#endif\ndiff --git a/drivers/crypto/qat/qat_adf/icp_qat_fw_la.h b/drivers/crypto/qat/qat_adf/icp_qat_fw_la.h\nnew file mode 100644\nindex 0000000..7671465\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/icp_qat_fw_la.h\n@@ -0,0 +1,404 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Intel Corporation nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+#ifndef _ICP_QAT_FW_LA_H_\n+#define _ICP_QAT_FW_LA_H_\n+#include \"icp_qat_fw.h\"\n+\n+enum icp_qat_fw_la_cmd_id {\n+\tICP_QAT_FW_LA_CMD_CIPHER = 0,\n+\tICP_QAT_FW_LA_CMD_AUTH = 1,\n+\tICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,\n+\tICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,\n+\tICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,\n+\tICP_QAT_FW_LA_CMD_TRNG_TEST = 5,\n+\tICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,\n+\tICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,\n+\tICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,\n+\tICP_QAT_FW_LA_CMD_MGF1 = 9,\n+\tICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,\n+\tICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,\n+\tICP_QAT_FW_LA_CMD_DELIMITER = 12\n+};\n+\n+#define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK\n+#define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR\n+#define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK\n+#define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR\n+\n+struct icp_qat_fw_la_bulk_req {\n+\tstruct icp_qat_fw_comn_req_hdr comn_hdr;\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;\n+\tstruct icp_qat_fw_comn_req_mid comn_mid;\n+\tstruct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;\n+\tstruct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;\n+};\n+\n+#define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1\n+#define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0\n+#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12\n+#define ICP_QAT_FW_LA_ZUC_3G_PROTO 1\n+#define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1\n+#define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11\n+#define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1\n+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1\n+#define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0\n+#define QAT_LA_DIGEST_IN_BUFFER_BITPOS\t10\n+#define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1\n+#define ICP_QAT_FW_LA_SNOW_3G_PROTO 4\n+#define ICP_QAT_FW_LA_GCM_PROTO\t2\n+#define ICP_QAT_FW_LA_CCM_PROTO\t1\n+#define ICP_QAT_FW_LA_NO_PROTO 0\n+#define QAT_LA_PROTO_BITPOS 7\n+#define QAT_LA_PROTO_MASK 0x7\n+#define ICP_QAT_FW_LA_CMP_AUTH_RES 1\n+#define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0\n+#define QAT_LA_CMP_AUTH_RES_BITPOS 6\n+#define QAT_LA_CMP_AUTH_RES_MASK 0x1\n+#define ICP_QAT_FW_LA_RET_AUTH_RES 1\n+#define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0\n+#define QAT_LA_RET_AUTH_RES_BITPOS 5\n+#define QAT_LA_RET_AUTH_RES_MASK 0x1\n+#define ICP_QAT_FW_LA_UPDATE_STATE 1\n+#define ICP_QAT_FW_LA_NO_UPDATE_STATE 0\n+#define QAT_LA_UPDATE_STATE_BITPOS 4\n+#define QAT_LA_UPDATE_STATE_MASK 0x1\n+#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0\n+#define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1\n+#define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3\n+#define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1\n+#define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0\n+#define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1\n+#define QAT_LA_CIPH_IV_FLD_BITPOS 2\n+#define QAT_LA_CIPH_IV_FLD_MASK 0x1\n+#define ICP_QAT_FW_LA_PARTIAL_NONE 0\n+#define ICP_QAT_FW_LA_PARTIAL_START 1\n+#define ICP_QAT_FW_LA_PARTIAL_MID 3\n+#define ICP_QAT_FW_LA_PARTIAL_END 2\n+#define QAT_LA_PARTIAL_BITPOS 0\n+#define QAT_LA_PARTIAL_MASK 0x3\n+#define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \\\n+\tcmp_auth, ret_auth, update_state, \\\n+\tciph_iv, ciphcfg, partial) \\\n+\t(((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \\\n+\tQAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \\\n+\t((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \\\n+\tQAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \\\n+\t((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \\\n+\tQAT_LA_DIGEST_IN_BUFFER_BITPOS) | \\\n+\t((proto & QAT_LA_PROTO_MASK) << \\\n+\tQAT_LA_PROTO_BITPOS)\t| \\\n+\t((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \\\n+\tQAT_LA_CMP_AUTH_RES_BITPOS) | \\\n+\t((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \\\n+\tQAT_LA_RET_AUTH_RES_BITPOS) | \\\n+\t((update_state & QAT_LA_UPDATE_STATE_MASK) << \\\n+\tQAT_LA_UPDATE_STATE_BITPOS) | \\\n+\t((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \\\n+\tQAT_LA_CIPH_IV_FLD_BITPOS) | \\\n+\t((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \\\n+\tQAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \\\n+\t((partial & QAT_LA_PARTIAL_MASK) << \\\n+\tQAT_LA_PARTIAL_BITPOS))\n+\n+#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \\\n+\tQAT_LA_CIPH_IV_FLD_MASK)\n+\n+#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \\\n+\tQAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)\n+\n+#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \\\n+\tQAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)\n+\n+#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \\\n+\tQAT_LA_GCM_IV_LEN_FLAG_MASK)\n+\n+#define ICP_QAT_FW_LA_PROTO_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)\n+\n+#define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \\\n+\tQAT_LA_CMP_AUTH_RES_MASK)\n+\n+#define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \\\n+\tQAT_LA_RET_AUTH_RES_MASK)\n+\n+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \\\n+\tQAT_LA_DIGEST_IN_BUFFER_MASK)\n+\n+#define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \\\n+\tQAT_LA_UPDATE_STATE_MASK)\n+\n+#define ICP_QAT_FW_LA_PARTIAL_GET(flags) \\\n+\tQAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \\\n+\tQAT_LA_PARTIAL_MASK)\n+\n+#define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \\\n+\tQAT_LA_CIPH_IV_FLD_MASK)\n+\n+#define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \\\n+\tQAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)\n+\n+#define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \\\n+\tQAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)\n+\n+#define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \\\n+\tQAT_LA_GCM_IV_LEN_FLAG_MASK)\n+\n+#define ICP_QAT_FW_LA_PROTO_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \\\n+\tQAT_LA_PROTO_MASK)\n+\n+#define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \\\n+\tQAT_LA_CMP_AUTH_RES_MASK)\n+\n+#define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \\\n+\tQAT_LA_RET_AUTH_RES_MASK)\n+\n+#define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \\\n+\tQAT_LA_DIGEST_IN_BUFFER_MASK)\n+\n+#define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \\\n+\tQAT_LA_UPDATE_STATE_MASK)\n+\n+#define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \\\n+\tQAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \\\n+\tQAT_LA_PARTIAL_MASK)\n+\n+struct icp_qat_fw_cipher_req_hdr_cd_pars {\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t content_desc_addr;\n+\t\t\tuint16_t content_desc_resrvd1;\n+\t\t\tuint8_t content_desc_params_sz;\n+\t\t\tuint8_t content_desc_hdr_resrvd2;\n+\t\t\tuint32_t content_desc_resrvd3;\n+\t\t} s;\n+\t\tstruct {\n+\t\t\tuint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\t\t} s1;\n+\t} u;\n+};\n+\n+struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint64_t content_desc_addr;\n+\t\t\tuint16_t content_desc_resrvd1;\n+\t\t\tuint8_t content_desc_params_sz;\n+\t\t\tuint8_t content_desc_hdr_resrvd2;\n+\t\t\tuint32_t content_desc_resrvd3;\n+\t\t} s;\n+\t\tstruct {\n+\t\t\tuint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\t\t} sl;\n+\t} u;\n+};\n+\n+struct icp_qat_fw_cipher_cd_ctrl_hdr {\n+\tuint8_t cipher_state_sz;\n+\tuint8_t cipher_key_sz;\n+\tuint8_t cipher_cfg_offset;\n+\tuint8_t next_curr_id;\n+\tuint8_t cipher_padding_sz;\n+\tuint8_t resrvd1;\n+\tuint16_t resrvd2;\n+\tuint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];\n+};\n+\n+struct icp_qat_fw_auth_cd_ctrl_hdr {\n+\tuint32_t resrvd1;\n+\tuint8_t resrvd2;\n+\tuint8_t hash_flags;\n+\tuint8_t hash_cfg_offset;\n+\tuint8_t next_curr_id;\n+\tuint8_t resrvd3;\n+\tuint8_t outer_prefix_sz;\n+\tuint8_t final_sz;\n+\tuint8_t inner_res_sz;\n+\tuint8_t resrvd4;\n+\tuint8_t inner_state1_sz;\n+\tuint8_t inner_state2_offset;\n+\tuint8_t inner_state2_sz;\n+\tuint8_t outer_config_offset;\n+\tuint8_t outer_state1_sz;\n+\tuint8_t outer_res_sz;\n+\tuint8_t outer_prefix_offset;\n+};\n+\n+struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {\n+\tuint8_t cipher_state_sz;\n+\tuint8_t cipher_key_sz;\n+\tuint8_t cipher_cfg_offset;\n+\tuint8_t next_curr_id_cipher;\n+\tuint8_t cipher_padding_sz;\n+\tuint8_t hash_flags;\n+\tuint8_t hash_cfg_offset;\n+\tuint8_t next_curr_id_auth;\n+\tuint8_t resrvd1;\n+\tuint8_t outer_prefix_sz;\n+\tuint8_t final_sz;\n+\tuint8_t inner_res_sz;\n+\tuint8_t resrvd2;\n+\tuint8_t inner_state1_sz;\n+\tuint8_t inner_state2_offset;\n+\tuint8_t inner_state2_sz;\n+\tuint8_t outer_config_offset;\n+\tuint8_t outer_state1_sz;\n+\tuint8_t outer_res_sz;\n+\tuint8_t outer_prefix_offset;\n+};\n+\n+#define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1\n+#define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0\n+#define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX\t240\n+#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \\\n+\t(sizeof(struct icp_qat_fw_la_cipher_req_params_t))\n+#define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)\n+\n+struct icp_qat_fw_la_cipher_req_params {\n+\tuint32_t cipher_offset;\n+\tuint32_t cipher_length;\n+\tunion {\n+\t\tuint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\t\tstruct {\n+\t\t\tuint64_t cipher_IV_ptr;\n+\t\t\tuint64_t resrvd1;\n+\t\t} s;\n+\t} u;\n+};\n+\n+struct icp_qat_fw_la_auth_req_params {\n+\tuint32_t auth_off;\n+\tuint32_t auth_len;\n+\tunion {\n+\t\tuint64_t auth_partial_st_prefix;\n+\t\tuint64_t aad_adr;\n+\t} u1;\n+\tuint64_t auth_res_addr;\n+\tunion {\n+\t\tuint8_t inner_prefix_sz;\n+\t\tuint8_t aad_sz;\n+\t} u2;\n+\tuint8_t resrvd1;\n+\tuint8_t hash_state_sz;\n+\tuint8_t auth_res_sz;\n+} __rte_packed;\n+\n+struct icp_qat_fw_la_auth_req_params_resrvd_flds {\n+\tuint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];\n+\tunion {\n+\t\tuint8_t inner_prefix_sz;\n+\t\tuint8_t aad_sz;\n+\t} u2;\n+\tuint8_t resrvd1;\n+\tuint16_t resrvd2;\n+};\n+\n+struct icp_qat_fw_la_resp {\n+\tstruct icp_qat_fw_comn_resp_hdr comn_resp;\n+\tuint64_t opaque_data;\n+\tuint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];\n+};\n+\n+#define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \\\n+\t ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))\n+\n+#define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \\\n+{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_cipher) \\\n+\t& ICP_QAT_FW_COMN_CURR_ID_MASK) | \\\n+\t((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \\\n+\t& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }\n+\n+#define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \\\n+\t(((cd_ctrl_hdr_t)->next_curr_id_cipher) \\\n+\t& ICP_QAT_FW_COMN_CURR_ID_MASK)\n+\n+#define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \\\n+{ (cd_ctrl_hdr_t)->next_curr_id_cipher = \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_cipher) \\\n+\t& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \\\n+\t((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }\n+\n+#define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \\\n+\t>> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))\n+\n+#define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \\\n+{ (cd_ctrl_hdr_t)->next_curr_id_auth = \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_auth) \\\n+\t& ICP_QAT_FW_COMN_CURR_ID_MASK) | \\\n+\t((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \\\n+\t& ICP_QAT_FW_COMN_NEXT_ID_MASK)) }\n+\n+#define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \\\n+\t(((cd_ctrl_hdr_t)->next_curr_id_auth) \\\n+\t& ICP_QAT_FW_COMN_CURR_ID_MASK)\n+\n+#define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \\\n+{ (cd_ctrl_hdr_t)->next_curr_id_auth = \\\n+\t((((cd_ctrl_hdr_t)->next_curr_id_auth) \\\n+\t& ICP_QAT_FW_COMN_NEXT_ID_MASK) | \\\n+\t((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }\n+\n+#endif\ndiff --git a/drivers/crypto/qat/qat_adf/icp_qat_hw.h b/drivers/crypto/qat/qat_adf/icp_qat_hw.h\nnew file mode 100644\nindex 0000000..4d8fe38\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/icp_qat_hw.h\n@@ -0,0 +1,306 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Intel Corporation nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+#ifndef _ICP_QAT_HW_H_\n+#define _ICP_QAT_HW_H_\n+\n+enum icp_qat_hw_ae_id {\n+\tICP_QAT_HW_AE_0 = 0,\n+\tICP_QAT_HW_AE_1 = 1,\n+\tICP_QAT_HW_AE_2 = 2,\n+\tICP_QAT_HW_AE_3 = 3,\n+\tICP_QAT_HW_AE_4 = 4,\n+\tICP_QAT_HW_AE_5 = 5,\n+\tICP_QAT_HW_AE_6 = 6,\n+\tICP_QAT_HW_AE_7 = 7,\n+\tICP_QAT_HW_AE_8 = 8,\n+\tICP_QAT_HW_AE_9 = 9,\n+\tICP_QAT_HW_AE_10 = 10,\n+\tICP_QAT_HW_AE_11 = 11,\n+\tICP_QAT_HW_AE_DELIMITER = 12\n+};\n+\n+enum icp_qat_hw_qat_id {\n+\tICP_QAT_HW_QAT_0 = 0,\n+\tICP_QAT_HW_QAT_1 = 1,\n+\tICP_QAT_HW_QAT_2 = 2,\n+\tICP_QAT_HW_QAT_3 = 3,\n+\tICP_QAT_HW_QAT_4 = 4,\n+\tICP_QAT_HW_QAT_5 = 5,\n+\tICP_QAT_HW_QAT_DELIMITER = 6\n+};\n+\n+enum icp_qat_hw_auth_algo {\n+\tICP_QAT_HW_AUTH_ALGO_NULL = 0,\n+\tICP_QAT_HW_AUTH_ALGO_SHA1 = 1,\n+\tICP_QAT_HW_AUTH_ALGO_MD5 = 2,\n+\tICP_QAT_HW_AUTH_ALGO_SHA224 = 3,\n+\tICP_QAT_HW_AUTH_ALGO_SHA256 = 4,\n+\tICP_QAT_HW_AUTH_ALGO_SHA384 = 5,\n+\tICP_QAT_HW_AUTH_ALGO_SHA512 = 6,\n+\tICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,\n+\tICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,\n+\tICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,\n+\tICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,\n+\tICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,\n+\tICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,\n+\tICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,\n+\tICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,\n+\tICP_QAT_HW_AUTH_RESERVED_1 = 15,\n+\tICP_QAT_HW_AUTH_RESERVED_2 = 16,\n+\tICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,\n+\tICP_QAT_HW_AUTH_RESERVED_3 = 18,\n+\tICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,\n+\tICP_QAT_HW_AUTH_ALGO_DELIMITER = 20\n+};\n+\n+enum icp_qat_hw_auth_mode {\n+\tICP_QAT_HW_AUTH_MODE0 = 0,\n+\tICP_QAT_HW_AUTH_MODE1 = 1,\n+\tICP_QAT_HW_AUTH_MODE2 = 2,\n+\tICP_QAT_HW_AUTH_MODE_DELIMITER = 3\n+};\n+\n+struct icp_qat_hw_auth_config {\n+\tuint32_t config;\n+\tuint32_t reserved;\n+};\n+\n+#define QAT_AUTH_MODE_BITPOS 4\n+#define QAT_AUTH_MODE_MASK 0xF\n+#define QAT_AUTH_ALGO_BITPOS 0\n+#define QAT_AUTH_ALGO_MASK 0xF\n+#define QAT_AUTH_CMP_BITPOS 8\n+#define QAT_AUTH_CMP_MASK 0x7F\n+#define QAT_AUTH_SHA3_PADDING_BITPOS 16\n+#define QAT_AUTH_SHA3_PADDING_MASK 0x1\n+#define QAT_AUTH_ALGO_SHA3_BITPOS 22\n+#define QAT_AUTH_ALGO_SHA3_MASK 0x3\n+#define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \\\n+\t(((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \\\n+\t((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \\\n+\t(((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \\\n+\t QAT_AUTH_ALGO_SHA3_BITPOS) | \\\n+\t (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \\\n+\t(algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \\\n+\t& QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \\\n+\t((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))\n+\n+struct icp_qat_hw_auth_counter {\n+\tuint32_t counter;\n+\tuint32_t reserved;\n+};\n+\n+#define QAT_AUTH_COUNT_MASK 0xFFFFFFFF\n+#define QAT_AUTH_COUNT_BITPOS 0\n+#define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \\\n+\t(((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)\n+\n+struct icp_qat_hw_auth_setup {\n+\tstruct icp_qat_hw_auth_config auth_config;\n+\tstruct icp_qat_hw_auth_counter auth_counter;\n+};\n+\n+#define QAT_HW_DEFAULT_ALIGNMENT 8\n+#define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))\n+#define ICP_QAT_HW_NULL_STATE1_SZ 32\n+#define ICP_QAT_HW_MD5_STATE1_SZ 16\n+#define ICP_QAT_HW_SHA1_STATE1_SZ 20\n+#define ICP_QAT_HW_SHA224_STATE1_SZ 32\n+#define ICP_QAT_HW_SHA256_STATE1_SZ 32\n+#define ICP_QAT_HW_SHA3_256_STATE1_SZ 32\n+#define ICP_QAT_HW_SHA384_STATE1_SZ 64\n+#define ICP_QAT_HW_SHA512_STATE1_SZ 64\n+#define ICP_QAT_HW_SHA3_512_STATE1_SZ 64\n+#define ICP_QAT_HW_SHA3_224_STATE1_SZ 28\n+#define ICP_QAT_HW_SHA3_384_STATE1_SZ 48\n+#define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16\n+#define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16\n+#define ICP_QAT_HW_AES_F9_STATE1_SZ 32\n+#define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16\n+#define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16\n+#define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8\n+#define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8\n+#define ICP_QAT_HW_NULL_STATE2_SZ 32\n+#define ICP_QAT_HW_MD5_STATE2_SZ 16\n+#define ICP_QAT_HW_SHA1_STATE2_SZ 20\n+#define ICP_QAT_HW_SHA224_STATE2_SZ 32\n+#define ICP_QAT_HW_SHA256_STATE2_SZ 32\n+#define ICP_QAT_HW_SHA3_256_STATE2_SZ 0\n+#define ICP_QAT_HW_SHA384_STATE2_SZ 64\n+#define ICP_QAT_HW_SHA512_STATE2_SZ 64\n+#define ICP_QAT_HW_SHA3_512_STATE2_SZ 0\n+#define ICP_QAT_HW_SHA3_224_STATE2_SZ 0\n+#define ICP_QAT_HW_SHA3_384_STATE2_SZ 0\n+#define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48\n+#define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16\n+#define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16\n+#define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16\n+#define ICP_QAT_HW_F9_IK_SZ 16\n+#define ICP_QAT_HW_F9_FK_SZ 16\n+#define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \\\n+\tICP_QAT_HW_F9_FK_SZ)\n+#define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ\n+#define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24\n+#define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32\n+#define ICP_QAT_HW_GALOIS_H_SZ 16\n+#define ICP_QAT_HW_GALOIS_LEN_A_SZ 8\n+#define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16\n+\n+struct icp_qat_hw_auth_sha512 {\n+\tstruct icp_qat_hw_auth_setup inner_setup;\n+\tuint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];\n+\tstruct icp_qat_hw_auth_setup outer_setup;\n+\tuint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];\n+};\n+\n+struct icp_qat_hw_auth_algo_blk {\n+\tstruct icp_qat_hw_auth_sha512 sha;\n+};\n+\n+#define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0\n+#define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF\n+\n+enum icp_qat_hw_cipher_algo {\n+\tICP_QAT_HW_CIPHER_ALGO_NULL = 0,\n+\tICP_QAT_HW_CIPHER_ALGO_DES = 1,\n+\tICP_QAT_HW_CIPHER_ALGO_3DES = 2,\n+\tICP_QAT_HW_CIPHER_ALGO_AES128 = 3,\n+\tICP_QAT_HW_CIPHER_ALGO_AES192 = 4,\n+\tICP_QAT_HW_CIPHER_ALGO_AES256 = 5,\n+\tICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,\n+\tICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,\n+\tICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,\n+\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,\n+\tICP_QAT_HW_CIPHER_DELIMITER = 10\n+};\n+\n+enum icp_qat_hw_cipher_mode {\n+\tICP_QAT_HW_CIPHER_ECB_MODE = 0,\n+\tICP_QAT_HW_CIPHER_CBC_MODE = 1,\n+\tICP_QAT_HW_CIPHER_CTR_MODE = 2,\n+\tICP_QAT_HW_CIPHER_F8_MODE = 3,\n+\tICP_QAT_HW_CIPHER_XTS_MODE = 6,\n+\tICP_QAT_HW_CIPHER_MODE_DELIMITER = 7\n+};\n+\n+struct icp_qat_hw_cipher_config {\n+\tuint32_t val;\n+\tuint32_t reserved;\n+};\n+\n+enum icp_qat_hw_cipher_dir {\n+\tICP_QAT_HW_CIPHER_ENCRYPT = 0,\n+\tICP_QAT_HW_CIPHER_DECRYPT = 1,\n+};\n+\n+enum icp_qat_hw_cipher_convert {\n+\tICP_QAT_HW_CIPHER_NO_CONVERT = 0,\n+\tICP_QAT_HW_CIPHER_KEY_CONVERT = 1,\n+};\n+\n+#define QAT_CIPHER_MODE_BITPOS 4\n+#define QAT_CIPHER_MODE_MASK 0xF\n+#define QAT_CIPHER_ALGO_BITPOS 0\n+#define QAT_CIPHER_ALGO_MASK 0xF\n+#define QAT_CIPHER_CONVERT_BITPOS 9\n+#define QAT_CIPHER_CONVERT_MASK 0x1\n+#define QAT_CIPHER_DIR_BITPOS 8\n+#define QAT_CIPHER_DIR_MASK 0x1\n+#define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2\n+#define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2\n+#define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \\\n+\t(((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \\\n+\t((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \\\n+\t((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \\\n+\t((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))\n+#define ICP_QAT_HW_DES_BLK_SZ 8\n+#define ICP_QAT_HW_3DES_BLK_SZ 8\n+#define ICP_QAT_HW_NULL_BLK_SZ 8\n+#define ICP_QAT_HW_AES_BLK_SZ 16\n+#define ICP_QAT_HW_KASUMI_BLK_SZ 8\n+#define ICP_QAT_HW_SNOW_3G_BLK_SZ 8\n+#define ICP_QAT_HW_ZUC_3G_BLK_SZ 8\n+#define ICP_QAT_HW_NULL_KEY_SZ 256\n+#define ICP_QAT_HW_DES_KEY_SZ 8\n+#define ICP_QAT_HW_3DES_KEY_SZ 24\n+#define ICP_QAT_HW_AES_128_KEY_SZ 16\n+#define ICP_QAT_HW_AES_192_KEY_SZ 24\n+#define ICP_QAT_HW_AES_256_KEY_SZ 32\n+#define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_F8_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_F8_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_F8_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_XTS_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_XTS_KEY_SZ_MULT)\n+#define ICP_QAT_HW_KASUMI_KEY_SZ 16\n+#define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_F8_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_XTS_KEY_SZ_MULT)\n+#define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \\\n+\tQAT_CIPHER_MODE_XTS_KEY_SZ_MULT)\n+#define ICP_QAT_HW_ARC4_KEY_SZ 256\n+#define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16\n+#define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16\n+#define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16\n+#define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16\n+#define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2\n+#define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024\n+\n+struct icp_qat_hw_cipher_aes256_f8 {\n+\tstruct icp_qat_hw_cipher_config cipher_config;\n+\tuint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ];\n+};\n+\n+struct icp_qat_hw_cipher_algo_blk {\n+\tstruct icp_qat_hw_cipher_aes256_f8 aes;\n+} __rte_cache_aligned;\n+#endif\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h\nnew file mode 100644\nindex 0000000..fb3a685\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/qat_algs.h\n@@ -0,0 +1,125 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+ * Redistributions of source code must retain the above copyright\n+ notice, this list of conditions and the following disclaimer.\n+ * Redistributions in binary form must reproduce the above copyright\n+ notice, this list of conditions and the following disclaimer in\n+ the documentation and/or other materials provided with the\n+ distribution.\n+ * Neither the name of Intel Corporation nor the names of its\n+ contributors may be used to endorse or promote products derived\n+ from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+#ifndef _ICP_QAT_ALGS_H_\n+#define _ICP_QAT_ALGS_H_\n+#include <rte_memory.h>\n+#include \"icp_qat_hw.h\"\n+#include \"icp_qat_fw.h\"\n+#include \"icp_qat_fw_la.h\"\n+\n+#define QAT_AES_HW_CONFIG_CBC_ENC(alg) \\\n+\tICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \\\n+\t\t\t\t\tICP_QAT_HW_CIPHER_NO_CONVERT, \\\n+\t\t\t\t\tICP_QAT_HW_CIPHER_ENCRYPT)\n+\n+#define QAT_AES_HW_CONFIG_CBC_DEC(alg) \\\n+\tICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \\\n+\t\t\t\t\tICP_QAT_HW_CIPHER_KEY_CONVERT, \\\n+\t\t\t\t\tICP_QAT_HW_CIPHER_DECRYPT)\n+\n+struct qat_alg_buf {\n+\tuint32_t len;\n+\tuint32_t resrvd;\n+\tuint64_t addr;\n+} __rte_packed;\n+\n+struct qat_alg_buf_list {\n+\tuint64_t resrvd;\n+\tuint32_t num_bufs;\n+\tuint32_t num_mapped_bufs;\n+\tstruct qat_alg_buf bufers[];\n+} __rte_packed __rte_cache_aligned;\n+\n+/* Common content descriptor */\n+struct qat_alg_cd {\n+\tstruct icp_qat_hw_cipher_algo_blk cipher;\n+\tstruct icp_qat_hw_auth_algo_blk hash;\n+} __rte_packed __rte_cache_aligned;\n+\n+struct qat_session {\n+\tenum icp_qat_fw_la_cmd_id qat_cmd;\n+\tenum icp_qat_hw_cipher_algo qat_cipher_alg;\n+\tenum icp_qat_hw_cipher_dir qat_dir;\n+\tenum icp_qat_hw_cipher_mode qat_mode;\n+\tenum icp_qat_hw_auth_algo qat_hash_alg;\n+\tstruct qat_alg_cd cd;\n+\tphys_addr_t cd_paddr;\n+\tstruct icp_qat_fw_la_bulk_req fw_req;\n+\tstruct qat_crypto_instance *inst;\n+\tuint8_t salt[ICP_QAT_HW_AES_BLK_SZ];\n+\trte_spinlock_t lock;\t/* protects this struct */\n+};\n+\n+struct qat_alg_ablkcipher_cd {\n+\tstruct icp_qat_hw_cipher_algo_blk *cd;\n+\tphys_addr_t cd_paddr;\n+\tstruct icp_qat_fw_la_bulk_req fw_req;\n+\tstruct qat_crypto_instance *inst;\n+\trte_spinlock_t lock;\t/* protects this struct */\n+};\n+\n+int qat_get_inter_state_size(enum icp_qat_hw_auth_algo qat_hash_alg);\n+\n+int qat_alg_aead_session_create_content_desc(struct qat_session *cd,\n+\t\t\t\t\tuint8_t *enckey, uint32_t enckeylen,\n+\t\t\t\t\tuint8_t *authkey, uint32_t authkeylen,\n+\t\t\t\t\tuint32_t add_auth_data_length,\n+\t\t\t\t\tuint32_t digestsize);\n+\n+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header);\n+\n+void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cd,\n+\t\t\t\t\tint alg, const uint8_t *key,\n+\t\t\t\t\tunsigned int keylen);\n+\n+void qat_alg_ablkcipher_init_dec(struct qat_alg_ablkcipher_cd *cd,\n+\t\t\t\t\tint alg, const uint8_t *key,\n+\t\t\t\t\tunsigned int keylen);\n+\n+int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);\n+\n+#endif\ndiff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\nnew file mode 100644\nindex 0000000..da6ddcd\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c\n@@ -0,0 +1,576 @@\n+/*\n+ This file is provided under a dual BSD/GPLv2 license. When using or\n+ redistributing this file, you may do so under either license.\n+\n+ GPL LICENSE SUMMARY\n+ Copyright(c) 2015 Intel Corporation.\n+ This program is free software; you can redistribute it and/or modify\n+ it under the terms of version 2 of the GNU General Public License as\n+ published by the Free Software Foundation.\n+\n+ This program is distributed in the hope that it will be useful, but\n+ WITHOUT ANY WARRANTY; without even the implied warranty of\n+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n+ General Public License for more details.\n+\n+ Contact Information:\n+ qat-linux@intel.com\n+\n+ BSD LICENSE\n+ Copyright(c) 2015 Intel Corporation.\n+ Redistribution and use in source and binary forms, with or without\n+ modification, are permitted provided that the following conditions\n+ are met:\n+\n+\t* Redistributions of source code must retain the above copyright\n+\t notice, this list of conditions and the following disclaimer.\n+\t* Redistributions in binary form must reproduce the above copyright\n+\t notice, this list of conditions and the following disclaimer in\n+\t the documentation and/or other materials provided with the\n+\t distribution.\n+\t* Neither the name of Intel Corporation nor the names of its\n+\t contributors may be used to endorse or promote products derived\n+\t from this software without specific prior written permission.\n+\n+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#include <rte_memcpy.h>\n+#include <rte_common.h>\n+#include <rte_spinlock.h>\n+#include <rte_byteorder.h>\n+#include <rte_log.h>\n+#include <rte_malloc.h>\n+\n+#include \"../qat_logs.h\"\n+#include \"qat_algs.h\"\n+\n+#include <openssl/sha.h>\t/* Needed to calculate pre-compute values */\n+#include <openssl/aes.h>\t/* Needed to calculate pre-compute values */\n+\n+\n+/* returns size in bytes per hash algo for state1 size field in cd_ctrl\n+ * This is digest size rounded up to nearest quadword */\n+static int qat_hash_get_state1_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n+{\n+\tswitch (qat_hash_alg) {\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA1_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA256_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n+\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_GALOIS_128_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n+\t\t/* return maximum state1 size in this case */\n+\t\treturn QAT_HW_ROUND_UP(ICP_QAT_HW_SHA512_STATE1_SZ,\n+\t\t\t\t\t\tQAT_HW_DEFAULT_ALIGNMENT);\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"invalid hash alg %u\", qat_hash_alg);\n+\t\treturn -EFAULT;\n+\t};\n+\treturn -EFAULT;\n+}\n+\n+/* returns digest size in bytes per hash algo */\n+static int qat_hash_get_digest_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n+{\n+\tswitch (qat_hash_alg) {\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\treturn ICP_QAT_HW_SHA1_STATE1_SZ;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\treturn ICP_QAT_HW_SHA256_STATE1_SZ;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\treturn ICP_QAT_HW_SHA512_STATE1_SZ;\n+\tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n+\t\t/* return maximum digest size in this case */\n+\t\treturn ICP_QAT_HW_SHA512_STATE1_SZ;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"invalid hash alg %u\", qat_hash_alg);\n+\t\treturn -EFAULT;\n+\t};\n+\treturn -EFAULT;\n+}\n+\n+/* returns block size in byes per hash algo */\n+static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg)\n+{\n+\tswitch (qat_hash_alg) {\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\treturn SHA_CBLOCK;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\treturn SHA256_CBLOCK;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\treturn SHA512_CBLOCK;\n+\tcase ICP_QAT_HW_AUTH_ALGO_DELIMITER:\n+\t\t/* return maximum block size in this case */\n+\t\treturn SHA512_CBLOCK;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"invalid hash alg %u\", qat_hash_alg);\n+\t\treturn -EFAULT;\n+\t};\n+\treturn -EFAULT;\n+}\n+\n+static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA_CTX ctx;\n+\n+\tif (!SHA1_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA1_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx, SHA_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha256(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA256_CTX ctx;\n+\n+\tif (!SHA256_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA256_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx, SHA256_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)\n+{\n+\tSHA512_CTX ctx;\n+\n+\tif (!SHA512_Init(&ctx))\n+\t\treturn -EFAULT;\n+\tSHA512_Transform(&ctx, data_in);\n+\trte_memcpy(data_out, &ctx, SHA512_DIGEST_LENGTH);\n+\treturn 0;\n+}\n+\n+static int partial_hash_compute(enum icp_qat_hw_auth_algo hash_alg,\n+\t\t\tuint8_t *data_in,\n+\t\t\tuint8_t *data_out)\n+{\n+\tint digest_size;\n+\tuint8_t digest[qat_hash_get_digest_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];\n+\tuint32_t *hash_state_out_be32;\n+\tuint64_t *hash_state_out_be64;\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tdigest_size = qat_hash_get_digest_size(hash_alg);\n+\tif (digest_size <= 0)\n+\t\treturn -EFAULT;\n+\n+\thash_state_out_be32 = (uint32_t *)data_out;\n+\thash_state_out_be64 = (uint64_t *)data_out;\n+\n+\tswitch (hash_alg) {\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\tif (partial_hash_sha1(data_in, digest))\n+\t\t\treturn -EFAULT;\n+\t\tfor (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)\n+\t\t\t*hash_state_out_be32 =\n+\t\t\t\trte_bswap32(*(((uint32_t *)digest)+i));\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\tif (partial_hash_sha256(data_in, digest))\n+\t\t\treturn -EFAULT;\n+\t\tfor (i = 0; i < digest_size >> 2; i++, hash_state_out_be32++)\n+\t\t\t*hash_state_out_be32 =\n+\t\t\t\trte_bswap32(*(((uint32_t *)digest)+i));\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\tif (partial_hash_sha512(data_in, digest))\n+\t\t\treturn -EFAULT;\n+\t\tfor (i = 0; i < digest_size >> 3; i++, hash_state_out_be64++)\n+\t\t\t*hash_state_out_be64 =\n+\t\t\t\trte_bswap64(*(((uint64_t *)digest)+i));\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"invalid hash alg %u\", hash_alg);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\treturn 0;\n+}\n+#define HMAC_IPAD_VALUE\t0x36\n+#define HMAC_OPAD_VALUE\t0x5c\n+#define HASH_XCBC_PRECOMP_KEY_NUM 3\n+\n+static int qat_alg_do_precomputes(enum icp_qat_hw_auth_algo hash_alg,\n+\t\t\t\tconst uint8_t *auth_key,\n+\t\t\t\tuint16_t auth_keylen,\n+\t\t\t\tuint8_t *p_state_buf,\n+\t\t\t\tuint16_t *p_state_len)\n+{\n+\tint block_size;\n+\tuint8_t ipad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];\n+\tuint8_t opad[qat_hash_get_block_size(ICP_QAT_HW_AUTH_ALGO_DELIMITER)];\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {\n+\t\tstatic uint8_t qat_aes_xcbc_key_seed[ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ] = {\n+\t\t\t0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,\n+\t\t\t0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,\n+\t\t\t0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n+\t\t\t0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,\n+\t\t\t0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,\n+\t\t\t0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,\n+\t\t};\n+\n+\t\tuint8_t *in = NULL;\n+\t\tuint8_t *out = p_state_buf;\n+\t\tint x;\n+\t\tAES_KEY enc_key;\n+\n+\t\tin = rte_zmalloc(\"working mem for key\",\n+\t\t\t\tICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ, 16);\n+\t\trte_memcpy(in, qat_aes_xcbc_key_seed,\n+\t\t\t\tICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);\n+\t\tfor (x = 0; x < HASH_XCBC_PRECOMP_KEY_NUM; x++) {\n+\t\t\tif (AES_set_encrypt_key(auth_key, auth_keylen << 3,\n+\t\t\t\t&enc_key) != 0) {\n+\t\t\t\trte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);\n+\t\t\t\tmemset(out - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ, 0,\n+\t\t\t\t\tICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ);\n+\t\t\t\treturn -EFAULT;\n+\t\t\t}\n+\t\t\tAES_encrypt(in, out, &enc_key);\n+\t\t\tin += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;\n+\t\t\tout += ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ;\n+\t\t}\n+\t\t*p_state_len = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;\n+\t\trte_free(in - x*ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ);\n+\t\treturn 0;\n+\t} else if ((hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||\n+\t\t(hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {\n+\t\tuint8_t *in = NULL;\n+\t\tuint8_t *out = p_state_buf;\n+\t\tAES_KEY enc_key;\n+\n+\t\tmemset(p_state_buf, 0, ICP_QAT_HW_GALOIS_H_SZ +\n+\t\t\t\tICP_QAT_HW_GALOIS_LEN_A_SZ +\n+\t\t\t\tICP_QAT_HW_GALOIS_E_CTR0_SZ);\n+\t\tin = rte_zmalloc(\"working mem for key\",\n+\t\t\t\tICP_QAT_HW_GALOIS_H_SZ, 16);\n+\t\tmemset(in, 0, ICP_QAT_HW_GALOIS_H_SZ);\n+\t\tif (AES_set_encrypt_key(auth_key, auth_keylen << 3,\n+\t\t\t&enc_key) != 0) {\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t\tAES_encrypt(in, out, &enc_key);\n+\t\t*p_state_len = ICP_QAT_HW_GALOIS_H_SZ +\n+\t\t\t\tICP_QAT_HW_GALOIS_LEN_A_SZ +\n+\t\t\t\tICP_QAT_HW_GALOIS_E_CTR0_SZ;\n+\t\trte_free(in);\n+\t\treturn 0;\n+\t}\n+\n+\tblock_size = qat_hash_get_block_size(hash_alg);\n+\tif (block_size <= 0)\n+\t\treturn -EFAULT;\n+\t/* init ipad and opad from key and xor with fixed values */\n+\tmemset(ipad, 0, block_size);\n+\tmemset(opad, 0, block_size);\n+\n+\tif (auth_keylen > (unsigned int)block_size) {\n+\t\tPMD_DRV_LOG(ERR, \"invalid keylen %u\", auth_keylen);\n+\t\treturn -EFAULT;\n+\t} else {\n+\t\trte_memcpy(ipad, auth_key, auth_keylen);\n+\t\trte_memcpy(opad, auth_key, auth_keylen);\n+\t}\n+\n+\tfor (i = 0; i < block_size; i++) {\n+\t\tuint8_t *ipad_ptr = ipad + i;\n+\t\tuint8_t *opad_ptr = opad + i;\n+\t\t*ipad_ptr ^= HMAC_IPAD_VALUE;\n+\t\t*opad_ptr ^= HMAC_OPAD_VALUE;\n+\t}\n+\n+\t/* do partial hash of ipad and copy to state1 */\n+\tif (partial_hash_compute(hash_alg, ipad, p_state_buf)) {\n+\t\tmemset(ipad, 0, block_size);\n+\t\tmemset(opad, 0, block_size);\n+\t\tPMD_DRV_LOG(ERR, \"ipad precompute failed\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* state len is a multiple of 8, so may be larger than the digest.\n+\t Put the partial hash of opad state_len bytes after state1 */\n+\t*p_state_len = qat_hash_get_state1_size(hash_alg);\n+\tif (partial_hash_compute(hash_alg, opad, p_state_buf + *p_state_len)) {\n+\t\tmemset(ipad, 0, block_size);\n+\t\tmemset(opad, 0, block_size);\n+\t\tPMD_DRV_LOG(ERR, \"opad precompute failed\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\t/* don't leave data lying around */\n+\tmemset(ipad, 0, block_size);\n+\tmemset(opad, 0, block_size);\n+\treturn 0;\n+}\n+\n+void qat_alg_init_common_hdr(struct icp_qat_fw_comn_req_hdr *header)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\theader->hdr_flags =\n+\t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n+\theader->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_LA;\n+\theader->comn_req_flags =\n+\t\tICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_64BIT_ADR,\n+\t\t\t\t\tQAT_COMN_PTR_TYPE_FLAT);\n+\tICP_QAT_FW_LA_PARTIAL_SET(header->serv_specif_flags,\n+\t\t\t\t ICP_QAT_FW_LA_PARTIAL_NONE);\n+\tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(header->serv_specif_flags,\n+\t\t\t\t\t ICP_QAT_FW_CIPH_IV_16BYTE_DATA);\n+\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_PROTO);\n+\tICP_QAT_FW_LA_UPDATE_STATE_SET(header->serv_specif_flags,\n+\t\t\t\t\t ICP_QAT_FW_LA_NO_UPDATE_STATE);\n+}\n+\n+int qat_alg_aead_session_create_content_desc(struct qat_session *cdesc,\n+\t\t\tuint8_t *cipherkey, uint32_t cipherkeylen,\n+\t\t\tuint8_t *authkey, uint32_t authkeylen,\n+\t\t\tuint32_t add_auth_data_length,\n+\t\t\tuint32_t digestsize)\n+{\n+\tstruct qat_alg_cd *content_desc = &cdesc->cd;\n+\tstruct icp_qat_hw_cipher_algo_blk *cipher = &content_desc->cipher;\n+\tstruct icp_qat_hw_auth_algo_blk *hash = &content_desc->hash;\n+\tstruct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;\n+\tvoid *ptr = &req_tmpl->cd_ctrl;\n+\tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cipher_cd_ctrl = ptr;\n+\tstruct icp_qat_fw_auth_cd_ctrl_hdr *hash_cd_ctrl = ptr;\n+\tstruct icp_qat_fw_la_auth_req_params *auth_param =\n+\t\t(struct icp_qat_fw_la_auth_req_params *)\n+\t\t((char *)&req_tmpl->serv_specif_rqpars +\n+\t\tsizeof(struct icp_qat_fw_la_cipher_req_params));\n+\tenum icp_qat_hw_cipher_convert key_convert;\n+\tuint16_t proto = ICP_QAT_FW_LA_NO_PROTO; /* no CCM/GCM/Snow3G */\n+\tuint16_t state1_size = 0;\n+\tuint16_t state2_size = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* CD setup */\n+\tif (cdesc->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {\n+\t\tkey_convert = ICP_QAT_HW_CIPHER_NO_CONVERT;\n+\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_RET_AUTH_RES);\n+\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_CMP_AUTH_RES);\n+\t} else {\n+\t\tkey_convert = ICP_QAT_HW_CIPHER_KEY_CONVERT;\n+\t\tICP_QAT_FW_LA_RET_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_LA_NO_RET_AUTH_RES);\n+\t\tICP_QAT_FW_LA_CMP_AUTH_SET(header->serv_specif_flags,\n+\t\t\t\t ICP_QAT_FW_LA_CMP_AUTH_RES);\n+\t}\n+\n+\tcipher->aes.cipher_config.val = ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode,\n+\t\t\tcdesc->qat_cipher_alg, key_convert, cdesc->qat_dir);\n+\tmemcpy(cipher->aes.key, cipherkey, cipherkeylen);\n+\n+\thash->sha.inner_setup.auth_config.reserved = 0;\n+\thash->sha.inner_setup.auth_config.config =\n+\t\t\tICP_QAT_HW_AUTH_CONFIG_BUILD(ICP_QAT_HW_AUTH_MODE1,\n+\t\t\t\tcdesc->qat_hash_alg, digestsize);\n+\thash->sha.inner_setup.auth_counter.counter =\n+\t\trte_bswap32(qat_hash_get_block_size(cdesc->qat_hash_alg));\n+\n+\t/* Do precomputes */\n+\tif (cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC) {\n+\t\tif (qat_alg_do_precomputes(cdesc->qat_hash_alg,\n+\t\t\tauthkey, authkeylen, (uint8_t *)(hash->sha.state1 +\n+\t\t\tICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ), &state2_size)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"(XCBC)precompute failed\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t} else if ((cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||\n+\t\t(cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {\n+\t\tif (qat_alg_do_precomputes(cdesc->qat_hash_alg,\n+\t\t\tcipherkey, cipherkeylen, (uint8_t *)(hash->sha.state1 +\n+\t\t\tICP_QAT_HW_GALOIS_128_STATE1_SZ), &state2_size)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"(GCM)precompute failed\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t\t/* write (the length of AAD) into bytes 16-19 of state2\n+\t\t* in big-endian format. This field is 8 bytes */\n+\t\t*(uint32_t *)&(hash->sha.state1[ICP_QAT_HW_GALOIS_128_STATE1_SZ +\n+\t\t\t\t\t ICP_QAT_HW_GALOIS_H_SZ]) =\n+\t\t\trte_bswap32(add_auth_data_length);\n+\t\tproto = ICP_QAT_FW_LA_GCM_PROTO;\n+\t} else {\n+\t\tif (qat_alg_do_precomputes(cdesc->qat_hash_alg,\n+\t\t\tauthkey, authkeylen, (uint8_t *)(hash->sha.state1), &state1_size)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"(SHA)precompute failed\");\n+\t\t\treturn -EFAULT;\n+\t\t}\n+\t}\n+\n+\t/* Request template setup */\n+\tqat_alg_init_common_hdr(header);\n+\theader->service_cmd_id = cdesc->qat_cmd;\n+\tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(header->serv_specif_flags,\n+\t\t\t\t\t ICP_QAT_FW_LA_DIGEST_IN_BUFFER);\n+\t/* Configure the common header protocol flags */\n+\tICP_QAT_FW_LA_PROTO_SET(header->serv_specif_flags, proto);\n+\tcd_pars->u.s.content_desc_addr = cdesc->cd_paddr;\n+\tcd_pars->u.s.content_desc_params_sz = sizeof(struct qat_alg_cd) >> 3;\n+\n+\t/* Cipher CD config setup */\n+\tcipher_cd_ctrl->cipher_key_sz = cipherkeylen >> 3;\n+\tcipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n+\tcipher_cd_ctrl->cipher_cfg_offset = 0;\n+\n+\t/* Auth CD config setup */\n+\thash_cd_ctrl->hash_cfg_offset = ((char *)hash - (char *)cipher) >> 3;\n+\thash_cd_ctrl->hash_flags = ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED;\n+\thash_cd_ctrl->inner_res_sz = digestsize;\n+\thash_cd_ctrl->final_sz = digestsize;\n+\thash_cd_ctrl->inner_state1_sz = state1_size;\n+\n+\tswitch (cdesc->qat_hash_alg) {\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA1:\n+\t\thash_cd_ctrl->inner_state2_sz =\n+\t\t\tRTE_ALIGN_CEIL(ICP_QAT_HW_SHA1_STATE2_SZ, 8);\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA256:\n+\t\thash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA256_STATE2_SZ;\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_SHA512:\n+\t\thash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_SHA512_STATE2_SZ;\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC:\n+\t\thash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ;\n+\t\thash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ;\n+\t\tmemset(hash->sha.state1, 0, ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ);\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n+\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n+\t\thash_cd_ctrl->inner_state2_sz = ICP_QAT_HW_GALOIS_H_SZ +\n+\t\t\t\t\t\tICP_QAT_HW_GALOIS_LEN_A_SZ +\n+\t\t\t\t\t\tICP_QAT_HW_GALOIS_E_CTR0_SZ;\n+\t\thash_cd_ctrl->inner_state1_sz = ICP_QAT_HW_GALOIS_128_STATE1_SZ;\n+\t\tmemset(hash->sha.state1, 0, ICP_QAT_HW_GALOIS_128_STATE1_SZ);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"invalid HASH alg %u\", cdesc->qat_hash_alg);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\thash_cd_ctrl->inner_state2_offset = hash_cd_ctrl->hash_cfg_offset +\n+\t\t\t((sizeof(struct icp_qat_hw_auth_setup) +\n+\t\t\t RTE_ALIGN_CEIL(hash_cd_ctrl->inner_state1_sz, 8)) >> 3);\n+\tauth_param->auth_res_sz = digestsize;\n+\n+\n+\tif (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);\n+\t} else if (cdesc->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER) {\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_AUTH);\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(hash_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\t\tICP_QAT_FW_COMN_CURR_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\t\tICP_QAT_FW_COMN_NEXT_ID_SET(cipher_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"invalid param, only authenticated encryption supported\");\n+\t\treturn -EFAULT;\n+\t}\n+\treturn 0;\n+}\n+\n+static void qat_alg_ablkcipher_init_com(struct icp_qat_fw_la_bulk_req *req,\n+\t\t\t\t\tstruct icp_qat_hw_cipher_algo_blk *cd,\n+\t\t\t\t\tconst uint8_t *key, unsigned int keylen)\n+{\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;\n+\tstruct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;\n+\tstruct icp_qat_fw_cipher_cd_ctrl_hdr *cd_ctrl = (void *)&req->cd_ctrl;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\trte_memcpy(cd->aes.key, key, keylen);\n+\tqat_alg_init_common_hdr(header);\n+\theader->service_cmd_id = ICP_QAT_FW_LA_CMD_CIPHER;\n+\tcd_pars->u.s.content_desc_params_sz =\n+\t\t\t\tsizeof(struct icp_qat_hw_cipher_algo_blk) >> 3;\n+\t/* Cipher CD config setup */\n+\tcd_ctrl->cipher_key_sz = keylen >> 3;\n+\tcd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;\n+\tcd_ctrl->cipher_cfg_offset = 0;\n+\tICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl, ICP_QAT_FW_SLICE_CIPHER);\n+\tICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);\n+}\n+\n+void qat_alg_ablkcipher_init_enc(struct qat_alg_ablkcipher_cd *cdesc,\n+\t\t\t\t\tint alg, const uint8_t *key,\n+\t\t\t\t\tunsigned int keylen)\n+{\n+\tstruct icp_qat_hw_cipher_algo_blk *enc_cd = cdesc->cd;\n+\tstruct icp_qat_fw_la_bulk_req *req = &cdesc->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tqat_alg_ablkcipher_init_com(req, enc_cd, key, keylen);\n+\tcd_pars->u.s.content_desc_addr = cdesc->cd_paddr;\n+\tenc_cd->aes.cipher_config.val = QAT_AES_HW_CONFIG_CBC_ENC(alg);\n+}\n+\n+void qat_alg_ablkcipher_init_dec(struct qat_alg_ablkcipher_cd *cdesc,\n+\t\t\t\t\tint alg, const uint8_t *key,\n+\t\t\t\t\tunsigned int keylen)\n+{\n+\tstruct icp_qat_hw_cipher_algo_blk *dec_cd = cdesc->cd;\n+\tstruct icp_qat_fw_la_bulk_req *req = &cdesc->fw_req;\n+\tstruct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req->cd_pars;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tqat_alg_ablkcipher_init_com(req, dec_cd, key, keylen);\n+\tcd_pars->u.s.content_desc_addr = cdesc->cd_paddr;\n+\tdec_cd->aes.cipher_config.val = QAT_AES_HW_CONFIG_CBC_DEC(alg);\n+}\n+\n+int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg)\n+{\n+\tswitch (key_len) {\n+\tcase ICP_QAT_HW_AES_128_KEY_SZ:\n+\t\t*alg = ICP_QAT_HW_CIPHER_ALGO_AES128;\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AES_192_KEY_SZ:\n+\t\t*alg = ICP_QAT_HW_CIPHER_ALGO_AES192;\n+\t\tbreak;\n+\tcase ICP_QAT_HW_AES_256_KEY_SZ:\n+\t\t*alg = ICP_QAT_HW_CIPHER_ALGO_AES256;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+\treturn 0;\n+}\n+\ndiff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c\nnew file mode 100644\nindex 0000000..48961f0\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_crypto.c\n@@ -0,0 +1,505 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ *\t * Redistributions of source code must retain the above copyright\n+ *\t notice, this list of conditions and the following disclaimer.\n+ *\t * Redistributions in binary form must reproduce the above copyright\n+ *\t notice, this list of conditions and the following disclaimer in\n+ *\t the documentation and/or other materials provided with the\n+ *\t distribution.\n+ *\t * Neither the name of Intel Corporation nor the names of its\n+ *\t contributors may be used to endorse or promote products derived\n+ *\t from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <stdio.h>\n+#include <stdlib.h>\n+#include <strings.h>\n+#include <string.h>\n+#include <inttypes.h>\n+#include <errno.h>\n+#include <sys/queue.h>\n+#include <stdarg.h>\n+\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_debug.h>\n+#include <rte_memory.h>\n+#include <rte_memzone.h>\n+#include <rte_tailq.h>\n+#include <rte_ether.h>\n+#include <rte_malloc.h>\n+#include <rte_launch.h>\n+#include <rte_eal.h>\n+#include <rte_per_lcore.h>\n+#include <rte_lcore.h>\n+#include <rte_atomic.h>\n+#include <rte_branch_prediction.h>\n+#include <rte_ring.h>\n+#include <rte_mempool.h>\n+#include <rte_mbuf.h>\n+#include <rte_string_fns.h>\n+#include <rte_spinlock.h>\n+\n+#include \"qat_logs.h\"\n+#include \"qat_algs.h\"\n+#include \"qat_crypto.h\"\n+#include \"adf_transport_access_macros.h\"\n+\n+\n+static inline uint32_t adf_modulo(uint32_t data, uint32_t shift);\n+static inline int qat_alg_write_mbuf_entry(struct rte_mbuf *mbuf, uint8_t *out_msg);\n+\n+void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,\n+\t\tvoid *session)\n+{\n+\tstruct qat_session *sess = session;\n+\tphys_addr_t cd_paddr = sess->cd_paddr;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (session) {\n+\t\tmemset(sess, 0, qat_crypto_sym_get_session_private_size(dev));\n+\n+\t\tsess->cd_paddr = cd_paddr;\n+\t}\n+}\n+\n+static int\n+qat_get_cmd_id(const struct rte_crypto_xform *xform)\n+{\n+\tif (xform->next == NULL)\n+\t\treturn -1;\n+\n+\t/* Cipher Only */\n+\tif (xform->type == RTE_CRYPTO_XFORM_CIPHER && xform->next == NULL)\n+\t\treturn -1; /* return ICP_QAT_FW_LA_CMD_CIPHER; */\n+\n+\t/* Authentication Only */\n+\tif (xform->type == RTE_CRYPTO_XFORM_AUTH && xform->next == NULL)\n+\t\treturn -1; /* return ICP_QAT_FW_LA_CMD_AUTH; */\n+\n+\t/* Cipher then Authenticate */\n+\tif (xform->type == RTE_CRYPTO_XFORM_CIPHER &&\n+\t\t\txform->next->type == RTE_CRYPTO_XFORM_AUTH)\n+\t\treturn ICP_QAT_FW_LA_CMD_CIPHER_HASH;\n+\n+\t/* Authenticate then Cipher */\n+\tif (xform->type == RTE_CRYPTO_XFORM_AUTH &&\n+\t\t\txform->next->type == RTE_CRYPTO_XFORM_CIPHER)\n+\t\treturn ICP_QAT_FW_LA_CMD_HASH_CIPHER;\n+\n+\treturn -1;\n+}\n+\n+static struct rte_crypto_auth_xform *\n+qat_get_auth_xform(struct rte_crypto_xform *xform)\n+{\n+\tdo {\n+\t\tif (xform->type == RTE_CRYPTO_XFORM_AUTH)\n+\t\t\treturn &xform->auth;\n+\n+\t\txform = xform->next;\n+\t} while (xform);\n+\n+\treturn NULL;\n+}\n+\n+static struct rte_crypto_cipher_xform *\n+qat_get_cipher_xform(struct rte_crypto_xform *xform)\n+{\n+\tdo {\n+\t\tif (xform->type == RTE_CRYPTO_XFORM_CIPHER)\n+\t\t\treturn &xform->cipher;\n+\n+\t\txform = xform->next;\n+\t} while (xform);\n+\n+\treturn NULL;\n+}\n+\n+\n+void *\n+qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_xform *xform, void *session_private)\n+{\n+\tstruct qat_pmd_private *internals = dev->data->dev_private;\n+\n+\tstruct qat_session *session = session_private;\n+\n+\tstruct rte_crypto_auth_xform *auth_xform = NULL;\n+\tstruct rte_crypto_cipher_xform *cipher_xform = NULL;\n+\n+\tint qat_cmd_id;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* Get requested QAT command id */\n+\tqat_cmd_id = qat_get_cmd_id(xform);\n+\tif (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {\n+\t\tPMD_DRV_LOG(ERR, \"Unsupported xform chain requested\");\n+\t\tgoto error_out;\n+\t}\n+\tsession->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;\n+\n+\t/* Get cipher xform from crypto xform chain */\n+\tcipher_xform = qat_get_cipher_xform(xform);\n+\n+\tswitch (cipher_xform->algo) {\n+\tcase RTE_CRYPTO_SYM_CIPHER_AES_CBC:\n+\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_CIPHER_AES_GCM:\n+\t\tif (qat_alg_validate_aes_key(cipher_xform->key.length,\n+\t\t\t\t&session->qat_cipher_alg) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Invalid AES cipher key size\");\n+\t\t\tgoto error_out;\n+\t\t}\n+\t\tsession->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_CIPHER_NULL:\n+\tcase RTE_CRYPTO_SYM_CIPHER_3DES_ECB:\n+\tcase RTE_CRYPTO_SYM_CIPHER_3DES_CBC:\n+\tcase RTE_CRYPTO_SYM_CIPHER_AES_ECB:\n+\tcase RTE_CRYPTO_SYM_CIPHER_AES_CTR:\n+\tcase RTE_CRYPTO_SYM_CIPHER_AES_CCM:\n+\tcase RTE_CRYPTO_SYM_CIPHER_KASUMI_F8:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Unsupported Cipher alg %u\",\n+\t\t\t\tcipher_xform->algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Cipher specified %u\\n\",\n+\t\t\t\tcipher_xform->algo);\n+\t\tgoto error_out;\n+\t}\n+\n+\tif (cipher_xform->op == RTE_CRYPTO_SYM_CIPHER_OP_ENCRYPT)\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;\n+\telse\n+\t\tsession->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;\n+\n+\n+\t/* Get authentication xform from Crypto xform chain */\n+\tauth_xform = qat_get_auth_xform(xform);\n+\n+\tswitch (auth_xform->algo) {\n+\tcase RTE_CRYPTO_SYM_HASH_SHA1_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_HASH_SHA256_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_HASH_SHA512_HMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_HASH_AES_XCBC_MAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_HASH_AES_GCM:\n+\tcase RTE_CRYPTO_SYM_HASH_AES_GMAC:\n+\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;\n+\t\t/* TODO what about ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ? */\n+\t\tbreak;\n+\tcase RTE_CRYPTO_SYM_HASH_NONE:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA1:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA256:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA512:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA224:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA224_HMAC:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA384:\n+\tcase RTE_CRYPTO_SYM_HASH_SHA384_HMAC:\n+\tcase RTE_CRYPTO_SYM_HASH_MD5:\n+\tcase RTE_CRYPTO_SYM_HASH_MD5_HMAC:\n+\tcase RTE_CRYPTO_SYM_HASH_AES_CCM:\n+\tcase RTE_CRYPTO_SYM_HASH_KASUMI_F9:\n+\tcase RTE_CRYPTO_SYM_HASH_SNOW3G_UIA2:\n+\tcase RTE_CRYPTO_SYM_HASH_AES_CMAC:\n+\tcase RTE_CRYPTO_SYM_HASH_AES_CBC_MAC:\n+\tcase RTE_CRYPTO_SYM_HASH_ZUC_EIA3:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Unsupported hash alg %u\",\n+\t\t\t\tauth_xform->algo);\n+\t\tgoto error_out;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"Crypto: Undefined Hash algo %u specified\",\n+\t\t\t\tauth_xform->algo);\n+\t\tgoto error_out;\n+\t}\n+\n+\tif (qat_alg_aead_session_create_content_desc(session,\n+\t\tcipher_xform->key.data,\n+\t\tcipher_xform->key.length,\n+\t\tauth_xform->key.data,\n+\t\tauth_xform->key.length,\n+\t\tauth_xform->add_auth_data_length,\n+\t\tauth_xform->digest_length))\n+\t\tgoto error_out;\n+\n+\treturn (struct rte_cryptodev_session *)session;\n+\n+error_out:\n+\trte_mempool_put(internals->sess_mp, session);\n+\treturn NULL;\n+}\n+\n+unsigned qat_crypto_sym_get_session_private_size(\n+\t\tstruct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);\n+}\n+\n+\n+uint16_t qat_crypto_pkt_tx_burst(void *qp, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct qat_queue *queue;\n+\tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n+\tuint32_t nb_pkts_sent = 0;\n+\tstruct rte_mbuf **cur_tx_pkt = tx_pkts;\n+\tint ret = 0;\n+\n+\tqueue = &(tmp_qp->tx_q);\n+\twhile (nb_pkts_sent != nb_pkts) {\n+\t\tif (rte_atomic16_add_return(&tmp_qp->inflights16, 1) >\n+\t\t\t\t queue->max_inflights) {\n+\t\t\trte_atomic16_sub(&tmp_qp->inflights16, 1);\n+\t\t\tif (nb_pkts_sent == 0)\n+\t\t\t\treturn 0;\n+\t\t\telse\n+\t\t\t\tgoto kick_tail;\n+\t\t}\n+\t\tret = qat_alg_write_mbuf_entry(*cur_tx_pkt,\n+\t\t\t(uint8_t *)queue->base_addr + queue->tail);\n+\t\tif (ret != 0) {\n+\t\t\ttmp_qp->stats.enqueue_err_count++;\n+\t\t\tif (nb_pkts_sent == 0)\n+\t\t\t\treturn 0;\n+\t\t\telse\n+\t\t\t\tgoto kick_tail;\n+\t\t}\n+\n+\t\tqueue->tail = adf_modulo(queue->tail +\n+\t\t\t\tqueue->msg_size,\n+\t\t\t\tADF_RING_SIZE_MODULO(queue->queue_size));\n+\t\tnb_pkts_sent++;\n+\t\tcur_tx_pkt++;\n+\t}\n+kick_tail:\n+\tWRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,\n+\t\t\tqueue->hw_queue_number, queue->tail);\n+\ttmp_qp->stats.enqueued_count += nb_pkts_sent;\n+\treturn nb_pkts_sent;\n+}\n+\n+uint16_t\n+qat_crypto_pkt_rx_burst(void *qp, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tstruct qat_queue *queue;\n+\tstruct qat_qp *tmp_qp = (struct qat_qp *)qp;\n+\tuint32_t msg_counter = 0;\n+\tstruct rte_mbuf *rx_mbuf;\n+\tstruct icp_qat_fw_comn_resp *resp_msg;\n+\n+\tqueue = &(tmp_qp->rx_q);\n+\tresp_msg = (struct icp_qat_fw_comn_resp *)((uint8_t *)queue->base_addr + queue->head);\n+\twhile (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG && msg_counter != nb_pkts) {\n+\t\trx_mbuf = (struct rte_mbuf *)(resp_msg->opaque_data);\n+\t\tif (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=\n+\t\t\t\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(\n+\t\t\t\t\t\tresp_msg->comn_hdr.comn_status)) {\n+\t\t\trx_mbuf->ol_flags |= PKT_RX_CRYPTO_DIGEST_BAD;\n+\t\t}\n+\t\t*(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;\n+\t\tqueue->head = adf_modulo(queue->head +\n+\t\t\t\t\tqueue->msg_size,\n+\t\t\t\t\tADF_RING_SIZE_MODULO(queue->queue_size));\n+\t\tresp_msg = (struct icp_qat_fw_comn_resp *)\n+\t\t\t\t\t((uint8_t *)queue->base_addr + queue->head);\n+\n+\t\t*rx_pkts = rx_mbuf;\n+\t\trx_pkts++;\n+\t\tmsg_counter++;\n+\t}\n+\tif (msg_counter > 0) {\n+\t\tWRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,\n+\t\t\t\t\tqueue->hw_bundle_number,\n+\t\t\t\t\tqueue->hw_queue_number, queue->head);\n+\t\trte_atomic16_sub(&tmp_qp->inflights16, msg_counter);\n+\t\ttmp_qp->stats.dequeued_count += msg_counter;\n+\t}\n+\treturn msg_counter;\n+}\n+\n+static inline int qat_alg_write_mbuf_entry(struct rte_mbuf *mbuf, uint8_t *out_msg)\n+{\n+\tstruct rte_crypto_op_data *rte_op_data = mbuf->crypto_op;\n+\tstruct qat_session *ctx;\n+\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\tstruct icp_qat_fw_la_auth_req_params *auth_param;\n+\tstruct icp_qat_fw_la_bulk_req *qat_req;\n+\n+\tif (unlikely(rte_op_data->type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\tPMD_DRV_LOG(ERR, \"QAT PMD only supports session oriented requests \"\n+\t\t\t\t\"mbuf (%p) is sessionless.\", mbuf);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(rte_op_data->session->type != RTE_CRYPTODEV_QAT_PMD)) {\n+\t\tPMD_DRV_LOG(ERR, \"Session was not created for this device\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tctx = (struct qat_session *)rte_op_data->session->_private;\n+\tqat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;\n+\t*qat_req = ctx->fw_req;\n+\tqat_req->comn_mid.opaque_data = (uint64_t)mbuf;\n+\n+\t/*\n+\t * The following code assumes:\n+\t * - single entry buffer.\n+\t * - always in place.\n+\t */\n+\tqat_req->comn_mid.dst_length = qat_req->comn_mid.src_length = mbuf->data_len;\n+\tqat_req->comn_mid.dest_data_addr = qat_req->comn_mid.src_data_addr\n+\t\t\t\t\t\t\t= rte_pktmbuf_mtophys(mbuf);\n+\n+\tcipher_param = (void *)&qat_req->serv_specif_rqpars;\n+\tauth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));\n+\n+\tcipher_param->cipher_length = rte_op_data->data.to_cipher.length;\n+\tcipher_param->cipher_offset = rte_op_data->data.to_cipher.offset;\n+\tif (rte_op_data->iv.length &&\n+\t\t(rte_op_data->iv.length <= sizeof(cipher_param->u.cipher_IV_array))) {\n+\t\trte_memcpy(cipher_param->u.cipher_IV_array, rte_op_data->iv.data,\n+\t\t\t\t\t\t\trte_op_data->iv.length);\n+\t} else {\n+\t\tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(qat_req->comn_hdr.serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_CIPH_IV_64BIT_PTR);\n+\t\tcipher_param->u.s.cipher_IV_ptr = rte_op_data->iv.phys_addr;\n+\t}\n+\tif (rte_op_data->digest.phys_addr) {\n+\t\tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(qat_req->comn_hdr.serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER);\n+\t\tauth_param->auth_res_addr = rte_op_data->digest.phys_addr;\n+\t}\n+\tauth_param->auth_off = rte_op_data->data.to_hash.offset;\n+\tauth_param->auth_len = rte_op_data->data.to_hash.length;\n+\tauth_param->u1.aad_adr = rte_op_data->additional_auth.phys_addr;\n+\t/* (GCM) aad length(240 max) will be at this location after precompute */\n+\tif (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {\n+\t\tauth_param->u2.aad_sz =\n+\t\tALIGN_POW2_ROUNDUP(ctx->cd.hash.sha.state1[ICP_QAT_HW_GALOIS_128_STATE1_SZ +\n+\t\t\t\t\t\t\tICP_QAT_HW_GALOIS_H_SZ + 3], 16);\n+\t}\n+\tauth_param->hash_state_sz = (auth_param->u2.aad_sz) >> 3;\n+\treturn 0;\n+}\n+\n+static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)\n+{\n+\tuint32_t div = data >> shift;\n+\tuint32_t mult = div << shift;\n+\n+\treturn data - mult;\n+}\n+\n+void qat_crypto_sym_session_init(struct rte_mempool *mp, void *priv_sess)\n+{\n+\tstruct qat_session *s = priv_sess;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\ts->cd_paddr = rte_mempool_virt2phy(mp, &s->cd);\n+}\n+\n+int qat_dev_config(__rte_unused struct rte_cryptodev *dev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\treturn -ENOTSUP;\n+}\n+\n+int qat_dev_start(__rte_unused struct rte_cryptodev *dev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\treturn -ENOTSUP;\n+}\n+\n+void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+}\n+\n+int qat_dev_close(__rte_unused struct rte_cryptodev *dev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\treturn 0;\n+}\n+\n+void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,\n+\t\t\t\t\t\tstruct rte_cryptodev_info *info)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (info != NULL) {\n+\t\tinfo->max_queue_pairs =\n+\t\t\t\tADF_NUM_SYM_QPS_PER_BUNDLE*ADF_NUM_BUNDLES_PER_DEV;\n+\t\tinfo->dev_type = RTE_CRYPTODEV_QAT_PMD;\n+\t}\n+}\n+\n+void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_stats *stats)\n+{\n+\tint i;\n+\tstruct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (stats == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"invalid stats ptr NULL\");\n+\t\treturn;\n+\t}\n+\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n+\t\tif (qp[i] == NULL) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"Uninitialised queue pair\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tstats->enqueued_count += qp[i]->stats.enqueued_count;\n+\t\tstats->dequeued_count += qp[i]->stats.enqueued_count;\n+\t\tstats->enqueue_err_count += qp[i]->stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp[i]->stats.enqueue_err_count;\n+\t}\n+}\n+\n+void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)\n+{\n+\tint i;\n+\tstruct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tfor (i = 0; i < dev->data->nb_queue_pairs; i++)\n+\t\tmemset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));\n+\tPMD_DRV_LOG(DEBUG, \"QAT crypto: stats cleared\");\n+}\n+\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nnew file mode 100644\nindex 0000000..c58d833\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -0,0 +1,111 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _QAT_CRYPTO_H_\n+#define _QAT_CRYPTO_H_\n+\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_memzone.h>\n+\n+/*\tThis macro rounds up a number to a be a multiple of\n+ *\tthe alignment when the alignment is a power of 2 */\n+#define ALIGN_POW2_ROUNDUP(num, align) \\\n+\t(((num) + (align) - 1) & ~((align) - 1))\n+\n+/**\n+ * Structure associated with each queue.\n+ */\n+struct qat_queue {\n+\tchar\t\tmemz_name[RTE_MEMZONE_NAMESIZE];\n+\tvoid\t\t*base_addr;\t\t/* Base address */\n+\tphys_addr_t\tbase_phys_addr;\t\t/* Queue physical address */\n+\tuint32_t\thead;\t\t\t/* Shadow copy of the head */\n+\tuint32_t\ttail;\t\t\t/* Shadow copy of the tail */\n+\tuint32_t\tmsg_size;\n+\tuint16_t\tmax_inflights;\n+\tuint32_t\tqueue_size;\n+\tuint8_t\t\thw_bundle_number;\n+\tuint8_t\t\thw_queue_number;\t /* HW queue aka ring offset on bundle */\n+};\n+\n+struct qat_qp {\n+\tvoid\t\t\t*mmap_bar_addr;\n+\trte_atomic16_t\t\tinflights16;\n+\tstruct\tqat_queue\ttx_q;\n+\tstruct\tqat_queue\trx_q;\n+\tstruct\trte_cryptodev_stats stats;\n+} __rte_cache_aligned;\n+\n+/** private data structure for each QAT device */\n+struct qat_pmd_private {\n+\tchar sess_mp_name[RTE_MEMPOOL_NAMESIZE];\n+\tstruct rte_mempool *sess_mp;\n+};\n+\n+int qat_dev_config(struct rte_cryptodev *dev);\n+int qat_dev_start(struct rte_cryptodev *dev);\n+void qat_dev_stop(struct rte_cryptodev *dev);\n+int qat_dev_close(struct rte_cryptodev *dev);\n+void qat_dev_info_get(struct rte_cryptodev *dev,\n+\tstruct rte_cryptodev_info *info);\n+\n+void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,\n+\tstruct rte_cryptodev_stats *stats);\n+void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);\n+\n+int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,\n+\tconst struct rte_cryptodev_qp_conf *rx_conf, int socket_id);\n+void qat_crypto_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id);\n+\n+int\n+qat_pmd_session_mempool_create(struct rte_cryptodev *dev,\n+\tunsigned nb_objs, unsigned obj_cache_size, int socket_id);\n+\n+extern unsigned\n+qat_crypto_sym_get_session_private_size(struct rte_cryptodev *dev);\n+\n+extern void\n+qat_crypto_sym_session_init(struct rte_mempool *mempool, void *priv_sess);\n+\n+extern void *\n+qat_crypto_sym_configure_session(struct rte_cryptodev *dev,\n+\t\tstruct rte_crypto_xform *xform, void *session_private);\n+\n+extern void\n+qat_crypto_sym_clear_session(struct rte_cryptodev *dev, void *session);\n+\n+\n+uint16_t qat_crypto_pkt_tx_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n+uint16_t qat_crypto_pkt_rx_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n+\n+#endif /* _QAT_CRYPTO_H_ */\ndiff --git a/drivers/crypto/qat/qat_logs.h b/drivers/crypto/qat/qat_logs.h\nnew file mode 100644\nindex 0000000..a909f63\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_logs.h\n@@ -0,0 +1,78 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _QAT_LOGS_H_\n+#define _QAT_LOGS_H_\n+\n+#define PMD_INIT_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, RTE_LOGTYPE_PMD, \\\n+\t\t\"PMD: %s(): \" fmt \"\\n\", __func__, ##args)\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_INIT\n+#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n+#else\n+#define PMD_INIT_FUNC_TRACE() do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX\n+#define PMD_RX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_RX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX\n+#define PMD_TX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_TX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX_FREE\n+#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_PMD_QAT_DEBUG_DRIVER\n+#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n+#else\n+#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n+\n+#endif /* _QAT_LOGS_H_ */\ndiff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c\nnew file mode 100644\nindex 0000000..226e67a\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_qp.c\n@@ -0,0 +1,372 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_atomic.h>\n+#include <rte_prefetch.h>\n+\n+#include \"qat_logs.h\"\n+#include \"qat_crypto.h\"\n+#include \"adf_transport_access_macros.h\"\n+\n+#define ADF_MAX_SYM_DESC\t\t\t4096\n+#define ADF_MIN_SYM_DESC\t\t\t128\n+#define ADF_SYM_TX_RING_DESC_SIZE\t\t128\n+#define ADF_SYM_RX_RING_DESC_SIZE\t\t32\n+#define ADF_SYM_TX_QUEUE_STARTOFF\t\t2 /* Offset from bundle start to 1st Sym Tx queue */\n+#define ADF_SYM_RX_QUEUE_STARTOFF\t\t10\n+#define ADF_ARB_REG_SLOT\t\t\t0x1000\n+#define ADF_ARB_RINGSRVARBEN_OFFSET\t\t0x19C\n+\n+#define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \\\n+\tADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \\\n+\t(ADF_ARB_REG_SLOT * index), value)\n+\n+static int qat_qp_check_queue_alignment(uint64_t phys_addr,\n+\tuint32_t queue_size_bytes);\n+static int qat_tx_queue_create(struct rte_cryptodev *dev,\n+\tstruct qat_queue *queue, uint8_t id, uint32_t nb_desc,\n+\tint socket_id);\n+static int qat_rx_queue_create(struct rte_cryptodev *dev,\n+\tstruct qat_queue *queue, uint8_t id, uint32_t nb_desc,\n+\tint socket_id);\n+static int qat_queue_create(struct rte_cryptodev *dev,\n+\tstruct qat_queue *queue, uint32_t nb_desc, uint8_t desc_size,\n+\tint socket_id);\n+static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n+\tuint32_t *queue_size_for_csr);\n+static void adf_configure_queues(struct qat_qp *queue);\n+static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr);\n+static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr);\n+\n+static const struct rte_memzone *\n+queue_dma_zone_reserve(const char *qp_name, uint32_t queue_size, int socket_id)\n+{\n+\tconst struct rte_memzone *mz;\n+\tunsigned memzone_flags = 0;\n+\tconst struct rte_memseg *ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tmz = rte_memzone_lookup(qp_name);\n+\tif (mz != 0) {\n+\t\tif (((size_t)queue_size <= mz->len) &&\n+\t\t\t\t((socket_id == SOCKET_ID_ANY) ||\n+\t\t\t\t\t(socket_id == mz->socket_id))) {\n+\t\t\tPMD_DRV_LOG(DEBUG, \"re-use memzone already allocated for %s\", qp_name);\n+\t\t\treturn mz;\n+\t\t} else {\n+\t\t\tPMD_DRV_LOG(ERR, \"Incompatible memzone already allocated %s, \"\n+\t\t\t\t\t\"size %u, socket %d. Requested size %u, socket %u\",\n+\t\t\t\t\tqp_name, (uint32_t)mz->len, mz->socket_id,\n+\t\t\t\t\tqueue_size, socket_id);\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n+\n+\tPMD_DRV_LOG(DEBUG, \"Allocate memzone for %s, size %u on socket %u\",\n+\t\t\t\t\tqp_name, queue_size, socket_id);\n+\tms = rte_eal_get_physmem_layout();\n+\tswitch (ms[0].hugepage_sz) {\n+\tcase(RTE_PGSIZE_2M):\n+\t\tmemzone_flags = RTE_MEMZONE_2MB;\n+\tbreak;\n+\tcase(RTE_PGSIZE_1G):\n+\t\tmemzone_flags = RTE_MEMZONE_1GB;\n+\tbreak;\n+\tcase(RTE_PGSIZE_16M):\n+\t\tmemzone_flags = RTE_MEMZONE_16MB;\n+\tbreak;\n+\tcase(RTE_PGSIZE_16G):\n+\t\tmemzone_flags = RTE_MEMZONE_16GB;\n+\tbreak;\n+\tdefault:\n+\t\tmemzone_flags = RTE_MEMZONE_SIZE_HINT_ONLY;\n+}\n+#ifdef RTE_LIBRTE_XEN_DOM0\n+\treturn rte_memzone_reserve_bounded(qp_name, queue_size,\n+\t\tsocket_id, 0, RTE_CACHE_LINE_SIZE, RTE_PGSIZE_2M);\n+#else\n+\treturn rte_memzone_reserve_aligned(qp_name, queue_size, socket_id,\n+\t\tmemzone_flags, queue_size);\n+#endif\n+}\n+\n+int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,\n+\tconst struct rte_cryptodev_qp_conf *qp_conf,\n+\tint socket_id)\n+{\n+\tstruct qat_qp *qp;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif ((qp_conf->nb_descriptors > ADF_MAX_SYM_DESC) ||\n+\t\t(qp_conf->nb_descriptors < ADF_MIN_SYM_DESC)) {\n+\t\tPMD_DRV_LOG(ERR, \"Can't create qp for %u descriptors\",\n+\t\t\t\tqp_conf->nb_descriptors);\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\tif ((dev->pci_dev->mem_resource == NULL) ||\n+\t\t(dev->pci_dev->mem_resource[0].addr == NULL)) {\n+\t\tPMD_DRV_LOG(ERR, \"Could not find VF config space (UIO driver attached?).\");\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\tif (queue_pair_id >= (ADF_NUM_SYM_QPS_PER_BUNDLE*ADF_NUM_BUNDLES_PER_DEV)) {\n+\t\tPMD_DRV_LOG(ERR, \"qp_id %u invalid for this device\", queue_pair_id);\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (dev->data->queue_pairs[queue_pair_id] != NULL) {\n+\t\tqat_crypto_sym_qp_release(dev, queue_pair_id);\n+\t\tdev->data->queue_pairs[queue_pair_id] = NULL;\n+\t}\n+\n+\t/* Allocate the queue pair data structure. */\n+\tqp = rte_zmalloc(\"qat PMD qp queue\", sizeof(*qp), RTE_CACHE_LINE_SIZE);\n+\tif (qp == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to alloc mem for qp struct\");\n+\t\treturn (-ENOMEM);\n+\t}\n+\tqp->mmap_bar_addr = dev->pci_dev->mem_resource[0].addr;\n+\trte_atomic16_init(&qp->inflights16);\n+\n+\tif (qat_tx_queue_create(dev, &(qp->tx_q),\n+\t\t\tqueue_pair_id, qp_conf->nb_descriptors, socket_id) != 0) {\n+\t\tPMD_INIT_LOG(ERR, \"Tx queue create failed \"\n+\t\t\t\t\"queue_pair_id=%u\", queue_pair_id);\n+\t\tgoto create_err;\n+\t}\n+\n+\tif (qat_rx_queue_create(dev, &(qp->rx_q),\n+\t\t\tqueue_pair_id, qp_conf->nb_descriptors, socket_id) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Rx queue create failed \"\n+\t\t\t\t\"queue_pair_id=%hu\", queue_pair_id);\n+\t\tgoto create_err;\n+\t}\n+\tdev->data->queue_pairs[queue_pair_id] = qp;\n+\tadf_configure_queues(qp);\n+\tadf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr);\n+\treturn 0;\n+\n+create_err:\n+\trte_free(qp);\n+\treturn (-EFAULT);\n+}\n+\n+void qat_crypto_sym_qp_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)\n+{\n+\tstruct qat_qp *qp = (struct qat_qp *)dev->data->queue_pairs[queue_pair_id];\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (qp == NULL) {\n+\t\tPMD_DRV_LOG(DEBUG, \"qp already freed\");\n+\t\treturn;\n+\t}\n+\n+\tadf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr);\n+\trte_free(qp);\n+}\n+\n+static int qat_tx_queue_create(struct rte_cryptodev *dev,\n+\tstruct qat_queue *queue, uint8_t qp_id,\n+\tuint32_t nb_desc, int socket_id)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tqueue->hw_bundle_number = qp_id/ADF_NUM_SYM_QPS_PER_BUNDLE;\n+\tqueue->hw_queue_number = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +\n+\t\t\t\t\t\tADF_SYM_TX_QUEUE_STARTOFF;\n+\tPMD_DRV_LOG(DEBUG, \"TX ring for %u msgs: qp_id %d, bundle %u, ring %u\",\n+\t\tnb_desc, qp_id, queue->hw_bundle_number, queue->hw_queue_number);\n+\n+\treturn qat_queue_create(dev, queue, nb_desc,\n+\t\t\t\tADF_SYM_TX_RING_DESC_SIZE, socket_id);\n+}\n+\n+static int qat_rx_queue_create(struct rte_cryptodev *dev,\n+\t\tstruct qat_queue *queue, uint8_t qp_id, uint32_t nb_desc,\n+\t\tint socket_id)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tqueue->hw_bundle_number = qp_id/ADF_NUM_SYM_QPS_PER_BUNDLE;\n+\tqueue->hw_queue_number = (qp_id%ADF_NUM_SYM_QPS_PER_BUNDLE) +\n+\t\t\t\t\t\tADF_SYM_RX_QUEUE_STARTOFF;\n+\n+\tPMD_DRV_LOG(DEBUG, \"RX ring for %u msgs: qp id %d, bundle %u, ring %u\",\n+\t\tnb_desc, qp_id, queue->hw_bundle_number, queue->hw_queue_number);\n+\treturn qat_queue_create(dev, queue, nb_desc,\n+\t\t\t\tADF_SYM_RX_RING_DESC_SIZE, socket_id);\n+}\n+\n+static int\n+qat_queue_create(struct rte_cryptodev *dev, struct qat_queue *queue,\n+\t\tuint32_t nb_desc, uint8_t desc_size, int socket_id)\n+{\n+\tuint64_t queue_base;\n+\tvoid *io_addr;\n+\tconst struct rte_memzone *qp_mz;\n+\tuint32_t queue_size_bytes = nb_desc*desc_size;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid descriptor size %d\", desc_size);\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\t/*\n+\t * Allocate a memzone for the queue - create a unique name.\n+\t */\n+\tsnprintf(queue->memz_name, sizeof(queue->memz_name), \"%s_%s_%d_%d_%d\",\n+\t\tdev->driver->pci_drv.name, \"qp_mem\", dev->data->dev_id,\n+\t\tqueue->hw_bundle_number, queue->hw_queue_number);\n+\tqp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes, socket_id);\n+\tif (qp_mz == NULL) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate ring memzone\");\n+\t\treturn (-ENOMEM);\n+\t}\n+\n+\tqueue->base_addr = (char *)qp_mz->addr;\n+\tqueue->base_phys_addr = qp_mz->phys_addr;\n+\tif (qat_qp_check_queue_alignment(queue->base_phys_addr, queue_size_bytes)) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid alignment on queue create \"\n+\t\t\t\t\t\" 0x%\"PRIx64\"\\n\", queue->base_phys_addr);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tif (adf_verify_queue_size(desc_size, nb_desc, &(queue->queue_size)) != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid num inflights\");\n+\t\treturn (-EINVAL);\n+\t}\n+\n+\tqueue->max_inflights = ADF_MAX_INFLIGHTS(queue->queue_size,\n+\t\t\t\t\tADF_BYTES_TO_MSG_SIZE(desc_size));\n+\tPMD_DRV_LOG(DEBUG, \"RING size in CSR: %u, in bytes %u, nb msgs %u,\"\n+\t\t\t\t\" msg_size %u, max_inflights %u \",\n+\t\t\t\tqueue->queue_size, queue_size_bytes,\n+\t\t\t\tnb_desc, desc_size, queue->max_inflights);\n+\n+\tif (queue->max_inflights < 2) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid num inflights\");\n+\t\treturn (-EINVAL);\n+\t}\n+\tqueue->head = 0;\n+\tqueue->tail = 0;\n+\tqueue->msg_size = desc_size;\n+\n+\t/*\n+\t * Write an unused pattern to the queue memory.\n+\t */\n+\tmemset(queue->base_addr, 0x7F, queue_size_bytes);\n+\n+\tqueue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,\n+\t\t\t\t\tqueue->queue_size);\n+\tio_addr = dev->pci_dev->mem_resource[0].addr;\n+\n+\tWRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,\n+\t\t\tqueue->hw_queue_number, queue_base);\n+\treturn 0;\n+}\n+\n+static int qat_qp_check_queue_alignment(uint64_t phys_addr,\n+\t\t\t\t\tuint32_t queue_size_bytes)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tif (((queue_size_bytes - 1) & phys_addr) != 0)\n+\t\treturn (-EINVAL);\n+\treturn 0;\n+}\n+\n+static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,\n+\tuint32_t *p_queue_size_for_csr)\n+{\n+\tuint8_t i = ADF_MIN_RING_SIZE;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tfor (; i <= ADF_MAX_RING_SIZE; i++)\n+\t\tif ((msg_size * msg_num) ==\n+\t\t\t\t(uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {\n+\t\t\t*p_queue_size_for_csr = i;\n+\t\t\treturn 0;\n+\t\t}\n+\tPMD_DRV_LOG(ERR, \"Invalid ring size %d\", msg_size * msg_num);\n+\treturn (-EINVAL);\n+}\n+\n+static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr)\n+{\n+\tuint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t\t\t(ADF_ARB_REG_SLOT * txq->hw_bundle_number);\n+\tuint32_t value;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tvalue = ADF_CSR_RD(base_addr, arb_csr_offset);\n+\tvalue |= (0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+}\n+\n+static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr)\n+{\n+\tuint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t\t\t\t\t(ADF_ARB_REG_SLOT * txq->hw_bundle_number);\n+\tuint32_t value;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tvalue = ADF_CSR_RD(base_addr, arb_csr_offset);\n+\tvalue ^= (0x01 << txq->hw_queue_number);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+}\n+\n+static void adf_configure_queues(struct qat_qp *qp)\n+{\n+\tuint32_t queue_config;\n+\tstruct qat_queue *queue = &qp->tx_q;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tqueue_config = BUILD_RING_CONFIG(queue->queue_size);\n+\n+\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,\n+\t\t\tqueue->hw_queue_number, queue_config);\n+\n+\tqueue = &qp->rx_q;\n+\tqueue_config =\n+\t\t\tBUILD_RESP_RING_CONFIG(queue->queue_size,\n+\t\t\t\t\tADF_RING_NEAR_WATERMARK_512,\n+\t\t\t\t\tADF_RING_NEAR_WATERMARK_0);\n+\n+\tWRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,\n+\t\t\tqueue->hw_queue_number, queue_config);\n+}\ndiff --git a/drivers/crypto/qat/rte_pmd_qat_version.map b/drivers/crypto/qat/rte_pmd_qat_version.map\nnew file mode 100644\nindex 0000000..fcf5bb3\n--- /dev/null\n+++ b/drivers/crypto/qat/rte_pmd_qat_version.map\n@@ -0,0 +1,5 @@\n+DPDK_2.0 {\n+\tglobal:\n+\n+\tlocal: *;\n+};\ndiff --git a/drivers/crypto/qat/rte_qat_cryptodev.c b/drivers/crypto/qat/rte_qat_cryptodev.c\nnew file mode 100644\nindex 0000000..49a936f\n--- /dev/null\n+++ b/drivers/crypto/qat/rte_qat_cryptodev.c\n@@ -0,0 +1,130 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_dev.h>\n+#include <rte_malloc.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"qat_crypto.h\"\n+#include \"qat_logs.h\"\n+\n+static struct rte_cryptodev_ops crypto_qat_ops = {\n+\n+\t\t/* Device related operations */\n+\t\t.dev_configure\t\t= qat_dev_config,\n+\t\t.dev_start\t\t= qat_dev_start,\n+\t\t.dev_stop\t\t= qat_dev_stop,\n+\t\t.dev_close\t\t= qat_dev_close,\n+\t\t.dev_infos_get\t\t= qat_dev_info_get,\n+\n+\t\t.stats_get\t\t= qat_crypto_sym_stats_get,\n+\t\t.stats_reset\t\t= qat_crypto_sym_stats_reset,\n+\t\t.queue_pair_setup\t= qat_crypto_sym_qp_setup,\n+\t\t.queue_pair_release\t= qat_crypto_sym_qp_release,\n+\t\t.queue_pair_start\t= NULL,\n+\t\t.queue_pair_stop\t= NULL,\n+\t\t.queue_pair_count\t= NULL,\n+\n+\t\t/* Crypto related operations */\n+\t\t.session_get_size\t= qat_crypto_sym_get_session_private_size,\n+\t\t.session_configure\t= qat_crypto_sym_configure_session,\n+\t\t.session_initialize\t= qat_crypto_sym_session_init,\n+\t\t.session_clear\t\t= qat_crypto_sym_clear_session\n+};\n+\n+/*\n+ * The set of PCI devices this driver supports\n+ */\n+\n+static struct rte_pci_id pci_id_qat_map[] = {\n+\t\t{\n+\t\t\t.vendor_id = 0x8086,\n+\t\t\t.device_id = 0x0443,\n+\t\t\t.subsystem_vendor_id = PCI_ANY_ID,\n+\t\t\t.subsystem_device_id = PCI_ANY_ID\n+\t\t},\n+\t\t{.device_id = 0},\n+};\n+\n+static int\n+crypto_qat_dev_init(__attribute__((unused)) struct rte_cryptodev_driver *crypto_drv,\n+\t\t\tstruct rte_cryptodev *cryptodev)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\tPMD_DRV_LOG(DEBUG, \"Found crypto device at %02x:%02x.%x\",\n+\t\tcryptodev->pci_dev->addr.bus,\n+\t\tcryptodev->pci_dev->addr.devid,\n+\t\tcryptodev->pci_dev->addr.function);\n+\n+\tcryptodev->dev_type = RTE_CRYPTODEV_QAT_PMD;\n+\tcryptodev->dev_ops = &crypto_qat_ops;\n+\n+\tcryptodev->enqueue_burst = qat_crypto_pkt_tx_burst;\n+\tcryptodev->dequeue_burst = qat_crypto_pkt_rx_burst;\n+\n+\t/* for secondary processes, we don't initialise any further as primary\n+\t * has already done this work. Only check we don't need a different\n+\t * RX function */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Device already initialised by primary process\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct rte_cryptodev_driver rte_qat_pmd = {\n+\t{\n+\t\t.name = \"rte_qat_pmd\",\n+\t\t.id_table = pci_id_qat_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t},\n+\t.cryptodev_init = crypto_qat_dev_init,\n+\t.dev_private_size = sizeof(struct qat_pmd_private),\n+};\n+\n+static int\n+rte_qat_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\treturn rte_cryptodev_pmd_driver_register(&rte_qat_pmd, PMD_PDEV);\n+}\n+\n+static struct rte_driver pmd_qat_drv = {\n+\t.type = PMD_PDEV,\n+\t.init = rte_qat_pmd_init,\n+};\n+\n+PMD_REGISTER_DRIVER(pmd_qat_drv);\n+\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 4a3c41b..dd48bea 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -144,6 +144,9 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += -lrte_pmd_pcap\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += -lrte_pmd_af_packet\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += -lrte_pmd_null\n \n+# QAT PMD has a dependency on libcrypto (from openssl) for calculating HMAC precomputes\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_QAT) += -lrte_pmd_qat -lcrypto\n+\n endif # ! $(CONFIG_RTE_BUILD_SHARED_LIB)\n \n endif # ! CONFIG_RTE_BUILD_COMBINE_LIBS\n", "prefixes": [ "dpdk-dev", "2/6" ] }