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GET /api/patches/7378/?format=api
{ "id": 7378, "url": "https://patches.dpdk.org/api/patches/7378/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443822602-8648-2-git-send-email-david.hunt@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443822602-8648-2-git-send-email-david.hunt@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443822602-8648-2-git-send-email-david.hunt@intel.com", "date": "2015-10-02T21:50:02", "name": "[dpdk-dev] lib: added support for armv7 architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3269f22cc1b719a2cb704c9b425f45e00377960f", "submitter": { "id": 342, "url": "https://patches.dpdk.org/api/people/342/?format=api", "name": "Hunt, David", "email": "david.hunt@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443822602-8648-2-git-send-email-david.hunt@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7378/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7378/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 7CCDF8E72;\n\tFri, 2 Oct 2015 23:50:34 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 19A8D8E71\n\tfor <dev@dpdk.org>; Fri, 2 Oct 2015 23:50:32 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby fmsmga101.fm.intel.com with ESMTP; 02 Oct 2015 14:50:32 -0700", "from irvmail001.ir.intel.com ([163.33.26.43])\n\tby orsmga002.jf.intel.com with ESMTP; 02 Oct 2015 14:50:31 -0700", "from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com\n\t[10.237.217.46])\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n\tt92LoUPW017489; Fri, 2 Oct 2015 22:50:30 +0100", "from sivswdev02.ir.intel.com (localhost [127.0.0.1])\n\tby sivswdev02.ir.intel.com with ESMTP id t92LoUIK009123;\n\tFri, 2 Oct 2015 22:50:30 +0100", "(from dhunt5@localhost)\n\tby sivswdev02.ir.intel.com with id t92LoUZW009119;\n\tFri, 2 Oct 2015 22:50:30 +0100" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,624,1437462000\"; d=\"scan'208\";a=\"818242115\"", "From": "David Hunt <david.hunt@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 2 Oct 2015 22:50:02 +0100", "Message-Id": "<1443822602-8648-2-git-send-email-david.hunt@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1443822602-8648-1-git-send-email-david.hunt@intel.com>", "References": "<1443822602-8648-1-git-send-email-david.hunt@intel.com>", "Subject": "[dpdk-dev] [PATCH] lib: added support for armv7 architecture", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Amruta Zende <amruta.zende@intel.com>\n\nSigned-off-by: Amruta Zende <amruta.zende@intel.com>\nSigned-off-by: David Hunt <david.hunt@intel.com>\n---\n MAINTAINERS | 5 +\n config/defconfig_arm-native-linuxapp-gcc | 56 ++++\n .../common/include/arch/arm/rte_atomic.h | 269 ++++++++++++++++++++\n .../common/include/arch/arm/rte_byteorder.h | 146 +++++++++++\n .../common/include/arch/arm/rte_cpuflags.h | 138 ++++++++++\n .../common/include/arch/arm/rte_cycles.h | 77 ++++++\n .../common/include/arch/arm/rte_memcpy.h | 101 ++++++++\n .../common/include/arch/arm/rte_prefetch.h | 64 +++++\n .../common/include/arch/arm/rte_rwlock.h | 70 +++++\n .../common/include/arch/arm/rte_spinlock.h | 116 +++++++++\n lib/librte_eal/common/include/arch/arm/rte_vect.h | 37 +++\n lib/librte_eal/linuxapp/Makefile | 3 +\n lib/librte_eal/linuxapp/arm_pmu/Makefile | 52 ++++\n lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c | 83 ++++++\n mk/arch/arm/rte.vars.mk | 58 +++++\n mk/machine/armv7-a/rte.vars.mk | 63 +++++\n mk/toolchain/gcc/rte.vars.mk | 8 +-\n 17 files changed, 1343 insertions(+), 3 deletions(-)\n create mode 100644 config/defconfig_arm-native-linuxapp-gcc\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h\n create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h\n create mode 100755 lib/librte_eal/linuxapp/arm_pmu/Makefile\n create mode 100644 lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c\n create mode 100644 mk/arch/arm/rte.vars.mk\n create mode 100644 mk/machine/armv7-a/rte.vars.mk", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 080a8e8..9d99d53 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -124,6 +124,11 @@ IBM POWER\n M: Chao Zhu <chaozhu@linux.vnet.ibm.com>\n F: lib/librte_eal/common/include/arch/ppc_64/\n \n+Arm V7\n+M: Amrute Zende <amruta.zende@intel.com>\n+M: David Hunt <david.hunt@intel.com>\n+F: lib/librte_eal/common/include/arch/arm/\n+\n Intel x86\n M: Bruce Richardson <bruce.richardson@intel.com>\n M: Konstantin Ananyev <konstantin.ananyev@intel.com>\ndiff --git a/config/defconfig_arm-native-linuxapp-gcc b/config/defconfig_arm-native-linuxapp-gcc\nnew file mode 100644\nindex 0000000..159aa36\n--- /dev/null\n+++ b/config/defconfig_arm-native-linuxapp-gcc\n@@ -0,0 +1,56 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2015 Intel Corporation. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+#\n+\n+#include \"common_linuxapp\"\n+\n+CONFIG_RTE_MACHINE=\"armv7-a\"\n+\n+CONFIG_RTE_ARCH=\"arm\"\n+CONFIG_RTE_ARCH_ARM32=y\n+CONFIG_RTE_ARCH_32=y\n+\n+CONFIG_RTE_TOOLCHAIN=\"gcc\"\n+CONFIG_RTE_TOOLCHAIN_GCC=y\n+\n+CONFIG_RTE_FORCE_INTRINSICS=y\n+CONFIG_RTE_LIBRTE_VHOST=n\n+CONFIG_RTE_LIBRTE_KNI=n\n+CONFIG_RTE_KNI_KMOD=n\n+CONFIG_RTE_LIBRTE_LPM=n\n+CONFIG_RTE_LIBRTE_ACL=n\n+CONFIG_RTE_LIBRTE_SCHED=n\n+CONFIG_RTE_LIBRTE_PORT=n\n+CONFIG_RTE_LIBRTE_PIPELINE=n\n+CONFIG_RTE_LIBRTE_TABLE=n\n+CONFIG_RTE_IXGBE_INC_VECTOR=n\n+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n\n+CONFIG_RTE_LIBRTE_CXGBE_PMD=n\n+\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\nnew file mode 100644\nindex 0000000..2a7339c\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h\n@@ -0,0 +1,269 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_ATOMIC_ARM32_H_\n+#define _RTE_ATOMIC_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * @file\n+ * Atomic Operations\n+ *\n+ * This file defines a API for atomic operations.\n+ */\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ */\n+#define\trte_mb() { __sync_synchronize(); }\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ */\n+#define\trte_wmb() {asm volatile(\"dsb st\" : : : \"memory\"); }\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ */\n+#define\trte_rmb() {asm volatile(\"dsb \" : : : \"memory\"); }\n+\n+\n+\n+/*------------------------- 16 bit atomic operations -------------------------*/\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+static inline int\n+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic16_inc(rte_atomic16_t *v)\n+{\n+\trte_atomic16_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic16_dec(rte_atomic16_t *v)\n+{\n+\trte_atomic16_sub(v, 1);\n+}\n+\n+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n+{\n+\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n+}\n+\n+\n+/*------------------------- 32 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic32_inc(rte_atomic32_t *v)\n+{\n+\trte_atomic32_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic32_dec(rte_atomic32_t *v)\n+{\n+\trte_atomic32_sub(v, 1);\n+}\n+\n+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n+{\n+\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n+}\n+\n+/*------------------------- 64 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic64_init(rte_atomic64_t *v)\n+{\n+#ifdef __LP64__\n+\tv->cnt = 0;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\ttmp, 0);\n+\t}\n+#endif\n+}\n+\n+static inline int64_t\n+rte_atomic64_read(rte_atomic64_t *v)\n+{\n+#ifdef __LP64__\n+\treturn v->cnt;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\t/* replace the value by itself */\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\ttmp, tmp);\n+\t}\n+\treturn tmp;\n+#endif\n+}\n+\n+static inline void\n+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n+{\n+#ifdef __LP64__\n+\tv->cnt = new_value;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\ttmp, new_value);\n+\t}\n+#endif\n+}\n+\n+static inline void\n+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n+{\n+\t__sync_fetch_and_add(&v->cnt, inc);\n+}\n+\n+static inline void\n+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n+{\n+\t__sync_fetch_and_sub(&v->cnt, dec);\n+}\n+\n+static inline void\n+rte_atomic64_inc(rte_atomic64_t *v)\n+{\n+\trte_atomic64_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic64_dec(rte_atomic64_t *v)\n+{\n+\trte_atomic64_sub(v, 1);\n+}\n+\n+static inline int64_t\n+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n+{\n+\treturn __sync_add_and_fetch(&v->cnt, inc);\n+}\n+\n+static inline int64_t\n+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n+{\n+\treturn __sync_sub_and_fetch(&v->cnt, dec);\n+}\n+\n+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_add_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_sub_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void rte_atomic64_clear(rte_atomic64_t *v)\n+{\n+\trte_atomic64_set(v, 0);\n+}\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_byteorder.h b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h\nnew file mode 100644\nindex 0000000..effbd62\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h\n@@ -0,0 +1,146 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014. All rights reserved.\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+/* Inspired from FreeBSD src/sys/powerpc/include/endian.h\n+ * Copyright (c) 1987, 1991, 1993\n+ * The Regents of the University of California. All rights reserved.\n+*/\n+\n+#ifndef _RTE_BYTEORDER_ARM32_H_\n+#define _RTE_BYTEORDER_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_byteorder.h\"\n+\n+/*\n+ * An architecture-optimized byte swap for a 16-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap16().\n+ */\n+static inline uint16_t\n+rte_arch_bswap16(uint16_t _x)\n+{\n+\treturn __builtin_bswap16(_x);\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 32-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap32().\n+ */\n+static inline uint32_t\n+rte_arch_bswap32(uint32_t _x)\n+{\n+\treturn __builtin_bswap32(_x);\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 64-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap64().\n+ */\n+/* 64-bit mode */\n+static inline uint64_t\n+rte_arch_bswap64(uint64_t _x)\n+{\n+\treturn __builtin_bswap64(_x);\n+}\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n+\t\t\trte_constant_bswap16(x) :\t\t\\\n+\t\t\trte_arch_bswap16(x)))\n+\n+#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?\t\t\\\n+\t\t\trte_constant_bswap32(x) :\t\t\\\n+\t\t\trte_arch_bswap32(x)))\n+\n+#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ?\t\t\\\n+\t\t\trte_constant_bswap64(x) :\t\t\\\n+\t\t\trte_arch_bswap64(x)))\n+#else\n+\t\t/*\n+\t\t * __builtin_bswap16 is only available gcc 4.8 and upwards\n+\t\t */\n+#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)\n+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n+\t\t\trte_constant_bswap16(x) :\t\t\\\n+\t\t\trte_arch_bswap16(x)))\n+#endif\n+#endif\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define rte_cpu_to_le_16(x) (x)\n+#define rte_cpu_to_le_32(x) (x)\n+#define rte_cpu_to_le_64(x) (x)\n+\n+#define rte_cpu_to_be_16(x) rte_bswap16(x)\n+#define rte_cpu_to_be_32(x) rte_bswap32(x)\n+#define rte_cpu_to_be_64(x) rte_bswap64(x)\n+\n+#define rte_le_to_cpu_16(x) (x)\n+#define rte_le_to_cpu_32(x) (x)\n+#define rte_le_to_cpu_64(x) (x)\n+\n+#define rte_be_to_cpu_16(x) rte_bswap16(x)\n+#define rte_be_to_cpu_32(x) rte_bswap32(x)\n+#define rte_be_to_cpu_64(x) rte_bswap64(x)\n+\n+#else /* RTE_BIG_ENDIAN */\n+\n+#define rte_cpu_to_le_16(x) rte_bswap16(x)\n+#define rte_cpu_to_le_32(x) rte_bswap32(x)\n+#define rte_cpu_to_le_64(x) rte_bswap64(x)\n+\n+#define rte_cpu_to_be_16(x) (x)\n+#define rte_cpu_to_be_32(x) (x)\n+#define rte_cpu_to_be_64(x) (x)\n+\n+#define rte_le_to_cpu_16(x) rte_bswap16(x)\n+#define rte_le_to_cpu_32(x) rte_bswap32(x)\n+#define rte_le_to_cpu_64(x) rte_bswap64(x)\n+\n+#define rte_be_to_cpu_16(x) (x)\n+#define rte_be_to_cpu_32(x) (x)\n+#define rte_be_to_cpu_64(x) (x)\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_BYTEORDER_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..411ca37\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h\n@@ -0,0 +1,138 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014. All rights reserved.\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CPUFLAGS_ARM32_H_\n+#define _RTE_CPUFLAGS_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+/* Symbolic values for the entries in the auxiliary table */\n+#define AT_HWCAP 16\n+#define AT_HWCAP2 26\n+#define AT_PLATFORM 15\n+\n+/* software based registers */\n+enum cpu_register_t {\n+\tREG_HWCAP = 0,\n+\tAARCH_MODE,\n+};\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_FP = 0,\n+\tRTE_CPUFLAG_ASIMD,\n+\tRTE_CPUFLAG_EVTSTRM,\n+\tRTE_CPUFLAG_AARCH64,\n+\tRTE_CPUFLAG_AARCH32,\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+\tFEAT_DEF(FP, 0x00000001, 0, REG_HWCAP, 0)\n+\tFEAT_DEF(ASIMD, 0x00000001, 0, REG_HWCAP, 1)\n+\tFEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 2)\n+\tFEAT_DEF(AARCH64, 0x00000001, 0, AARCH_MODE, 3)\n+\tFEAT_DEF(AARCH32, 0x00000001, 0, AARCH_MODE, 4)\n+};\n+\n+/*\n+ * Read AUXV software register and get cpu features for Power\n+ */\n+static inline void\n+rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,\n+\t__attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)\n+{\n+\tint auxv_fd;\n+\tElf32_auxv_t auxv;\n+\n+\tauxv_fd = open(\"/proc/self/auxv\", O_RDONLY);\n+\tassert(auxv_fd);\n+\twhile (read(auxv_fd, &auxv,\n+\t\tsizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {\n+\t\tif (auxv.a_type == AT_HWCAP)\n+\t\t\tout[REG_HWCAP] = auxv.a_un.a_val;\n+\t\tif (auxv.a_type == AT_PLATFORM)\t{\n+\t\t\tif (strcmp((const char *)auxv.a_un.a_val, \"aarch64\")\n+\t\t\t\t\t== 0)\n+\t\t\t\tout[AARCH_MODE] = (1 << 3);\n+\t\t\telse if (strcmp((const char *)auxv.a_un.a_val,\n+\t\t\t\t\t\t\"aarch32\") == 0)\n+\t\t\t\tout[AARCH_MODE] = (1 << 4);\n+\t\t}\n+\t}\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+static inline int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\tcpuid_registers_t regs = {0};\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\t/* Flag does not match anything in the feature tables */\n+\t\treturn -ENOENT;\n+\n+\tfeat = &cpu_feature_table[feature];\n+\n+\tif (!feat->leaf)\n+\t\t/* This entry in the table wasn't filled out! */\n+\t\treturn -EFAULT;\n+\n+\t/* get the cpuid leaf containing the desired feature */\n+\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n+\n+\t/* check if the feature is enabled */\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles.h b/lib/librte_eal/common/include/arch/arm/rte_cycles.h\nnew file mode 100644\nindex 0000000..140d1bb\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles.h\n@@ -0,0 +1,77 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014. All rights reserved.\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_CYCLES_ARM32_H_\n+#define _RTE_CYCLES_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\tunsigned tsc;\n+\tuint64_t final_tsc;\n+\n+\t/* Read PMCCNTR */\n+\tasm volatile(\"mrc p15, 0, %0, c9, c13, 0\" : \"=r\"(tsc));\n+\t/* 1 tick = 64 clocks */\n+\tfinal_tsc = ((uint64_t)tsc) << 6;\n+\n+\treturn (uint64_t)final_tsc;\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\tasm volatile(\"isb sy\" : : : );\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CYCLES_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_memcpy.h b/lib/librte_eal/common/include/arch/arm/rte_memcpy.h\nnew file mode 100644\nindex 0000000..341052e\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_memcpy.h\n@@ -0,0 +1,101 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014. All rights reserved.\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_MEMCPY_ARM32_H_\n+#define _RTE_MEMCPY_ARM32_H_\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_memcpy.h\"\n+\n+\n+\n+static inline void\n+rte_mov16(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 16);\n+}\n+\n+static inline void\n+rte_mov32(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 32);\n+}\n+\n+static inline void\n+rte_mov48(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 48);\n+}\n+\n+static inline void\n+rte_mov64(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 64);\n+}\n+\n+static inline void\n+rte_mov128(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 128);\n+}\n+\n+static inline void\n+rte_mov256(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 256);\n+}\n+\n+static inline void *\n+rte_memcpy(void *dst, const void *src, size_t n)\n+{\n+\treturn memcpy(dst, src, n);\n+}\n+\n+\n+static inline void *\n+rte_memcpy_func(void *dst, const void *src, size_t n)\n+{\n+\treturn memcpy(dst, src, n);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MEMCPY_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_prefetch.h b/lib/librte_eal/common/include/arch/arm/rte_prefetch.h\nnew file mode 100644\nindex 0000000..47be3b8\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_prefetch.h\n@@ -0,0 +1,64 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_PREFETCH_ARM32_H_\n+#define _RTE_PREFETCH_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_prefetch.h\"\n+\n+static inline void\n+rte_prefetch0(const volatile void __attribute__((unused)) *p)\n+{\n+\tasm volatile(\"nop\");\n+}\n+\n+static inline void\n+rte_prefetch1(const volatile void __attribute__((unused)) *p)\n+{\n+\tasm volatile(\"nop\");\n+}\n+\n+static inline void\n+rte_prefetch2(const volatile void __attribute__((unused)) *p)\n+{\n+\tasm volatile(\"nop\");\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_PREFETCH_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_rwlock.h b/lib/librte_eal/common/include/arch/arm/rte_rwlock.h\nnew file mode 100644\nindex 0000000..87349b9\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_rwlock.h\n@@ -0,0 +1,70 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_RWLOCK_ARM32_H_\n+#define _RTE_RWLOCK_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_rwlock.h\"\n+\n+static inline void\n+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_unlock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_unlock(rwl);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_RWLOCK_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h\nnew file mode 100644\nindex 0000000..45d01a0\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h\n@@ -0,0 +1,116 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) IBM Corporation 2014. All rights reserved.\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of IBM Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_SPINLOCK_ARM32_H_\n+#define _RTE_SPINLOCK_ARM32_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+\n+#include \"generic/rte_spinlock.h\"\n+\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+\n+static inline void\n+rte_spinlock_lock(rte_spinlock_t *sl)\n+{\n+\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n+\t\twhile (sl->locked)\n+\t\t\trte_pause();\n+}\n+\n+static inline void\n+rte_spinlock_unlock(rte_spinlock_t *sl)\n+{\n+\t__sync_lock_release(&sl->locked);\n+}\n+\n+static inline int\n+rte_spinlock_trylock(rte_spinlock_t *sl)\n+{\n+\treturn (__sync_lock_test_and_set(&sl->locked, 1) == 0);\n+}\n+\n+#endif\n+\n+static inline int\n+rte_tm_supported(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline void\n+rte_spinlock_lock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_lock(sl); /* fall-back */\n+}\n+\n+static inline int\n+rte_spinlock_trylock_tm(rte_spinlock_t *sl)\n+{\n+\treturn rte_spinlock_trylock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_unlock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_unlock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_lock(slr); /* fall-back */\n+}\n+\n+static inline void\n+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_unlock(slr);\n+}\n+\n+static inline int\n+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\treturn rte_spinlock_recursive_trylock(slr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_SPINLOCK_ARM32_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h\nnew file mode 100644\nindex 0000000..5994efd\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h\n@@ -0,0 +1,37 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_VECT_ARM32_H_\n+#define _RTE_VECT_ARM32_H_\n+\n+\n+#endif /* _RTE_VECT_ARM32_H_*/\ndiff --git a/lib/librte_eal/linuxapp/Makefile b/lib/librte_eal/linuxapp/Makefile\nindex d9c5233..549f2ed 100644\n--- a/lib/librte_eal/linuxapp/Makefile\n+++ b/lib/librte_eal/linuxapp/Makefile\n@@ -35,6 +35,9 @@ ifeq ($(CONFIG_RTE_EAL_IGB_UIO),y)\n DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += igb_uio\n endif\n DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal\n+ifeq ($(CONFIG_RTE_ARCH), \"arm\")\n+DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += arm_pmu\n+endif\n ifeq ($(CONFIG_RTE_KNI_KMOD),y)\n DIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += kni\n endif\ndiff --git a/lib/librte_eal/linuxapp/arm_pmu/Makefile b/lib/librte_eal/linuxapp/arm_pmu/Makefile\nnew file mode 100755\nindex 0000000..0adb23b\n--- /dev/null\n+++ b/lib/librte_eal/linuxapp/arm_pmu/Makefile\n@@ -0,0 +1,52 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2015 Intel Corporation. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# module name and path\n+#\n+MODULE = arm_pmu\n+MODULE_PATH = drivers/net/arm_pmu\n+\n+#\n+# CFLAGS\n+#\n+MODULE_CFLAGS += -I$(SRCDIR) --param max-inline-insns-single=100\n+MODULE_CFLAGS += -I$(RTE_OUTPUT)/include\n+MODULE_CFLAGS += -Winline -Wall -Werror\n+MODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+SRCS-y := rte_enable_pmu.c\n+\n+include $(RTE_SDK)/mk/rte.module.mk\ndiff --git a/lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c b/lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c\nnew file mode 100644\nindex 0000000..9d77271\n--- /dev/null\n+++ b/lib/librte_eal/linuxapp/arm_pmu/rte_enable_pmu.c\n@@ -0,0 +1,83 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+ /**\n+ * @file\n+ * This file enables the ARM PMU.\n+ *\n+ * It contains the code to enable the usage of PMU registers\n+ * by application code on all cores.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/module.h>\n+#include <linux/pci.h>\n+#include <linux/uio_driver.h>\n+#include <linux/io.h>\n+#include <linux/msi.h>\n+#include <linux/version.h>\n+#include <linux/slab.h>\n+\n+void enable_pmu(void __attribute__((unused)) *info)\n+{\n+\tint core_id = 0;\n+\n+\tcore_id = smp_processor_id();\n+\t/* Configure PMUSERENR - Enables user mode to have access to the\n+\t * Performance Monitor Registers. */\n+\tasm volatile(\"mcr p15, 0, %0, c9, c14, 0\" : : \"r\"(1));\n+\t/* Configure PMCR */\n+\tasm volatile(\"mcr p15, 0, %0, c9, c12, 0\" : : \"r\"(29));\n+\t/* Configure PMCNTENSET Enable counters */\n+\tasm volatile(\"mcr p15, 0, %0, c9, c12, 1\" : : \"r\"(0x8000000f));\n+\treturn;\n+}\n+\n+int __init init_module_set_arm_pmu(void)\n+{\n+\tint ret = 0;\n+\t/* smp_call_function will make sure that the registers\n+\t * for all the cores are enabled for tracking their PMUs\n+\t * This is required for the rdtsc equivalent on ARMv7 */\n+\tret = smp_call_function(&enable_pmu, NULL, 0);\n+\t/* smp_call_function would only call on all other modules\n+\t * so call it for the current module */\n+\tenable_pmu(NULL);\n+\treturn ret;\n+}\n+\n+void __exit cleanup_module_set_arm_pmu(void)\n+{\n+}\n+\n+module_init(init_module_set_arm_pmu);\n+module_exit(cleanup_module_set_arm_pmu);\ndiff --git a/mk/arch/arm/rte.vars.mk b/mk/arch/arm/rte.vars.mk\nnew file mode 100644\nindex 0000000..3dfeb16\n--- /dev/null\n+++ b/mk/arch/arm/rte.vars.mk\n@@ -0,0 +1,58 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2015 Intel Corporation. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+#\n+# arch:\n+#\n+# - define ARCH variable (overriden by cmdline or by previous\n+# optional define in machine .mk)\n+# - define CROSS variable (overriden by cmdline or previous define\n+# in machine .mk)\n+# - define CPU_CFLAGS variable (overriden by cmdline or previous\n+# define in machine .mk)\n+# - define CPU_LDFLAGS variable (overriden by cmdline or previous\n+# define in machine .mk)\n+# - define CPU_ASFLAGS variable (overriden by cmdline or previous\n+# define in machine .mk)\n+# - may override any previously defined variable\n+#\n+# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32\n+#\n+\n+ARCH ?= arm\n+# common arch dir in eal headers\n+ARCH_DIR := arm\n+CROSS ?=\n+\n+CPU_CFLAGS += -flax-vector-conversions\n+CPU_LDFLAGS ?=\n+CPU_ASFLAGS ?=\n+\n+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\ndiff --git a/mk/machine/armv7-a/rte.vars.mk b/mk/machine/armv7-a/rte.vars.mk\nnew file mode 100644\nindex 0000000..feeebfa\n--- /dev/null\n+++ b/mk/machine/armv7-a/rte.vars.mk\n@@ -0,0 +1,63 @@\n+# BSD LICENSE\n+#\n+# Copyright(c) 2015 Intel Corporation. All rights reserved.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of Intel Corporation nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+#\n+# machine:\n+#\n+# - can define ARCH variable (overriden by cmdline value)\n+# - can define CROSS variable (overriden by cmdline value)\n+# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n+# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n+# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n+# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n+# overrides the one defined in arch.\n+# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n+# overrides the one defined in arch.\n+# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n+# overrides the one defined in arch.\n+# - may override any previously defined variable\n+#\n+\n+# ARCH =\n+# CROSS =\n+# MACHINE_CFLAGS =\n+# MACHINE_LDFLAGS =\n+# MACHINE_ASFLAGS =\n+# CPU_CFLAGS =\n+# CPU_LDFLAGS =\n+# CPU_ASFLAGS =\n+\n+MACHINE_CFLAGS += -march=armv7-a\n+\n+#Tried this for gdb - did not work - Dwarf version error seen\n+# we need a gdb that can understand dwarf version 4\n+#CPU_CFLAGS += -g -gdwarf-2 -gstrict-dwarf\n+#CPU_CFLAGS := $(filter-out -O3,$(CPU_CFLAGS))\n+#CPU_CFLAGS := $(filter-out -O2,$(CPU_CFLAGS))\ndiff --git a/mk/toolchain/gcc/rte.vars.mk b/mk/toolchain/gcc/rte.vars.mk\nindex 0f51c66..501fce5 100644\n--- a/mk/toolchain/gcc/rte.vars.mk\n+++ b/mk/toolchain/gcc/rte.vars.mk\n@@ -1,7 +1,6 @@\n # BSD LICENSE\n #\n-# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n-# All rights reserved.\n+# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n #\n # Redistribution and use in source and binary forms, with or without\n # modification, are permitted provided that the following conditions\n@@ -73,7 +72,10 @@ endif\n \n WERROR_FLAGS := -W -Wall -Werror -Wstrict-prototypes -Wmissing-prototypes\n WERROR_FLAGS += -Wmissing-declarations -Wold-style-definition -Wpointer-arith\n-WERROR_FLAGS += -Wcast-align -Wnested-externs -Wcast-qual\n+ifneq ($(CONFIG_RTE_ARCH), \"arm\")\n+WERROR_FLAGS += -Wcast-align\n+endif\n+WERROR_FLAGS += -Wnested-externs -Wcast-qual\n WERROR_FLAGS += -Wformat-nonliteral -Wformat-security\n WERROR_FLAGS += -Wundef -Wwrite-strings\n \n", "prefixes": [ "dpdk-dev" ] }