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GET /api/patches/7374/?format=api
{ "id": 7374, "url": "https://patches.dpdk.org/api/patches/7374/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443799208-9408-3-git-send-email-danielx.t.mrzyglod@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443799208-9408-3-git-send-email-danielx.t.mrzyglod@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443799208-9408-3-git-send-email-danielx.t.mrzyglod@intel.com", "date": "2015-10-02T15:20:07", "name": "[dpdk-dev,2/3] ixgbe: add additional ieee1588 support functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e54108d199b29dc7e6a0c8c0dd322390d8c25d4c", "submitter": { "id": 23, "url": "https://patches.dpdk.org/api/people/23/?format=api", "name": "Daniel Mrzyglod", "email": "danielx.t.mrzyglod@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443799208-9408-3-git-send-email-danielx.t.mrzyglod@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7374/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7374/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 0B86A8E5A;\n\tFri, 2 Oct 2015 17:23:40 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 884628DB1\n\tfor <dev@dpdk.org>; Fri, 2 Oct 2015 17:23:38 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby fmsmga102.fm.intel.com with ESMTP; 02 Oct 2015 08:23:38 -0700", "from unknown ([10.217.248.93])\n\tby orsmga002.jf.intel.com with SMTP; 02 Oct 2015 08:23:35 -0700", "by (sSMTP sendmail emulation); Fri, 02 Oct 2015 17:22:32 +0200" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,623,1437462000\"; d=\"scan'208\";a=\"818014954\"", "From": "Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 2 Oct 2015 17:20:07 +0200", "Message-Id": "<1443799208-9408-3-git-send-email-danielx.t.mrzyglod@intel.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1443799208-9408-1-git-send-email-danielx.t.mrzyglod@intel.com>", "References": "<1443799208-9408-1-git-send-email-danielx.t.mrzyglod@intel.com>", "Subject": "[dpdk-dev] [PATCH 2/3] ixgbe: add additional ieee1588 support\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add additional functions to support the existing IEEE1588\nfunctionality and to enable getting, setting and adjusting\nthe device time.\n\nSigned-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 250 +++++++++++++++++++++++++++++++++++++--\n drivers/net/ixgbe/ixgbe_ethdev.h | 24 ++++\n 2 files changed, 263 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex ec2918c..d0c575f 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -126,10 +126,12 @@\n #define IXGBE_HKEY_MAX_INDEX 10\n \n /* Additional timesync values. */\n-#define IXGBE_TIMINCA_16NS_SHIFT 24\n-#define IXGBE_TIMINCA_INCVALUE 16000000\n-#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \\\n-\t\t\t\t | IXGBE_TIMINCA_INCVALUE)\n+#define NSEC_PER_SEC 1000000000L\n+#define IXGBE_INCVAL_10GB 0x66666666\n+#define IXGBE_INCVAL_SHIFT_10GB 28\n+#define IXGBE_INCVAL_SHIFT_82599 7\n+#define IXGBE_INCPER_SHIFT_82599 24\n+#define IXGBE_CYCLECOUTER_MASK 0xffffffffffffffff\n \n static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);\n static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);\n@@ -325,6 +327,11 @@ static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t flags);\n static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t struct timespec *timestamp);\n+static int ixgbe_timesync_adjust(struct rte_eth_dev *dev, int64_t delta);\n+static int ixgbe_timesync_gettime(struct rte_eth_dev *dev,\n+\t\tstruct timespec *timestamp);\n+static int ixgbe_timesync_settime(struct rte_eth_dev *dev,\n+\t\tstruct timespec *timestamp);\n \n /*\n * Define VF Stats MACRO for Non \"cleared on read\" register\n@@ -465,6 +472,9 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {\n \t.get_eeprom_length = ixgbe_get_eeprom_length,\n \t.get_eeprom = ixgbe_get_eeprom,\n \t.set_eeprom = ixgbe_set_eeprom,\n+\t.timesync_adjust = ixgbe_timesync_adjust,\n+\t.timesync_gettime = ixgbe_timesync_gettime,\n+\t.timesync_settime = ixgbe_timesync_settime,\n };\n \n /*\n@@ -5241,20 +5251,223 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n \t\t\t\t\t ixgbe_dev_addr_list_itr, TRUE);\n }\n \n+static inline uint64_t\n+timespec_to_ns(const struct timespec *ts)\n+{\n+\treturn ((uint64_t) ts->tv_sec * NSEC_PER_SEC) + ts->tv_nsec;\n+}\n+\n+static struct timespec\n+ns_to_timespec(int64_t nsec)\n+{\n+\t struct timespec ts = {0, 0};\n+\t int32_t rem;\n+\n+\t if (nsec == 0)\n+\t\t\t return ts;\n+\t rem = nsec % NSEC_PER_SEC;\n+\t ts.tv_sec = nsec / NSEC_PER_SEC;\n+\n+\t if (unlikely(rem < 0)) {\n+\t\t\t ts.tv_sec--;\n+\t\t\t rem += NSEC_PER_SEC;\n+\t }\n+\n+\t ts.tv_nsec = rem;\n+\n+\t return ts;\n+}\n+\n+static inline uint64_t\n+cyclecounter_cycles_to_ns(const struct cyclecounter *cc,\n+\t\t\t\t uint64_t cycles, uint64_t mask, uint64_t *frac)\n+{\n+\tuint64_t ns = cycles;\n+\n+\tns = (ns * cc->mult) + *frac;\n+\t*frac = ns & mask;\n+\treturn ns >> cc->shift;\n+}\n+\n+static uint64_t\n+cyclecounter_cycles_to_ns_backwards(const struct cyclecounter *cc,\n+\t\t\t uint64_t cycles, uint64_t mask __rte_unused, uint64_t frac)\n+{\n+\tuint64_t ns = (uint64_t) cycles;\n+\n+\tns = ((ns * cc->mult) - frac) >> cc->shift;\n+\n+\treturn ns;\n+}\n+\n+static uint64_t\n+timecounter_cycles_to_ns_time(struct timecounter *tc, uint64_t cycle_tstamp)\n+{\n+\tuint64_t delta = (cycle_tstamp - tc->cycle_last) & tc->cc->mask;\n+\tuint64_t nsec = tc->nsec, frac = tc->frac;\n+\n+\n+\t/* Cycle counts that are corectly converted as they\n+\t * are between -1/2 max cycle count and +1/2max cycle count\n+\t * */\n+\tif (delta > tc->cc->mask / 2) {\n+\t\tdelta = (tc->cycle_last - cycle_tstamp) & tc->cc->mask;\n+\t\tnsec -= cyclecounter_cycles_to_ns_backwards(tc->cc, delta, tc->mask, frac);\n+\t} else {\n+\t\tnsec += cyclecounter_cycles_to_ns(tc->cc, delta, tc->mask, &frac);\n+\t}\n+\n+\treturn nsec;\n+}\n+\n+static uint64_t\n+ixgbe_read_timesync_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t systim_cycles = 0;\n+\n+\tsystim_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);\n+\tsystim_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;\n+\n+\treturn systim_cycles;\n+}\n+\n+static uint64_t\n+timecounter_read_ns_delta(struct rte_eth_dev *dev)\n+{\n+\tuint64_t cycle_now, cycle_delta;\n+\tuint64_t ns_offset;\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\t/* read cycle counter: */\n+\tcycle_now = adapter->tc.cc->read(dev);\n+\n+\t/* calculate the delta since the last timecounter_read_delta(): */\n+\tcycle_delta = (cycle_now - adapter->tc.cycle_last) & adapter->tc.cc->mask;\n+\n+\t/* convert to nanoseconds: */\n+\tns_offset = cyclecounter_cycles_to_ns(adapter->tc.cc, cycle_delta,\n+\t\t\t\t\tadapter->tc.mask, &adapter->tc.frac);\n+\n+\t/* update time stamp of timecounter_read_delta() call: */\n+\tadapter->tc.cycle_last = cycle_now;\n+\n+\treturn ns_offset;\n+}\n+\n+static uint64_t\n+timecounter_read(struct rte_eth_dev *dev)\n+{\n+\tuint64_t nsec;\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\t/* increment time by nanoseconds since last call */\n+\tnsec = timecounter_read_ns_delta(dev);\n+\tnsec += adapter->tc.nsec;\n+\tadapter->tc.nsec = nsec;\n+\n+\treturn nsec;\n+}\n+\n+\n+static void\n+timecounter_init(struct rte_eth_dev *dev,\n+\t\t uint64_t start_time)\n+{\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\tadapter->tc.cc = &adapter->cc;\n+\tadapter->tc.cycle_last = adapter->tc.cc->read(dev);\n+\tadapter->tc.nsec = start_time;\n+\tadapter->tc.mask = (1ULL << adapter->tc.cc->shift) - 1;\n+\tadapter->tc.frac = 0;\n+}\n+\n+static void\n+ixgbe_start_cyclecounter(struct rte_eth_dev *dev)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\tuint32_t incval = 0;\n+\tuint32_t shift = 0;\n+\n+\tincval = IXGBE_INCVAL_10GB >> IXGBE_INCVAL_SHIFT_82599;\n+\tshift = IXGBE_INCVAL_SHIFT_10GB - IXGBE_INCVAL_SHIFT_82599;\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA,\n+\t\t\t(1 << IXGBE_INCPER_SHIFT_82599) |\n+\t\t\tincval);\n+\n+\tmemset(&adapter->cc, 0, sizeof(struct cyclecounter));\n+\tadapter->cc.read = ixgbe_read_timesync_cyclecounter;\n+\tadapter->cc.mask = IXGBE_CYCLECOUTER_MASK;\n+\tadapter->cc.shift = shift;\n+\tadapter->cc.mult = 1;\n+}\n+\n+static int\n+ixgbe_timesync_adjust(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n+\tadapter->tc.nsec += delta;\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ixgbe_timesync_settime(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t ns;\n+\tns = timespec_to_ns(ts);\n+\n+\t/* reset the timecounter */\n+\ttimecounter_init(dev, ns);\n+\t/* it's setup after every change */\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ixgbe_timesync_gettime(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tuint64_t ns;\n+\n+\tns = timecounter_read(dev);\n+\t*ts = ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n static int\n ixgbe_timesync_enable(struct rte_eth_dev *dev)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t tsync_ctl;\n \tuint32_t tsauxc;\n+\tuint64_t ns;\n+\tstruct timespec zerotime = {0, 0};\n \n \t/* Enable system time for platforms where it isn't on by default. */\n \ttsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);\n \ttsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;\n-\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n \n-\t/* Start incrementing the register used to timestamp PTP packets. */\n-\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);\n+\t/* Set 0.0 epoch time to initialize timecounter*/\n+\tns = timespec_to_ns(&zerotime);\n+\tixgbe_start_cyclecounter(dev);\n+\ttimecounter_init(dev, ns);\n+\n+\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n \n \t/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n \tIXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),\n@@ -5272,6 +5485,9 @@ ixgbe_timesync_enable(struct rte_eth_dev *dev)\n \ttsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;\n \tIXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);\n \n+\t/* After writing to registers should be flush */\n+\tIXGBE_WRITE_FLUSH(hw);\n+\n \treturn 0;\n }\n \n@@ -5306,9 +5522,13 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t uint32_t flags __rte_unused)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n \tuint32_t tsync_rxctl;\n \tuint32_t rx_stmpl;\n \tuint32_t rx_stmph;\n+\tuint64_t regival = 0;\n \n \ttsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);\n \tif ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)\n@@ -5316,9 +5536,11 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \n \trx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);\n \trx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);\n+\ttimecounter_read(dev);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tregival = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n+\tregival = timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = ns_to_timespec(regival);\n \n \treturn 0;\n }\n@@ -5328,9 +5550,13 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp)\n {\n \tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ixgbe_adapter *adapter =\n+\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n+\n \tuint32_t tsync_txctl;\n \tuint32_t tx_stmpl;\n \tuint32_t tx_stmph;\n+\tuint64_t regival = 0;\n \n \ttsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);\n \tif ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)\n@@ -5338,9 +5564,11 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \n \ttx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);\n \ttx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);\n+\ttimecounter_read(dev);\n \n-\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n-\ttimestamp->tv_nsec = 0;\n+\tregival = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n+\tregival = timecounter_cycles_to_ns_time(&adapter->tc, regival);\n+\t*timestamp = ns_to_timespec(regival);\n \n \treturn 0;\n }\ndiff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h\nindex c3d4f4f..6708e08 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.h\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.h\n@@ -252,6 +252,27 @@ struct ixgbe_filter_info {\n };\n \n /*\n+ * Structure for cyclecounter IEEE1588 functionality\n+ */\n+struct cyclecounter {\n+\tuint64_t (*read)(struct rte_eth_dev *dev);\n+\tuint64_t mask;\n+\tuint32_t mult;\n+\tuint32_t shift;\n+};\n+\n+/*\n+ * Structure for structure that keep UnixEpoch time\n+ */\n+struct timecounter {\n+\tstruct cyclecounter *cc;\n+\tuint64_t cycle_last;\n+\tuint64_t nsec;\n+\tuint64_t mask;\n+\tuint64_t frac;\n+};\n+\n+/*\n * Structure to store private data for each driver instance (for each port).\n */\n struct ixgbe_adapter {\n@@ -273,6 +294,9 @@ struct ixgbe_adapter {\n \n \tbool rx_bulk_alloc_allowed;\n \tbool rx_vec_allowed;\n+\n+\tstruct cyclecounter cc;\n+\tstruct timecounter tc;\n };\n \n #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\\\n", "prefixes": [ "dpdk-dev", "2/3" ] }