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GET /api/patches/73061/?format=api
{ "id": 73061, "url": "https://patches.dpdk.org/api/patches/73061/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200703210210.40568-10-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200703210210.40568-10-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200703210210.40568-10-ajit.khaparde@broadcom.com", "date": "2020-07-03T21:01:28", "name": "[v5,09/51] net/bnxt: add support for exact match", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e27d69291ced11133fe30f3186b1675a6c1c439f", "submitter": { "id": 501, "url": "https://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 1766, "url": "https://patches.dpdk.org/api/users/1766/?format=api", "username": "ajitkhaparde", "first_name": "Ajit", "last_name": "Khaparde", "email": "ajit.khaparde@broadcom.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200703210210.40568-10-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 10785, "url": "https://patches.dpdk.org/api/series/10785/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10785", "date": "2020-07-03T21:01:19", "name": "net/bnxt: add features for host-based flow management", "version": 5, "mbox": "https://patches.dpdk.org/series/10785/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/73061/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/73061/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1390BA0524;\n\tFri, 3 Jul 2020 23:07:01 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5DA621DCDF;\n\tFri, 3 Jul 2020 23:05:22 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n [192.19.229.170]) by dpdk.org (Postfix) with ESMTP id 6670A1DBCF\n for <dev@dpdk.org>; Fri, 3 Jul 2020 23:04:59 +0200 (CEST)", "from mail-irv-17.broadcom.com (mail-irv-17.lvn.broadcom.net\n [10.75.242.48])\n by rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 599A830C028;\n Fri, 3 Jul 2020 14:04:58 -0700 (PDT)", "from localhost.localdomain (unknown [10.230.185.215])\n by mail-irv-17.broadcom.com (Postfix) with ESMTP id 4269814008B;\n Fri, 3 Jul 2020 14:04:57 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 599A830C028", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n s=dkimrelay; t=1593810298;\n bh=6nb4nhLsGJ6vM4xVS9aUHmhRVU1fybeQ8Vc/j36gBDE=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=hff/drzAhOwvxQc2qVWK1ZbEVW5zVnBiB0/OhUGFgIv+19oAaNP/HhdHffJsCG4af\n q7liAB8vp/BwfufX6wsDurN2RgNwaa9xGkmMTTPPQLCuudCsIKLN6oyXvglAW6zEs9\n taogPY1zZ3wJ10NNtAF+Rwtuc3QJFqGpk0iStf9M=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "Peter Spreadborough <peter.spreadborough@broadcom.com>,\n Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>", "Date": "Fri, 3 Jul 2020 14:01:28 -0700", "Message-Id": "<20200703210210.40568-10-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.21.1 (Apple Git-122.3)", "In-Reply-To": "<20200703210210.40568-1-ajit.khaparde@broadcom.com>", "References": "<1f5421dc-0453-6dc8-09c2-ddfff6eb4888@intel.com>\n <20200703210210.40568-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 09/51] net/bnxt: add support for exact match", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Peter Spreadborough <peter.spreadborough@broadcom.com>\n\n- Add Exact Match support\n- Create EM table pool of memory indices\n- Insert exact match internal entry API\n- Sends EM internal insert and delete request to firmware\n\nSigned-off-by: Peter Spreadborough <peter.spreadborough@broadcom.com>\nSigned-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 3091 ++++++++++++++---\n drivers/net/bnxt/tf_core/hwrm_tf.h | 9 +\n drivers/net/bnxt/tf_core/lookup3.h | 1 -\n drivers/net/bnxt/tf_core/stack.c | 8 +\n drivers/net/bnxt/tf_core/stack.h | 10 +\n drivers/net/bnxt/tf_core/tf_core.c | 144 +-\n drivers/net/bnxt/tf_core/tf_core.h | 383 +-\n drivers/net/bnxt/tf_core/tf_em.c | 98 +-\n drivers/net/bnxt/tf_core/tf_em.h | 31 +\n drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 12 +\n drivers/net/bnxt/tf_core/tf_msg.c | 86 +-\n drivers/net/bnxt/tf_core/tf_msg.h | 13 +\n drivers/net/bnxt/tf_core/tf_session.h | 18 +\n drivers/net/bnxt/tf_core/tf_tbl.c | 99 +-\n drivers/net/bnxt/tf_core/tf_tbl.h | 57 +-\n drivers/net/bnxt/tf_core/tfp.h | 123 +-\n 16 files changed, 3493 insertions(+), 690 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex 7e30c9ffc..30516eb75 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -611,6 +611,10 @@ struct cmd_nums {\n \t#define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)\n \t/* Queries pf ids belong to specified host(s) */\n \t#define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)\n+\t/* Queries extended stats per function */\n+\t#define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)\n+\t/* Queries exteded statitics context */\n+\t#define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST UINT32_C(0x200)\n \t/* Experimental */\n@@ -647,41 +651,49 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_SESSION_ATTACH UINT32_C(0x2c7)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_CLOSE UINT32_C(0x2c8)\n+\t#define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_QCFG UINT32_C(0x2c9)\n+\t#define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2ca)\n+\t#define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cb)\n+\t#define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2cc)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)\n \t/* Experimental */\n-\t#define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cd)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)\n \t/* Experimental */\n-\t#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2d0)\n+\t#define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)\n \t/* Experimental */\n-\t#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2d1)\n+\t#define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)\n \t/* Experimental */\n-\t#define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2da)\n+\t#define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)\n \t/* Experimental */\n-\t#define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2db)\n+\t#define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)\n \t/* Experimental */\n-\t#define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2dc)\n+\t#define HWRM_TF_CTXT_MEM_RGTR UINT32_C(0x2e4)\n \t/* Experimental */\n-\t#define HWRM_TF_EXT_EM_OP UINT32_C(0x2dd)\n+\t#define HWRM_TF_CTXT_MEM_UNRGTR UINT32_C(0x2e5)\n \t/* Experimental */\n-\t#define HWRM_TF_EXT_EM_CFG UINT32_C(0x2de)\n+\t#define HWRM_TF_EXT_EM_QCAPS UINT32_C(0x2e6)\n \t/* Experimental */\n-\t#define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2df)\n+\t#define HWRM_TF_EXT_EM_OP UINT32_C(0x2e7)\n \t/* Experimental */\n-\t#define HWRM_TF_TCAM_SET UINT32_C(0x2ee)\n+\t#define HWRM_TF_EXT_EM_CFG UINT32_C(0x2e8)\n \t/* Experimental */\n-\t#define HWRM_TF_TCAM_GET UINT32_C(0x2ef)\n+\t#define HWRM_TF_EXT_EM_QCFG UINT32_C(0x2e9)\n \t/* Experimental */\n-\t#define HWRM_TF_TCAM_MOVE UINT32_C(0x2f0)\n+\t#define HWRM_TF_EM_INSERT UINT32_C(0x2ea)\n \t/* Experimental */\n-\t#define HWRM_TF_TCAM_FREE UINT32_C(0x2f1)\n+\t#define HWRM_TF_EM_DELETE UINT32_C(0x2eb)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_SET UINT32_C(0x2f8)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_GET UINT32_C(0x2f9)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)\n \t/* Experimental */\n \t#define HWRM_SV UINT32_C(0x400)\n \t/* Experimental */\n@@ -715,6 +727,13 @@ struct cmd_nums {\n \t#define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)\n \t/* Send driver debug information to firmware */\n \t#define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)\n+\t/* Query debug capabilities of firmware */\n+\t#define HWRM_DBG_QCAPS UINT32_C(0xff20)\n+\t/* Retrieve debug settings of firmware */\n+\t#define HWRM_DBG_QCFG UINT32_C(0xff21)\n+\t/* Set destination parameters for crashdump medium */\n+\t#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)\n+\t#define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)\n \t/* Experimental */\n \t#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)\n \t#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)\n@@ -914,8 +933,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 30\n-#define HWRM_VERSION_STR \"1.10.1.30\"\n+#define HWRM_VERSION_RSVD 45\n+#define HWRM_VERSION_STR \"1.10.1.45\"\n \n /****************\n * hwrm_ver_get *\n@@ -2292,6 +2311,35 @@ struct cmpl_base {\n \t * Completion of TX packet. Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)\n+\t/*\n+\t * NO-OP completion:\n+\t * Completion of NO-OP. Length = 16B\n+\t */\n+\t#define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)\n+\t/*\n+\t * TX L2 coalesced completion:\n+\t * Completion of coalesced TX packet. Length = 16B\n+\t */\n+\t#define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)\n+\t/*\n+\t * TX L2 PTP completion:\n+\t * Completion of PTP TX packet. Length = 32B\n+\t */\n+\t#define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3)\n+\t/*\n+\t * RX L2 TPA Start V2 Completion:\n+\t * Completion of and L2 RX packet. Length = 32B\n+\t * This is the new version of the RX_TPA_START completion used\n+\t * in SR2 and later chips.\n+\t */\n+\t#define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)\n+\t/*\n+\t * RX L2 V2 completion:\n+\t * Completion of and L2 RX packet. Length = 32B\n+\t * This is the new version of the RX_L2 completion used in SR2\n+\t * and later chips.\n+\t */\n+\t#define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)\n \t/*\n \t * RX L2 completion:\n \t * Completion of and L2 RX packet. Length = 32B\n@@ -2321,6 +2369,24 @@ struct cmpl_base {\n \t * Length = 16B\n \t */\n \t#define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)\n+\t/*\n+\t * VEE Flush Completion:\n+\t * This completion is inserted manually by\n+\t * the Primate and processed by the VEE hardware to ensure that\n+\t * all completions on a VEE function have been processed by the\n+\t * VEE hardware before FLR process is completed.\n+\t */\n+\t#define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)\n+\t/*\n+\t * Mid Path Short Completion :\n+\t * Completion of a Mid Path Command. Length = 16B\n+\t */\n+\t#define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)\n+\t/*\n+\t * Mid Path Long Completion :\n+\t * Completion of a Mid Path Command. Length = 32B\n+\t */\n+\t#define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)\n \t/*\n \t * HWRM Command Completion:\n \t * Completion of an HWRM command.\n@@ -2398,7 +2464,9 @@ struct tx_cmpl {\n \tuint16_t\tunused_0;\n \t/*\n \t * This is a copy of the opaque field from the first TX BD of this\n-\t * transmitted packet.\n+\t * transmitted packet. Note that, if the packet was described by a short\n+\t * CSO or short CSO inline BD, then the 16-bit opaque field from the\n+\t * short CSO BD will appear in the bottom 16 bits of this field.\n \t */\n \tuint32_t\topaque;\n \tuint16_t\terrors_v;\n@@ -2407,58 +2475,352 @@ struct tx_cmpl {\n \t * for each pass through the completion queue. The even passes\n \t * will write 1. The odd passes will write 0.\n \t */\n-\t#define TX_CMPL_V UINT32_C(0x1)\n-\t#define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)\n-\t#define TX_CMPL_ERRORS_SFT 1\n+\t#define TX_CMPL_V UINT32_C(0x1)\n+\t#define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)\n+\t#define TX_CMPL_ERRORS_SFT 1\n \t/*\n \t * This error indicates that there was some sort of problem\n \t * with the BDs for the packet.\n \t */\n-\t#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)\n-\t#define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1\n \t/* No error */\n-\t#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 1)\n \t/*\n \t * Bad Format:\n \t * BDs were not formatted correctly.\n \t */\n-\t#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)\n+\t#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT \\\n+\t\t(UINT32_C(0x2) << 1)\n \t#define TX_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n \t\tTX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT\n \t/*\n \t * When this bit is '1', it indicates that the length of\n \t * the packet was zero. No packet was transmitted.\n \t */\n-\t#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)\n+\t#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)\n \t/*\n \t * When this bit is '1', it indicates that the packet\n \t * was longer than the programmed limit in TDI. No\n \t * packet was transmitted.\n \t */\n-\t#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)\n+\t#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)\n \t/*\n \t * When this bit is '1', it indicates that one or more of the\n \t * BDs associated with this packet generated a PCI error.\n \t * This probably means the address was not valid.\n \t */\n-\t#define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)\n+\t#define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)\n \t/*\n \t * When this bit is '1', it indicates that the packet was longer\n \t * than indicated by the hint. No packet was transmitted.\n \t */\n-\t#define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)\n+\t#define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)\n \t/*\n \t * When this bit is '1', it indicates that the packet was\n \t * dropped due to Poison TLP error on one or more of the\n \t * TLPs in the PXP completion.\n \t */\n-\t#define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)\n+\t#define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was dropped\n+\t * due to a transient internal error in TDC. The packet or LSO can\n+\t * be retried and may transmit successfully on a subsequent attempt.\n+\t */\n+\t#define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', it was not possible to collect a a timestamp\n+\t * for a PTP completion, in which case the timestamp_hi and\n+\t * timestamp_lo fields are invalid. When this bit is '0' for a PTP\n+\t * completion, the timestamp_hi and timestamp_lo fields are valid.\n+\t * RJRN will copy the value of this bit into the field of the same\n+\t * name in all TX completions, regardless of whether such completions\n+\t * are PTP completions or other TX completions.\n+\t */\n+\t#define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)\n \t/* unused2 is 16 b */\n \tuint16_t\tunused_1;\n \t/* unused3 is 32 b */\n \tuint32_t\tunused_2;\n } __rte_packed;\n \n+/* tx_cmpl_coal (size:128b/16B) */\n+struct tx_cmpl_coal {\n+\tuint16_t\tflags_type;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_CMPL_COAL_TYPE_SFT 0\n+\t/*\n+\t * TX L2 coalesced completion:\n+\t * Completion of TX packet. Length = 16B\n+\t */\n+\t#define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)\n+\t#define TX_CMPL_COAL_TYPE_LAST TX_CMPL_COAL_TYPE_TX_L2_COAL\n+\t#define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define TX_CMPL_COAL_FLAGS_SFT 6\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an\n+\t * error of some type. Type of error is indicated in\n+\t * error_flags.\n+\t */\n+\t#define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet completed\n+\t * was transmitted using the push acceleration data provided\n+\t * by the driver. When this bit is '0', it indicates that the\n+\t * packet had not push acceleration data written or was executed\n+\t * as a normal packet even though push data was provided.\n+\t */\n+\t#define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)\n+\t/* unused1 is 16 b */\n+\tuint16_t\tunused_0;\n+\t/*\n+\t * This is a copy of the opaque field from the first TX BD of the packet\n+\t * which corresponds with the reported sq_cons_idx. Note that, with\n+\t * coalesced completions, completions are generated for only some of the\n+\t * packets. The driver will see the opaque field for only those packets.\n+\t * Note that, if the packet was described by a short CSO or short CSO\n+\t * inline BD, then the 16-bit opaque field from the short CSO BD will\n+\t * appear in the bottom 16 bits of this field. For TX rings with\n+\t * completion coalescing enabled (which would use the coalesced\n+\t * completion record), it is suggested that the driver populate the\n+\t * opaque field to indicate the specific TX ring with which the\n+\t * completion is associated, then utilize the opaque and sq_cons_idx\n+\t * fields in the coalesced completion record to determine the specific\n+\t * packets that are to be completed on that ring.\n+\t */\n+\tuint32_t\topaque;\n+\tuint16_t\terrors_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define TX_CMPL_COAL_V UINT32_C(0x1)\n+\t#define TX_CMPL_COAL_ERRORS_MASK \\\n+\t\tUINT32_C(0xfffe)\n+\t#define TX_CMPL_COAL_ERRORS_SFT 1\n+\t/*\n+\t * This error indicates that there was some sort of problem\n+\t * with the BDs for the packet.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)\n+\t#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_SFT 1\n+\t/* No error */\n+\t#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tTX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT\n+\t/*\n+\t * When this bit is '1', it indicates that the length of\n+\t * the packet was zero. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet\n+\t * was longer than the programmed limit in TDI. No\n+\t * packet was transmitted.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', it indicates that one or more of the\n+\t * BDs associated with this packet generated a PCI error.\n+\t * This probably means the address was not valid.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was longer\n+\t * than indicated by the hint. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was\n+\t * dropped due to Poison TLP error on one or more of the\n+\t * TLPs in the PXP completion.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was dropped\n+\t * due to a transient internal error in TDC. The packet or LSO can\n+\t * be retried and may transmit successfully on a subsequent attempt.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', it was not possible to collect a a timestamp\n+\t * for a PTP completion, in which case the timestamp_hi and\n+\t * timestamp_lo fields are invalid. When this bit is '0' for a PTP\n+\t * completion, the timestamp_hi and timestamp_lo fields are valid.\n+\t * RJRN will copy the value of this bit into the field of the same\n+\t * name in all TX completions, regardless of whether such\n+\t * completions are PTP completions or other TX completions.\n+\t */\n+\t#define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR \\\n+\t\tUINT32_C(0x400)\n+\t/* unused2 is 16 b */\n+\tuint16_t\tunused_1;\n+\tuint32_t\tsq_cons_idx;\n+\t/*\n+\t * This value is SQ index for the start of the packet following the\n+\t * last completed packet.\n+\t */\n+\t#define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)\n+\t#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0\n+} __rte_packed;\n+\n+/* tx_cmpl_ptp (size:128b/16B) */\n+struct tx_cmpl_ptp {\n+\tuint16_t\tflags_type;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_CMPL_PTP_TYPE_SFT 0\n+\t/*\n+\t * TX L2 PTP completion:\n+\t * Completion of TX packet. Length = 32B\n+\t */\n+\t#define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2)\n+\t#define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP\n+\t#define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define TX_CMPL_PTP_FLAGS_SFT 6\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an\n+\t * error of some type. Type of error is indicated in\n+\t * error_flags.\n+\t */\n+\t#define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet completed\n+\t * was transmitted using the push acceleration data provided\n+\t * by the driver. When this bit is '0', it indicates that the\n+\t * packet had not push acceleration data written or was executed\n+\t * as a normal packet even though push data was provided.\n+\t */\n+\t#define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80)\n+\t/* unused1 is 16 b */\n+\tuint16_t\tunused_0;\n+\t/*\n+\t * This is a copy of the opaque field from the first TX BD of this\n+\t * transmitted packet. Note that, if the packet was described by a short\n+\t * CSO or short CSO inline BD, then the 16-bit opaque field from the\n+\t * short CSO BD will appear in the bottom 16 bits of this field.\n+\t */\n+\tuint32_t\topaque;\n+\tuint16_t\terrors_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define TX_CMPL_PTP_V UINT32_C(0x1)\n+\t#define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe)\n+\t#define TX_CMPL_PTP_ERRORS_SFT 1\n+\t/*\n+\t * This error indicates that there was some sort of problem\n+\t * with the BDs for the packet.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)\n+\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1\n+\t/* No error */\n+\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t#define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tTX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT\n+\t/*\n+\t * When this bit is '1', it indicates that the length of\n+\t * the packet was zero. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet\n+\t * was longer than the programmed limit in TDI. No\n+\t * packet was transmitted.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', it indicates that one or more of the\n+\t * BDs associated with this packet generated a PCI error.\n+\t * This probably means the address was not valid.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was longer\n+\t * than indicated by the hint. No packet was transmitted.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was\n+\t * dropped due to Poison TLP error on one or more of the\n+\t * TLPs in the PXP completion.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)\n+\t/*\n+\t * When this bit is '1', it indicates that the packet was dropped due\n+\t * to a transient internal error in TDC. The packet or LSO can be\n+\t * retried and may transmit successfully on a subsequent attempt.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)\n+\t/*\n+\t * When this bit is '1', it was not possible to collect a a timestamp\n+\t * for a PTP completion, in which case the timestamp_hi and\n+\t * timestamp_lo fields are invalid. When this bit is '0' for a PTP\n+\t * completion, the timestamp_hi and timestamp_lo fields are valid.\n+\t * RJRN will copy the value of this bit into the field of the same\n+\t * name in all TX completions, regardless of whether such\n+\t * completions are PTP completions or other TX completions.\n+\t */\n+\t#define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)\n+\t/* unused2 is 16 b */\n+\tuint16_t\tunused_1;\n+\t/*\n+\t * This is timestamp value (lower 32bits) read from PM for the PTP\n+\t * timestamp enabled packet.\n+\t */\n+\tuint32_t\ttimestamp_lo;\n+} __rte_packed;\n+\n+/* tx_cmpl_ptp_hi (size:128b/16B) */\n+struct tx_cmpl_ptp_hi {\n+\t/*\n+\t * This is timestamp value (lower 32bits) read from PM for the PTP\n+\t * timestamp enabled packet.\n+\t */\n+\tuint16_t\ttimestamp_hi[3];\n+\tuint16_t\treserved16;\n+\tuint64_t\tv2;\n+\t/*\n+\t * This value is written by the NIC such that it will be different for\n+\t * each pass through the completion queue.The even passes will write 1.\n+\t * The odd passes will write 0\n+\t */\n+\t#define TX_CMPL_PTP_HI_V2 UINT32_C(0x1)\n+} __rte_packed;\n+\n /* rx_pkt_cmpl (size:128b/16B) */\n struct rx_pkt_cmpl {\n \tuint16_t\tflags_type;\n@@ -3003,12 +3365,8 @@ struct rx_pkt_cmpl_hi {\n \t#define RX_PKT_CMPL_REORDER_SFT 0\n } __rte_packed;\n \n-/*\n- * This TPA completion structure is used on devices where the\n- * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.\n- */\n-/* rx_tpa_start_cmpl (size:128b/16B) */\n-struct rx_tpa_start_cmpl {\n+/* rx_pkt_v2_cmpl (size:128b/16B) */\n+struct rx_pkt_v2_cmpl {\n \tuint16_t\tflags_type;\n \t/*\n \t * This field indicates the exact type of the completion.\n@@ -3017,84 +3375,143 @@ struct rx_tpa_start_cmpl {\n \t * records. Odd values indicate 32B\n \t * records.\n \t */\n-\t#define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)\n-\t#define RX_TPA_START_CMPL_TYPE_SFT 0\n+\t#define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)\n+\t#define RX_PKT_V2_CMPL_TYPE_SFT 0\n \t/*\n-\t * RX L2 TPA Start Completion:\n-\t * Completion at the beginning of a TPA operation.\n-\t * Length = 32B\n+\t * RX L2 V2 completion:\n+\t * Completion of and L2 RX packet. Length = 32B\n+\t * This is the new version of the RX_L2 completion used in SR2\n+\t * and later chips.\n \t */\n-\t#define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)\n-\t#define RX_TPA_START_CMPL_TYPE_LAST \\\n-\t\tRX_TPA_START_CMPL_TYPE_RX_TPA_START\n-\t#define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n-\t#define RX_TPA_START_CMPL_FLAGS_SFT 6\n-\t/* This bit will always be '0' for TPA start completions. */\n-\t#define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)\n+\t#define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)\n+\t#define RX_PKT_V2_CMPL_TYPE_LAST \\\n+\t\tRX_PKT_V2_CMPL_TYPE_RX_L2_V2\n+\t#define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define RX_PKT_V2_CMPL_FLAGS_SFT 6\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an\n+\t * error of some type. Type of error is indicated in\n+\t * error_flags.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)\n \t/* This field indicates how the packet was placed in the buffer. */\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t/*\n+\t * Normal:\n+\t * Packet was placed using normal algorithm.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL \\\n+\t\t(UINT32_C(0x0) << 7)\n \t/*\n \t * Jumbo:\n-\t * TPA Packet was placed using jumbo algorithm. This means\n-\t * that the first buffer will be filled with data before\n-\t * moving to aggregation buffers. Each aggregation buffer\n-\t * will be filled before moving to the next aggregation\n-\t * buffer.\n+\t * Packet was placed using jumbo algorithm.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \\\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO \\\n \t\t(UINT32_C(0x1) << 7)\n \t/*\n \t * Header/Data Separation:\n \t * Packet was placed using Header/Data separation algorithm.\n \t * The separation location is indicated by the itype field.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \\\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS \\\n \t\t(UINT32_C(0x2) << 7)\n \t/*\n-\t * GRO/Jumbo:\n-\t * Packet will be placed using GRO/Jumbo where the first\n-\t * packet is filled with data. Subsequent packets will be\n-\t * placed such that any one packet does not span two\n-\t * aggregation buffers unless it starts at the beginning of\n-\t * an aggregation buffer.\n+\t * Truncation:\n+\t * Packet was placed using truncation algorithm. The\n+\t * placed (truncated) length is indicated in the payload_offset\n+\t * field. The original length is indicated in the len field.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \\\n-\t\t(UINT32_C(0x5) << 7)\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION \\\n+\t\t(UINT32_C(0x3) << 7)\n+\t#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_LAST \\\n+\t\tRX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION\n+\t/* This bit is '1' if the RSS field in this completion is valid. */\n+\t#define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)\n \t/*\n-\t * GRO/Header-Data Separation:\n-\t * Packet will be placed using GRO/HDS where the header\n-\t * is in the first packet.\n-\t * Payload of each packet will be\n-\t * placed such that any one packet does not span two\n-\t * aggregation buffers unless it starts at the beginning of\n-\t * an aggregation buffer.\n+\t * This bit is '1' if metadata has been added to the end of the\n+\t * packet in host memory. Metadata starts at the first 32B boundary\n+\t * after the end of the packet for regular and jumbo placement.\n+\t * It starts at the first 32B boundary after the end of the header\n+\t * for HDS placement. The length of the metadata is indicated in the\n+\t * metadata itself.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \\\n-\t\t(UINT32_C(0x6) << 7)\n-\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \\\n-\t\tRX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS\n-\t/* This bit is '1' if the RSS field in this completion is valid. */\n-\t#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)\n-\t/* unused is 1 b */\n-\t#define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)\n+\t#define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)\n \t/*\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)\n-\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_SFT 12\n+\t/*\n+\t * Not Known:\n+\t * Indicates that the packet type was not known.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/*\n+\t * IP Packet:\n+\t * Indicates that the packet was an IP packet, but further\n+\t * classification was not possible.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP \\\n+\t\t(UINT32_C(0x1) << 12)\n \t/*\n \t * TCP Packet:\n \t * Indicates that the packet was IP and TCP.\n+\t * This indicates that the payload_offset field is valid.\n \t */\n-\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \\\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP \\\n \t\t(UINT32_C(0x2) << 12)\n-\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \\\n-\t\tRX_TPA_START_CMPL_FLAGS_ITYPE_TCP\n \t/*\n-\t * This value indicates the amount of packet data written to the\n-\t * buffer the opaque field in this completion corresponds to.\n+\t * UDP Packet:\n+\t * Indicates that the packet was IP and UDP.\n+\t * This indicates that the payload_offset field is valid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/*\n+\t * FCoE Packet:\n+\t * Indicates that the packet was recognized as a FCoE.\n+\t * This also indicates that the payload_offset field is valid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/*\n+\t * RoCE Packet:\n+\t * Indicates that the packet was recognized as a RoCE.\n+\t * This also indicates that the payload_offset field is valid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t/*\n+\t * ICMP Packet:\n+\t * Indicates that the packet was recognized as ICMP.\n+\t * This indicates that the payload_offset field is valid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP \\\n+\t\t(UINT32_C(0x7) << 12)\n+\t/*\n+\t * PtP packet wo/timestamp:\n+\t * Indicates that the packet was recognized as a PtP\n+\t * packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP \\\n+\t\t(UINT32_C(0x8) << 12)\n+\t/*\n+\t * PtP packet w/timestamp:\n+\t * Indicates that the packet was recognized as a PtP\n+\t * packet and that a timestamp was taken for the packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP \\\n+\t\t(UINT32_C(0x9) << 12)\n+\t#define RX_PKT_V2_CMPL_FLAGS_ITYPE_LAST \\\n+\t\tRX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP\n+\t/*\n+\t * This is the length of the data for the packet stored in the\n+\t * buffer(s) identified by the opaque value. This includes\n+\t * the packet BD and any associated buffer BDs. This does not include\n+\t * the length of any data places in aggregation BDs.\n \t */\n \tuint16_t\tlen;\n \t/*\n@@ -3102,19 +3519,597 @@ struct rx_tpa_start_cmpl {\n \t * corresponds to.\n \t */\n \tuint32_t\topaque;\n+\tuint8_t\tagg_bufs_v1;\n \t/*\n \t * This value is written by the NIC such that it will be different\n \t * for each pass through the completion queue. The even passes\n \t * will write 1. The odd passes will write 0.\n \t */\n-\tuint8_t\tv1;\n+\t#define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)\n \t/*\n-\t * This value is written by the NIC such that it will be different\n-\t * for each pass through the completion queue. The even passes\n-\t * will write 1. The odd passes will write 0.\n+\t * This value is the number of aggregation buffers that follow this\n+\t * entry in the completion ring that are a part of this packet.\n+\t * If the value is zero, then the packet is completely contained\n+\t * in the buffer space provided for the packet in the RX ring.\n \t */\n-\t#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)\n-\t#define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1\n+\t#define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)\n+\t#define RX_PKT_V2_CMPL_AGG_BUFS_SFT 1\n+\t/* unused1 is 2 b */\n+\t#define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)\n+\t#define RX_PKT_V2_CMPL_UNUSED1_SFT 6\n+\t/*\n+\t * This is the RSS hash type for the packet. The value is packed\n+\t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n+\t *\n+\t * The value of tuple_extrac_op provides the information about\n+\t * what fields the hash was computed on.\n+\t * * 0: The RSS hash was computed over source IP address,\n+\t * destination IP address, source port, and destination port of inner\n+\t * IP and TCP or UDP headers. Note: For non-tunneled packets,\n+\t * the packet headers are considered inner packet headers for the RSS\n+\t * hash computation purpose.\n+\t * * 1: The RSS hash was computed over source IP address and destination\n+\t * IP address of inner IP header. Note: For non-tunneled packets,\n+\t * the packet headers are considered inner packet headers for the RSS\n+\t * hash computation purpose.\n+\t * * 2: The RSS hash was computed over source IP address,\n+\t * destination IP address, source port, and destination port of\n+\t * IP and TCP or UDP headers of outer tunnel headers.\n+\t * Note: For non-tunneled packets, this value is not applicable.\n+\t * * 3: The RSS hash was computed over source IP address and\n+\t * destination IP address of IP header of outer tunnel headers.\n+\t * Note: For non-tunneled packets, this value is not applicable.\n+\t *\n+\t * Note that 4-tuples values listed above are applicable\n+\t * for layer 4 protocols supported and enabled for RSS in the hardware,\n+\t * HWRM firmware, and drivers. For example, if RSS hash is supported and\n+\t * enabled for TCP traffic only, then the values of tuple_extract_op\n+\t * corresponding to 4-tuples are only valid for TCP traffic.\n+\t */\n+\tuint8_t\trss_hash_type;\n+\tuint16_t\tmetadata1_payload_offset;\n+\t/*\n+\t * This is data from the CFA as indicated by the meta_format field.\n+\t * If truncation placement is not used, this value indicates the offset\n+\t * in bytes from the beginning of the packet where the inner payload\n+\t * starts. This value is valid for TCP, UDP, FCoE, and RoCE packets. If\n+\t * truncation placement is used, this value represents the placed\n+\t * (truncated) length of the packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)\n+\t#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0\n+\t/* This is data from the CFA as indicated by the meta_format field. */\n+\t#define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)\n+\t#define RX_PKT_V2_CMPL_METADATA1_SFT 12\n+\t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)\n+\t#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n+\t#define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)\n+\t/*\n+\t * This value is the RSS hash value calculated for the packet\n+\t * based on the mode bits and key value in the VNIC. When vee_cmpl_mode\n+\t * is set in VNIC context, this is the lower 32b of the host address\n+\t * from the first BD used to place the packet.\n+\t */\n+\tuint32_t\trss_hash;\n+} __rte_packed;\n+\n+/* Last 16 bytes of RX Packet V2 Completion Record */\n+/* rx_pkt_v2_cmpl_hi (size:128b/16B) */\n+struct rx_pkt_v2_cmpl_hi {\n+\tuint32_t\tflags2;\n+\t/*\n+\t * When this bit is '0', the cs_ok field has the following definition:-\n+\t * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum\n+\t * in the delivered packet, counted from the outer-most header group to\n+\t * the inner-most header group, stopping at the first error. -\n+\t * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum\n+\t * in the delivered packet, counted from the outer-most header group to\n+\t * the inner-most header group, stopping at the first error. When this\n+\t * bit is '1', the cs_ok field has the following definition: -\n+\t * hdr_cnt[2:0] = The number of header groups that were parsed by the\n+\t * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit\n+\t * will be '1' if all the parsed header groups with an IP checksum are\n+\t * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed\n+\t * header groups with an L4 checksum are valid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE \\\n+\t\tUINT32_C(0x8)\n+\t/* This value indicates what format the metadata field is. */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_SFT 4\n+\t/* There is no metadata information. Values are zero. */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],\n+\t * de, vid[11:0]} The metadata2 field contains the table scope\n+\t * and action record pointer. - metadata2[25:0] contains the\n+\t * action record pointer. - metadata2[31:26] contains the table\n+\t * scope.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}\n+\t * The metadata2 field contains the Tunnel ID\n+\t * value, justified to LSB. i\n+\t * - VXLAN = VNI[23:0] -> VXLAN Network ID\n+\t * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier\n+\t * - NVGRE = TNI[23:0] -> Tenant Network ID\n+\t * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0\n+\t * - IPv4 = 0 (not populated)\n+\t * - IPv6 = Flow Label[19:0]\n+\t * - PPPoE = sessionID[15:0]\n+\t * - MPLs = Outer label[19:0]\n+\t * - UPAR = Selected[31:0] with bit mask\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}\n+\t * The metadata2 field contains the 32b metadata from the prepended\n+\t * header (chdr_data).\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}\n+\t * The metadata2 field contains the outer_l3_offset,\n+\t * inner_l2_offset, inner_l3_offset, and inner_l4_size.\n+\t * - metadata2[8:0] contains the outer_l3_offset.\n+\t * - metadata2[17:9] contains the inner_l2_offset.\n+\t * - metadata2[26:18] contains the inner_l3_offset.\n+\t * - metadata2[31:27] contains the inner_l4_size.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_LAST \\\n+\t\tRX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET\n+\t/*\n+\t * This field indicates the IP type for the inner-most IP header.\n+\t * A value of '0' indicates IPv4. A value of '1' indicates IPv6.\n+\t * This value is only valid if itype indicates a packet\n+\t * with an IP header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This indicates that the complete 1's complement checksum was\n+\t * calculated for the packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This field indicates the status of IP and L4 CS calculations done\n+\t * by the chip. The format of this field is indicated by the\n+\t * cs_all_ok_mode bit.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK \\\n+\t\tUINT32_C(0xfc00)\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_SFT 10\n+\t/*\n+\t * This value is the complete 1's complement checksum calculated from\n+\t * the start of the outer L3 header to the end of the packet (not\n+\t * including the ethernet crc). It is valid when the\n+\t * 'complete_checksum_calc' flag is set.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK \\\n+\t\tUINT32_C(0xffff0000)\n+\t#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_SFT 16\n+\t/*\n+\t * This is data from the CFA block as indicated by the meta_format\n+\t * field.\n+\t * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped\n+\t * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],\n+\t * act_rec_ptr[25:0]}\n+\t * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]\n+\t * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]\n+\t * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]\n+\t * When vee_cmpl_mode is set in VNIC context, this is the upper 32b\n+\t * of the host address from the first BD used to place the packet.\n+\t */\n+\tuint32_t\tmetadata2;\n+\tuint16_t\terrors_v2;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_V2 \\\n+\t\tUINT32_C(0x1)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_MASK \\\n+\t\tUINT32_C(0xfffe)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_SFT 1\n+\t/*\n+\t * This error indicates that there was some sort of problem with\n+\t * the BDs for the packet that was found after part of the\n+\t * packet was already placed. The packet should be treated as\n+\t * invalid.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK \\\n+\t\tUINT32_C(0xe)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_SFT 1\n+\t/* No buffer error */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Did Not Fit: Packet did not fit into packet buffer provided.\n+\t * For regular placement, this means the packet did not fit in\n+\t * the buffer provided. For HDS and jumbo placement, this means\n+\t * that the packet could not be placed into 8 physical buffers\n+\t * (if fixed-size buffers are used), or that the packet could\n+\t * not be placed in the number of physical buffers configured\n+\t * for the VNIC (if variable-size buffers are used)\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/*\n+\t * Not On Chip: All BDs needed for the packet were not on-chip\n+\t * when the packet arrived. For regular placement, this error is\n+\t * not valid. For HDS and jumbo placement, this means that not\n+\t * enough agg BDs were posted to place the packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tRX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH\n+\t/*\n+\t * This indicates that there was an error in the outer tunnel\n+\t * portion of the packet when this field is non-zero.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK \\\n+\t\tUINT32_C(0x70)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_SFT 4\n+\t/*\n+\t * No additional error occurred on the outer tunnel portion\n+\t * of the packet or the packet does not have a outer tunnel.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/*\n+\t * Indicates that IP header version does not match expectation\n+\t * from L2 Ethertype for IPv4 and IPv6 in the outer tunnel header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/*\n+\t * Indicates that header length is out of range in the outer\n+\t * tunnel header. Valid for IPv4.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/*\n+\t * Indicates that physical packet is shorter than that claimed\n+\t * by the outer tunnel l3 header length. Valid for IPv4, or\n+\t * IPv6 outer tunnel packets.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/*\n+\t * Indicates that the physical packet is shorter than that\n+\t * claimed by the outer tunnel UDP header length for a outer\n+\t * tunnel UDP packet that is not fragmented.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/*\n+\t * Indicates that the IPv4 TTL or IPv6 hop limit check have\n+\t * failed (e.g. TTL = 0) in the outer tunnel header. Valid for\n+\t * IPv4, and IPv6.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t/*\n+\t * Indicates that the IP checksum failed its check in the outer\n+\t * tunnel header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR \\\n+\t\t(UINT32_C(0x6) << 4)\n+\t/*\n+\t * Indicates that the L4 checksum failed its check in the outer\n+\t * tunnel header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR \\\n+\t\t(UINT32_C(0x7) << 4)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_LAST \\\n+\t\tRX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR\n+\t/*\n+\t * This indicates that there was a CRC error on either an FCoE\n+\t * or RoCE packet. The itype indicates the packet type.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This indicates that there was an error in the tunnel portion\n+\t * of the packet when this field is non-zero.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK \\\n+\t\tUINT32_C(0xe00)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_SFT 9\n+\t/*\n+\t * No additional error occurred on the tunnel portion\n+\t * of the packet or the packet does not have a tunnel.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 9)\n+\t/*\n+\t * Indicates that IP header version does not match expectation\n+\t * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION \\\n+\t\t(UINT32_C(0x1) << 9)\n+\t/*\n+\t * Indicates that header length is out of range in the tunnel\n+\t * header. Valid for IPv4.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN \\\n+\t\t(UINT32_C(0x2) << 9)\n+\t/*\n+\t * Indicates that physical packet is shorter than that claimed\n+\t * by the tunnel l3 header length. Valid for IPv4, or IPv6 tunnel\n+\t * packet packets.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x3) << 9)\n+\t/*\n+\t * Indicates that the physical packet is shorter than that claimed\n+\t * by the tunnel UDP header length for a tunnel UDP packet that is\n+\t * not fragmented.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x4) << 9)\n+\t/*\n+\t * Indicates that the IPv4 TTL or IPv6 hop limit check have failed\n+\t * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL \\\n+\t\t(UINT32_C(0x5) << 9)\n+\t/*\n+\t * Indicates that the IP checksum failed its check in the tunnel\n+\t * header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR \\\n+\t\t(UINT32_C(0x6) << 9)\n+\t/*\n+\t * Indicates that the L4 checksum failed its check in the tunnel\n+\t * header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR \\\n+\t\t(UINT32_C(0x7) << 9)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_LAST \\\n+\t\tRX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR\n+\t/*\n+\t * This indicates that there was an error in the inner\n+\t * portion of the packet when this\n+\t * field is non-zero.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK \\\n+\t\tUINT32_C(0xf000)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_SFT 12\n+\t/*\n+\t * No additional error occurred on the tunnel portion\n+\t * or the packet of the packet does not have a tunnel.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/*\n+\t * Indicates that IP header version does not match\n+\t * expectation from L2 Ethertype for IPv4 and IPv6 or that\n+\t * option other than VFT was parsed on\n+\t * FCoE packet.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/*\n+\t * indicates that header length is out of range. Valid for\n+\t * IPv4 and RoCE\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/*\n+\t * indicates that the IPv4 TTL or IPv6 hop limit check\n+\t * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/*\n+\t * Indicates that physical packet is shorter than that\n+\t * claimed by the l3 header length. Valid for IPv4,\n+\t * IPv6 packet or RoCE packets.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/*\n+\t * Indicates that the physical packet is shorter than that\n+\t * claimed by the UDP header length for a UDP packet that is\n+\t * not fragmented.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t/*\n+\t * Indicates that TCP header length > IP payload. Valid for\n+\t * TCP packets only.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN \\\n+\t\t(UINT32_C(0x6) << 12)\n+\t/* Indicates that TCP header length < 5. Valid for TCP. */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \\\n+\t\t(UINT32_C(0x7) << 12)\n+\t/*\n+\t * Indicates that TCP option headers result in a TCP header\n+\t * size that does not match data offset in TCP header. Valid\n+\t * for TCP.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \\\n+\t\t(UINT32_C(0x8) << 12)\n+\t/*\n+\t * Indicates that the IP checksum failed its check in the\n+\t * inner header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR \\\n+\t\t(UINT32_C(0x9) << 12)\n+\t/*\n+\t * Indicates that the L4 checksum failed its check in the\n+\t * inner header.\n+\t */\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR \\\n+\t\t(UINT32_C(0xa) << 12)\n+\t#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_LAST \\\n+\t\tRX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR\n+\t/*\n+\t * This is data from the CFA block as indicated by the meta_format\n+\t * field.\n+\t */\n+\tuint16_t\tmetadata0;\n+\t/* When meta_format=1, this value is the VLAN VID. */\n+\t#define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)\n+\t#define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0\n+\t/* When meta_format=1, this value is the VLAN DE. */\n+\t#define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)\n+\t/* When meta_format=1, this value is the VLAN PRI. */\n+\t#define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)\n+\t#define RX_PKT_V2_CMPL_HI_METADATA0_PRI_SFT 13\n+\t/*\n+\t * The timestamp field contains the 32b timestamp for the packet from\n+\t * the MAC.\n+\t */\n+\tuint32_t\ttimestamp;\n+} __rte_packed;\n+\n+/*\n+ * This TPA completion structure is used on devices where the\n+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.\n+ */\n+/* rx_tpa_start_cmpl (size:128b/16B) */\n+struct rx_tpa_start_cmpl {\n+\tuint16_t\tflags_type;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)\n+\t#define RX_TPA_START_CMPL_TYPE_SFT 0\n+\t/*\n+\t * RX L2 TPA Start Completion:\n+\t * Completion at the beginning of a TPA operation.\n+\t * Length = 32B\n+\t */\n+\t#define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)\n+\t#define RX_TPA_START_CMPL_TYPE_LAST \\\n+\t\tRX_TPA_START_CMPL_TYPE_RX_TPA_START\n+\t#define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define RX_TPA_START_CMPL_FLAGS_SFT 6\n+\t/* This bit will always be '0' for TPA start completions. */\n+\t#define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)\n+\t/* This field indicates how the packet was placed in the buffer. */\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t/*\n+\t * Jumbo:\n+\t * TPA Packet was placed using jumbo algorithm. This means\n+\t * that the first buffer will be filled with data before\n+\t * moving to aggregation buffers. Each aggregation buffer\n+\t * will be filled before moving to the next aggregation\n+\t * buffer.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO \\\n+\t\t(UINT32_C(0x1) << 7)\n+\t/*\n+\t * Header/Data Separation:\n+\t * Packet was placed using Header/Data separation algorithm.\n+\t * The separation location is indicated by the itype field.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS \\\n+\t\t(UINT32_C(0x2) << 7)\n+\t/*\n+\t * GRO/Jumbo:\n+\t * Packet will be placed using GRO/Jumbo where the first\n+\t * packet is filled with data. Subsequent packets will be\n+\t * placed such that any one packet does not span two\n+\t * aggregation buffers unless it starts at the beginning of\n+\t * an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \\\n+\t\t(UINT32_C(0x5) << 7)\n+\t/*\n+\t * GRO/Header-Data Separation:\n+\t * Packet will be placed using GRO/HDS where the header\n+\t * is in the first packet.\n+\t * Payload of each packet will be\n+\t * placed such that any one packet does not span two\n+\t * aggregation buffers unless it starts at the beginning of\n+\t * an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS \\\n+\t\t(UINT32_C(0x6) << 7)\n+\t#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST \\\n+\t\tRX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS\n+\t/* This bit is '1' if the RSS field in this completion is valid. */\n+\t#define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)\n+\t/* unused is 1 b */\n+\t#define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)\n+\t/*\n+\t * This value indicates what the inner packet determined for the\n+\t * packet was.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)\n+\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12\n+\t/*\n+\t * TCP Packet:\n+\t * Indicates that the packet was IP and TCP.\n+\t */\n+\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t#define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST \\\n+\t\tRX_TPA_START_CMPL_FLAGS_ITYPE_TCP\n+\t/*\n+\t * This value indicates the amount of packet data written to the\n+\t * buffer the opaque field in this completion corresponds to.\n+\t */\n+\tuint16_t\tlen;\n+\t/*\n+\t * This is a copy of the opaque field from the RX BD this completion\n+\t * corresponds to.\n+\t */\n+\tuint32_t\topaque;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\tuint8_t\tv1;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)\n+\t#define RX_TPA_START_CMPL_LAST RX_TPA_START_CMPL_V1\n \t/*\n \t * This is the RSS hash type for the packet. The value is packed\n \t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n@@ -3285,6 +4280,430 @@ struct rx_tpa_start_cmpl_hi {\n \t#define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27\n } __rte_packed;\n \n+/*\n+ * This TPA completion structure is used on devices where the\n+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.\n+ * RX L2 TPA Start V2 Completion Record (32 bytes split to 2 16-byte\n+ * struct)\n+ */\n+/* rx_tpa_start_v2_cmpl (size:128b/16B) */\n+struct rx_tpa_start_v2_cmpl {\n+\tuint16_t\tflags_type;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define RX_TPA_START_V2_CMPL_TYPE_SFT 0\n+\t/*\n+\t * RX L2 TPA Start V2 Completion:\n+\t * Completion at the beginning of a TPA operation.\n+\t * Length = 32B\n+\t * This is the new version of the RX_TPA_START completion used\n+\t * in SR2 and later chips.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 \\\n+\t\tUINT32_C(0xd)\n+\t#define RX_TPA_START_V2_CMPL_TYPE_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_MASK \\\n+\t\tUINT32_C(0xffc0)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_SFT 6\n+\t/*\n+\t * When this bit is '1', it indicates a packet that has an error\n+\t * of some type. Type of error is indicated in error_flags.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_ERROR \\\n+\t\tUINT32_C(0x40)\n+\t/* This field indicates how the packet was placed in the buffer. */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK \\\n+\t\tUINT32_C(0x380)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t/*\n+\t * Jumbo:\n+\t * TPA Packet was placed using jumbo algorithm. This means\n+\t * that the first buffer will be filled with data before\n+\t * moving to aggregation buffers. Each aggregation buffer\n+\t * will be filled before moving to the next aggregation\n+\t * buffer.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO \\\n+\t\t(UINT32_C(0x1) << 7)\n+\t/*\n+\t * Header/Data Separation:\n+\t * Packet was placed using Header/Data separation algorithm.\n+\t * The separation location is indicated by the itype field.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS \\\n+\t\t(UINT32_C(0x2) << 7)\n+\t/*\n+\t * IOC/Jumbo:\n+\t * Packet will be placed using In-Order Completion/Jumbo where\n+\t * the first packet of the aggregation is placed using Jumbo\n+\t * Placement. Subsequent packets will be placed such that each\n+\t * packet starts at the beginning of an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \\\n+\t\t(UINT32_C(0x4) << 7)\n+\t/*\n+\t * GRO/Jumbo:\n+\t * Packet will be placed using GRO/Jumbo where the first\n+\t * packet is filled with data. Subsequent packets will be\n+\t * placed such that any one packet does not span two\n+\t * aggregation buffers unless it starts at the beginning of\n+\t * an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO \\\n+\t\t(UINT32_C(0x5) << 7)\n+\t/*\n+\t * GRO/Header-Data Separation:\n+\t * Packet will be placed using GRO/HDS where the header\n+\t * is in the first packet.\n+\t * Payload of each packet will be\n+\t * placed such that any one packet does not span two\n+\t * aggregation buffers unless it starts at the beginning of\n+\t * an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS \\\n+\t\t(UINT32_C(0x6) << 7)\n+\t/*\n+\t * IOC/Header-Data Separation:\n+\t * Packet will be placed using In-Order Completion/HDS where\n+\t * the header is in the first packet buffer. Payload of each\n+\t * packet will be placed such that each packet starts at the\n+\t * beginning of an aggregation buffer.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS \\\n+\t\t(UINT32_C(0x7) << 7)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS\n+\t/* This bit is '1' if the RSS field in this completion is valid. */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit is '1' if metadata has been added to the end of the\n+\t * packet in host memory. Metadata starts at the first 32B boundary\n+\t * after the end of the packet for regular and jumbo placement. It\n+\t * starts at the first 32B boundary after the end of the header for\n+\t * HDS placement. The length of the metadata is indicated in the\n+\t * metadata itself.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This value indicates what the inner packet determined for the\n+\t * packet was.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK \\\n+\t\tUINT32_C(0xf000)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_SFT 12\n+\t/*\n+\t * TCP Packet:\n+\t * Indicates that the packet was IP and TCP.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP\n+\t/*\n+\t * This value indicates the amount of packet data written to the\n+\t * buffer the opaque field in this completion corresponds to.\n+\t */\n+\tuint16_t\tlen;\n+\t/*\n+\t * This is a copy of the opaque field from the RX BD this completion\n+\t * corresponds to. If the VNIC is configured to not use an Rx BD for\n+\t * the TPA Start completion, then this is a copy of the opaque field\n+\t * from the first BD used to place the TPA Start packet.\n+\t */\n+\tuint32_t\topaque;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\tuint8_t\tv1;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)\n+\t#define RX_TPA_START_V2_CMPL_LAST RX_TPA_START_V2_CMPL_V1\n+\t/*\n+\t * This is the RSS hash type for the packet. The value is packed\n+\t * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.\n+\t *\n+\t * The value of tuple_extrac_op provides the information about\n+\t * what fields the hash was computed on.\n+\t * * 0: The RSS hash was computed over source IP address,\n+\t * destination IP address, source port, and destination port of inner\n+\t * IP and TCP or UDP headers. Note: For non-tunneled packets,\n+\t * the packet headers are considered inner packet headers for the RSS\n+\t * hash computation purpose.\n+\t * * 1: The RSS hash was computed over source IP address and destination\n+\t * IP address of inner IP header. Note: For non-tunneled packets,\n+\t * the packet headers are considered inner packet headers for the RSS\n+\t * hash computation purpose.\n+\t * * 2: The RSS hash was computed over source IP address,\n+\t * destination IP address, source port, and destination port of\n+\t * IP and TCP or UDP headers of outer tunnel headers.\n+\t * Note: For non-tunneled packets, this value is not applicable.\n+\t * * 3: The RSS hash was computed over source IP address and\n+\t * destination IP address of IP header of outer tunnel headers.\n+\t * Note: For non-tunneled packets, this value is not applicable.\n+\t *\n+\t * Note that 4-tuples values listed above are applicable\n+\t * for layer 4 protocols supported and enabled for RSS in the hardware,\n+\t * HWRM firmware, and drivers. For example, if RSS hash is supported and\n+\t * enabled for TCP traffic only, then the values of tuple_extract_op\n+\t * corresponding to 4-tuples are only valid for TCP traffic.\n+\t */\n+\tuint8_t\trss_hash_type;\n+\t/*\n+\t * This is the aggregation ID that the completion is associated\n+\t * with. Use this number to correlate the TPA start completion\n+\t * with the TPA end completion.\n+\t */\n+\tuint16_t\tagg_id;\n+\t/*\n+\t * This is the aggregation ID that the completion is associated\n+\t * with. Use this number to correlate the TPA start completion\n+\t * with the TPA end completion.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)\n+\t#define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_SFT 12\n+\t/* When meta_format != 0, this value is the VLAN TPID_SEL. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_SFT 12\n+\t/* When meta_format != 0, this value is the VLAN valid. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)\n+\t/*\n+\t * This value is the RSS hash value calculated for the packet\n+\t * based on the mode bits and key value in the VNIC.\n+\t * When vee_cmpl_mode is set in VNIC context, this is the lower\n+\t * 32b of the host address from the first BD used to place the packet.\n+\t */\n+\tuint32_t\trss_hash;\n+} __rte_packed;\n+\n+/*\n+ * Last 16 bytes of RX L2 TPA Start V2 Completion Record\n+ *\n+ * This TPA completion structure is used on devices where the\n+ * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.\n+ */\n+/* rx_tpa_start_v2_cmpl_hi (size:128b/16B) */\n+struct rx_tpa_start_v2_cmpl_hi {\n+\tuint32_t\tflags2;\n+\t/* This indicates that the aggregation was done using GRO rules. */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '0', the cs_ok field has the following definition:-\n+\t * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum\n+\t * in the delivered packet, counted from the outer-most header group to\n+\t * the inner-most header group, stopping at the first error. -\n+\t * l4_cs_ok[5:3] = The number of header groups with a valid L4 checksum\n+\t * in the delivered packet, counted from the outer-most header group to\n+\t * the inner-most header group, stopping at the first error. When this\n+\t * bit is '1', the cs_ok field has the following definition: -\n+\t * hdr_cnt[2:0] = The number of header groups that were parsed by the\n+\t * chip and passed in the delivered packet. - ip_cs_all_ok[3] =This bit\n+\t * will be '1' if all the parsed header groups with an IP checksum are\n+\t * valid. - l4_cs_all_ok[4] = This bit will be '1' if all the parsed\n+\t * header groups with an L4 checksum are valid.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE \\\n+\t\tUINT32_C(0x8)\n+\t/* This value indicates what format the metadata field is. */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_SFT 4\n+\t/* There is no metadata information. Values are zero. */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],\n+\t * de, vid[11:0]} The metadata2 field contains the table scope\n+\t * and action record pointer. - metadata2[25:0] contains the\n+\t * action record pointer. - metadata2[31:26] contains the table\n+\t * scope.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}\n+\t * The metadata2 field contains the Tunnel ID\n+\t * value, justified to LSB. i\n+\t * - VXLAN = VNI[23:0] -> VXLAN Network ID\n+\t * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier\n+\t * - NVGRE = TNI[23:0] -> Tenant Network ID\n+\t * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0\n+\t * - IPv4 = 0 (not populated)\n+\t * - IPv6 = Flow Label[19:0]\n+\t * - PPPoE = sessionID[15:0]\n+\t * - MPLs = Outer label[19:0]\n+\t * - UPAR = Selected[31:0] with bit mask\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}\n+\t * The metadata2 field contains the 32b metadata from the prepended\n+\t * header (chdr_data).\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/*\n+\t * The {metadata1, metadata0} fields contain the vtag\n+\t * information:\n+\t * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}\n+\t * The metadata2 field contains the outer_l3_offset,\n+\t * inner_l2_offset, inner_l3_offset, and inner_l4_size.\n+\t * - metadata2[8:0] contains the outer_l3_offset.\n+\t * - metadata2[17:9] contains the inner_l2_offset.\n+\t * - metadata2[26:18] contains the inner_l3_offset.\n+\t * - metadata2[31:27] contains the inner_l4_size.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET\n+\t/*\n+\t * This field indicates the IP type for the inner-most IP header.\n+\t * A value of '0' indicates IPv4. A value of '1' indicates IPv6.\n+\t * This value is only valid if itype indicates a packet\n+\t * with an IP header.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This indicates that the complete 1's complement checksum was\n+\t * calculated for the packet in the affregation.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This field indicates the status of IP and L4 CS calculations done\n+\t * by the chip. The format of this field is indicated by the\n+\t * cs_all_ok_mode bit.\n+\t * CS status for TPA packets is always valid. This means that \"all_ok\"\n+\t * status will always be set. The ok count status will be set\n+\t * appropriately for the packet header, such that all existing CS\n+\t * values are ok.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK \\\n+\t\tUINT32_C(0xfc00)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_SFT 10\n+\t/*\n+\t * This value is the complete 1's complement checksum calculated from\n+\t * the start of the outer L3 header to the end of the packet (not\n+\t * including the ethernet crc). It is valid when the\n+\t * 'complete_checksum_calc' flag is set. For TPA Start completions,\n+\t * the complete checksum is calculated for the first packet in the\n+\t * aggregation only.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \\\n+\t\tUINT32_C(0xffff0000)\n+\t#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16\n+\t/*\n+\t * This is data from the CFA block as indicated by the meta_format\n+\t * field.\n+\t * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped\n+\t * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],\n+\t * act_rec_ptr[25:0]}\n+\t * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]\n+\t * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]\n+\t * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]\n+\t * When vee_cmpl_mode is set in VNIC context, this is the upper 32b\n+\t * of the host address from the first BD used to place the packet.\n+\t */\n+\tuint32_t\tmetadata2;\n+\tuint16_t\terrors_v2;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_V2 \\\n+\t\tUINT32_C(0x1)\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_MASK \\\n+\t\tUINT32_C(0xfffe)\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_SFT 1\n+\t/*\n+\t * This error indicates that there was some sort of problem with\n+\t * the BDs for the packetThe packet should be treated as\n+\t * invalid.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK \\\n+\t\tUINT32_C(0xe)\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_SFT 1\n+\t/* No buffer error */\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Did Not Fit:\n+\t * Packet did not fit into packet buffer provided. This means\n+\t * that the TPA Start packet was too big to be placed into the\n+\t * per-packet maximum number of physical buffers configured for\n+\t * the VNIC, or that it was too big to be placed into the\n+\t * per-aggregation maximum number of physical buffers configured\n+\t * for the VNIC. This error only occurs when the VNIC is\n+\t * configured for variable size receive buffers.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/*\n+\t * Bad Format:\n+\t * BDs were not formatted correctly.\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t/*\n+\t * Flush:\n+\t * There was a bad_format error on the previous operation\n+\t */\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH \\\n+\t\t(UINT32_C(0x5) << 1)\n+\t#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_LAST \\\n+\t\tRX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH\n+\t/*\n+\t * This is data from the CFA block as indicated by the meta_format\n+\t * field.\n+\t */\n+\tuint16_t\tmetadata0;\n+\t/* When meta_format != 0, this value is the VLAN VID. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)\n+\t#define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0\n+\t/* When meta_format != 0, this value is the VLAN DE. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)\n+\t/* When meta_format != 0, this value is the VLAN PRI. */\n+\t#define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)\n+\t#define RX_TPA_START_V2_CMPL_METADATA0_PRI_SFT 13\n+\t/*\n+\t * This field contains the outer_l3_offset, inner_l2_offset,\n+\t * inner_l3_offset, and inner_l4_size.\n+\t *\n+\t * hdr_offsets[8:0] contains the outer_l3_offset.\n+\t * hdr_offsets[17:9] contains the inner_l2_offset.\n+\t * hdr_offsets[26:18] contains the inner_l3_offset.\n+\t * hdr_offsets[31:27] contains the inner_l4_size.\n+\t */\n+\tuint32_t\thdr_offsets;\n+} __rte_packed;\n+\n /*\n * This TPA completion structure is used on devices where the\n * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.\n@@ -3299,27 +4718,27 @@ struct rx_tpa_end_cmpl {\n \t * records. Odd values indicate 32B\n \t * records.\n \t */\n-\t#define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)\n-\t#define RX_TPA_END_CMPL_TYPE_SFT 0\n+\t#define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)\n+\t#define RX_TPA_END_CMPL_TYPE_SFT 0\n \t/*\n \t * RX L2 TPA End Completion:\n \t * Completion at the end of a TPA operation.\n \t * Length = 32B\n \t */\n-\t#define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)\n+\t#define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)\n \t#define RX_TPA_END_CMPL_TYPE_LAST \\\n \t\tRX_TPA_END_CMPL_TYPE_RX_TPA_END\n-\t#define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n-\t#define RX_TPA_END_CMPL_FLAGS_SFT 6\n+\t#define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define RX_TPA_END_CMPL_FLAGS_SFT 6\n \t/*\n \t * When this bit is '1', it indicates a packet that has an\n \t * error of some type. Type of error is indicated in\n \t * error_flags.\n \t */\n-\t#define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)\n+\t#define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)\n \t/* This field indicates how the packet was placed in the buffer. */\n-\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n-\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7\n+\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)\n+\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7\n \t/*\n \t * Jumbo:\n \t * TPA Packet was placed using jumbo algorithm. This means\n@@ -3337,6 +4756,15 @@ struct rx_tpa_end_cmpl {\n \t */\n \t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS \\\n \t\t(UINT32_C(0x2) << 7)\n+\t/*\n+\t * IOC/Jumbo:\n+\t * Packet will be placed using In-Order Completion/Jumbo where\n+\t * the first packet of the aggregation is placed using Jumbo\n+\t * Placement. Subsequent packets will be placed such that each\n+\t * packet starts at the beginning of an aggregation buffer.\n+\t */\n+\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO \\\n+\t\t(UINT32_C(0x4) << 7)\n \t/*\n \t * GRO/Jumbo:\n \t * Packet will be placed using GRO/Jumbo where the first\n@@ -3358,11 +4786,28 @@ struct rx_tpa_end_cmpl {\n \t */\n \t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS \\\n \t\t(UINT32_C(0x6) << 7)\n+\t/*\n+\t * IOC/Header-Data Separation:\n+\t * Packet will be placed using In-Order Completion/HDS where\n+\t * the header is in the first packet buffer. Payload of each\n+\t * packet will be placed such that each packet starts at the\n+\t * beginning of an aggregation buffer.\n+\t */\n+\t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS \\\n+\t\t(UINT32_C(0x7) << 7)\n \t#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST \\\n-\t\tRX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS\n-\t/* unused is 2 b */\n-\t#define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)\n-\t#define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10\n+\t\tRX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS\n+\t/* unused is 1 b */\n+\t#define RX_TPA_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)\n+\t/*\n+\t * This bit is '1' if metadata has been added to the end of the\n+\t * packet in host memory. Metadata starts at the first 32B boundary\n+\t * after the end of the packet for regular and jumbo placement.\n+\t * It starts at the first 32B boundary after the end of the header\n+\t * for HDS placement. The length of the metadata is indicated in the\n+\t * metadata itself.\n+\t */\n+\t#define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)\n \t/*\n \t * This value indicates what the inner packet determined for the\n \t * packet was.\n@@ -3372,8 +4817,9 @@ struct rx_tpa_end_cmpl {\n \t * field is valid and contains the TCP checksum.\n \t * This also indicates that the payload_offset field is valid.\n \t */\n-\t#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)\n-\t#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12\n+\t#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK \\\n+\t\tUINT32_C(0xf000)\n+\t#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12\n \t/*\n \t * This value is zero for TPA End completions.\n \t * There is no data in the buffer that corresponds to the opaque\n@@ -4243,6 +5689,52 @@ struct rx_abuf_cmpl {\n \tuint32_t\tunused_2;\n } __rte_packed;\n \n+/* VEE FLUSH Completion Record (16 bytes) */\n+/* vee_flush (size:128b/16B) */\n+struct vee_flush {\n+\tuint32_t\tdownstream_path_type;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)\n+\t#define VEE_FLUSH_TYPE_SFT 0\n+\t/*\n+\t * VEE Flush Completion:\n+\t * This completion is inserted manually by the Primate and processed\n+\t * by the VEE hardware to ensure that all completions on a VEE\n+\t * function have been processed by the VEE hardware before FLR\n+\t * process is completed.\n+\t */\n+\t#define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)\n+\t#define VEE_FLUSH_TYPE_LAST VEE_FLUSH_TYPE_VEE_FLUSH\n+\t/* downstream_path is 1 b */\n+\t#define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)\n+\t/* This completion is associated with VEE Transmit */\n+\t#define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)\n+\t/* This completion is associated with VEE Receive */\n+\t#define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)\n+\t#define VEE_FLUSH_DOWNSTREAM_PATH_LAST VEE_FLUSH_DOWNSTREAM_PATH_RX\n+\t/*\n+\t * This is an opaque value that is passed through the completion\n+\t * to the VEE handler SW and is used to indicate what VEE VQ or\n+\t * function has completed FLR processing.\n+\t */\n+\tuint32_t\topaque;\n+\tuint32_t\tv;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes will\n+\t * write 1. The odd passes will write 0.\n+\t */\n+\t#define VEE_FLUSH_V UINT32_C(0x1)\n+\t/* unused3 is 32 b */\n+\tuint32_t\tunused_3;\n+} __rte_packed;\n+\n /* eject_cmpl (size:128b/16B) */\n struct eject_cmpl {\n \tuint16_t\ttype;\n@@ -6562,7 +8054,7 @@ struct hwrm_async_event_cmpl_deferred_response {\n \t/*\n \t * The PF's mailbox is clear to issue another command.\n \t * A command with this seq_id is still in progress\n-\t * and will return a regular HWRM completion when done.\n+\t * and will return a regualr HWRM completion when done.\n \t * 'event_data1' field, if non-zero, contains the estimated\n \t * execution time for the command.\n \t */\n@@ -7476,6 +8968,8 @@ struct hwrm_func_qcaps_input {\n \t * Function ID of the function that is being queried.\n \t * 0xFF... (All Fs) if the query is for the requesting\n \t * function.\n+\t * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID\n+\t * to be used by a trusted VF to query its parent PF.\n \t */\n \tuint16_t\tfid;\n \tuint8_t\tunused_0[6];\n@@ -7729,6 +9223,12 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \\\n \t\tUINT32_C(0x40000000)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware supports\n+\t * DBG_QCAPS command\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED \\\n+\t\tUINT32_C(0x80000000)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -7854,6 +9354,19 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \\\n \t\tUINT32_C(0x2)\n+\t/*\n+\t * If 1, the device can report extended hw statistics (including\n+\t * additional tpa statistics).\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then the core firmware has support to enable/\n+\t * disable hot reset support for interface dynamically through\n+\t * HWRM_FUNC_CFG.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT \\\n+\t\tUINT32_C(0x8)\n \tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -7904,6 +9417,8 @@ struct hwrm_func_qcfg_input {\n \t * Function ID of the function that is being queried.\n \t * 0xFF... (All Fs) if the query is for the requesting\n \t * function.\n+\t * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID\n+\t * to be used by a trusted VF to query its parent PF.\n \t */\n \tuint16_t\tfid;\n \tuint8_t\tunused_0[6];\n@@ -8013,6 +9528,15 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \\\n \t\tUINT32_C(0x100)\n+\t/*\n+\t * If set to 1, then the firmware and all currently registered driver\n+\t * instances support hot reset. The hot reset support will be updated\n+\t * dynamically based on the driver interface advertisement.\n+\t * If set to 0, then the adapter is not currently able to initiate\n+\t * hot reset.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED \\\n+\t\tUINT32_C(0x200)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -8565,6 +10089,17 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS \\\n \t\tUINT32_C(0x2000000)\n+\t/*\n+\t * If this bit is set to 0, then the interface does not support hot\n+\t * reset capability which it advertised with the hot_reset_support\n+\t * flag in HWRM_FUNC_DRV_RGTR. If any of the function has set this\n+\t * flag to 0, adapter cannot do the hot reset. In this state, if the\n+\t * firmware receives a hot reset request, firmware must fail the\n+\t * request. If this bit is set to 1, then interface is renabling the\n+\t * hot reset capability.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS \\\n+\t\tUINT32_C(0x4000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -8704,6 +10239,12 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \\\n \t\tUINT32_C(0x400000)\n+\t/*\n+\t * This bit must be '1' for the hot_reset_if_en_dis field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT \\\n+\t\tUINT32_C(0x800000)\n \t/*\n \t * The maximum transmission unit of the function.\n \t * The HWRM should make sure that the mtu of\n@@ -9036,15 +10577,21 @@ struct hwrm_func_qstats_input {\n \t/* This flags indicates the type of statistics request. */\n \tuint8_t\tflags;\n \t/* This value is not used to avoid backward compatibility issues. */\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n \t/*\n \t * flags should be set to 1 when request is for only RoCE statistics.\n \t * This will be honored only if the caller_fid is a privileged PF.\n \t * In all other cases FID and caller_fid should be the same.\n \t */\n-\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t/*\n+\t * flags should be set to 2 when request is for the counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n \t#define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \\\n-\t\tHWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY\n+\t\tHWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK\n \tuint8_t\tunused_0[5];\n } __rte_packed;\n \n@@ -9130,6 +10677,132 @@ struct hwrm_func_qstats_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/************************\n+ * hwrm_func_qstats_ext *\n+ ************************/\n+\n+\n+/* hwrm_func_qstats_ext_input (size:192b/24B) */\n+struct hwrm_func_qstats_ext_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being queried.\n+\t * 0xFF... (All Fs) if the query is for the requesting\n+\t * function.\n+\t * A privileged PF can query for other function's statistics.\n+\t */\n+\tuint16_t\tfid;\n+\t/* This flags indicates the type of statistics request. */\n+\tuint8_t\tflags;\n+\t/* This value is not used to avoid backward compatibility issues. */\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n+\t/*\n+\t * flags should be set to 1 when request is for only RoCE statistics.\n+\t * This will be honored only if the caller_fid is a privileged PF.\n+\t * In all other cases FID and caller_fid should be the same.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)\n+\t/*\n+\t * flags should be set to 2 when request is for the counter mask\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)\n+\t#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \\\n+\t\tHWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK\n+\tuint8_t\tunused_0[5];\n+} __rte_packed;\n+\n+/* hwrm_func_qstats_ext_output (size:1472b/184B) */\n+struct hwrm_func_qstats_ext_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on received path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA eligible packets */\n+\tuint64_t\trx_tpa_eligible_pkt;\n+\t/* Number of TPA eligible bytes */\n+\tuint64_t\trx_tpa_eligible_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\trx_tpa_pkt;\n+\t/* Number of TPA bytes */\n+\tuint64_t\trx_tpa_bytes;\n+\t/* Number of TPA errors */\n+\tuint64_t\trx_tpa_errors;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***********************\n * hwrm_func_clr_stats *\n ***********************/\n@@ -10116,7 +11789,7 @@ struct hwrm_func_backing_store_qcaps_output {\n \t *\n \t * TQM slowpath rings should be sized as follows:\n \t *\n-\t * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size\n+\t * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size\n \t *\n \t * Where:\n \t * num_vnics is the number of VNICs allocated in the VNIC backing store\n@@ -11039,7 +12712,7 @@ struct hwrm_func_backing_store_cfg_input {\n \t *\n \t * TQM slowpath rings should be sized as follows:\n \t *\n-\t * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size\n+\t * num_entries = num_vnics + num_l2_tx_rings + 2 * num_roce_qps + tqm_min_size\n \t *\n \t * Where:\n \t * num_vnics is the number of VNICs allocated in the VNIC backing store\n@@ -16149,7 +17822,18 @@ struct hwrm_port_qstats_input {\n \tuint64_t\tresp_addr;\n \t/* Port ID of port that is being queried. */\n \tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tflags;\n+\t/* This value is not used to avoid backward compatibility issues. */\n+\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n+\t/*\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n+\t#define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \\\n+\t\tHWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This is the host address where\n \t * Tx port statistics will be stored\n@@ -16382,7 +18066,7 @@ struct rx_port_stats_ext {\n * Port Rx Statistics extended PFC WatchDog Format.\n * StormDetect and StormRevert event determination is based\n * on an integration period and a percentage threshold.\n- * StormDetect event - when percentage of XOFF frames received\n+ * StormDetect event - when percentage of XOFF frames receieved\n * within an integration period exceeds the configured threshold.\n * StormRevert event - when percentage of XON frames received\n * within an integration period exceeds the configured threshold.\n@@ -16843,7 +18527,18 @@ struct hwrm_port_qstats_ext_input {\n \t * statistics block in bytes\n \t */\n \tuint16_t\trx_stat_size;\n-\tuint8_t\tunused_0[2];\n+\tuint8_t\tflags;\n+\t/* This value is not used to avoid backward compatibility issues. */\n+\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0)\n+\t/*\n+\t * This bit is set to 1 when request is for the counter mask,\n+\t * representing width of each of the stats counters, rather than\n+\t * counters themselves.\n+\t */\n+\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n+\t#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \\\n+\t\tHWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK\n+\tuint8_t\tunused_0;\n \t/*\n \t * This is the host address where\n \t * Tx port statistics will be stored\n@@ -25312,95 +27007,104 @@ struct hwrm_ring_free_input {\n \t/* Ring Type. */\n \tuint8_t\tring_type;\n \t/* L2 Completion Ring (CR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t/* RoCE Notification Completion Ring (ROCE_CR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n+\t/* RX Aggregation Ring */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n+\t/* Notification Queue */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_FREE_INPUT_RING_TYPE_NQ\n+\tuint8_t\tunused_0;\n+\t/* Physical number of ring allocated. */\n+\tuint16_t\tring_id;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_ring_free_output (size:128b/16B) */\n+struct hwrm_ring_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************\n+ * hwrm_ring_reset *\n+ *******************/\n+\n+\n+/* hwrm_ring_reset_input (size:192b/24B) */\n+struct hwrm_ring_reset_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* L2 Completion Ring (CR) */\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n \t/* TX Ring (TR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)\n \t/* RX Ring (RR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)\n \t/* RoCE Notification Completion Ring (ROCE_CR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n-\t/* RX Aggregation Ring */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n-\t/* Notification Queue */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \\\n-\t\tHWRM_RING_FREE_INPUT_RING_TYPE_NQ\n-\tuint8_t\tunused_0;\n-\t/* Physical number of ring allocated. */\n-\tuint16_t\tring_id;\n-\tuint8_t\tunused_1[4];\n-} __rte_packed;\n-\n-/* hwrm_ring_free_output (size:128b/16B) */\n-struct hwrm_ring_free_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Rx Ring Group. This is to reset rx and aggregation in an atomic\n+\t * operation. Completion ring associated with this ring group is\n+\t * not reset.\n \t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/*******************\n- * hwrm_ring_reset *\n- *******************/\n-\n-\n-/* hwrm_ring_reset_input (size:192b/24B) */\n-struct hwrm_ring_reset_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* Ring Type. */\n-\tuint8_t\tring_type;\n-\t/* L2 Completion Ring (CR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n-\t/* TX Ring (TR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)\n-\t/* RX Ring (RR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)\n-\t/* RoCE Notification Completion Ring (ROCE_CR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)\n \t#define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \\\n-\t\tHWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL\n+\t\tHWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP\n \tuint8_t\tunused_0;\n-\t/* Physical number of the ring. */\n+\t/*\n+\t * Physical number of the ring. When ring type is rx_ring_grp, ring id\n+\t * actually refers to ring group id.\n+\t */\n \tuint16_t\tring_id;\n \tuint8_t\tunused_1[4];\n } __rte_packed;\n@@ -25615,7 +27319,18 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {\n \tuint64_t\tresp_addr;\n \t/* Physical number of completion ring. */\n \tuint16_t\tring_id;\n-\tuint8_t\tunused_0[6];\n+\tuint16_t\tflags;\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0\n+\t/*\n+\t * Set this flag to 1 when querying parameters on a notification\n+\t * queue. Set this flag to 0 when querying parameters on a\n+\t * completion queue or completion ring.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ \\\n+\t\tUINT32_C(0x4)\n+\tuint8_t\tunused_0[4];\n } __rte_packed;\n \n /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */\n@@ -25652,19 +27367,19 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output {\n \t */\n \tuint16_t\tnum_cmpl_dma_aggr_during_int;\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * Timer used to aggregate completions before\n \t * DMA during the normal mode (not in interrupt mode).\n \t */\n \tuint16_t\tcmpl_aggr_dma_tmr;\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the interrupt mode.\n+\t * Timer used to aggregate completions before\n+\t * DMA when in interrupt mode.\n \t */\n \tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n-\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n+\t/* Minimum time between two interrupts. */\n \tuint16_t\tint_lat_tmr_min;\n \t/*\n-\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n+\t * Maximum wait time spent aggregating\n \t * completions before signaling the interrupt after the\n \t * interrupt is enabled.\n \t */\n@@ -25738,7 +27453,7 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {\n \t/*\n \t * Set this flag to 1 when configuring parameters on a\n \t * notification queue. Set this flag to 0 when configuring\n-\t * parameters on a completion queue.\n+\t * parameters on a completion queue or completion ring.\n \t */\n \t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \\\n \t\tUINT32_C(0x4)\n@@ -25753,20 +27468,20 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {\n \t */\n \tuint16_t\tnum_cmpl_dma_aggr_during_int;\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * Timer used to aggregate completions before\n \t * DMA during the normal mode (not in interrupt mode).\n \t */\n \tuint16_t\tcmpl_aggr_dma_tmr;\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the interrupt mode.\n+\t * Timer used to aggregate completions before\n+\t * DMA while in interrupt mode.\n \t */\n \tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n-\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n+\t/* Minimum time between two interrupts. */\n \tuint16_t\tint_lat_tmr_min;\n \t/*\n-\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n-\t * cmpls before signaling the interrupt after the\n+\t * Maximum wait time spent aggregating\n+\t * completions before signaling the interrupt after the\n \t * interrupt is enabled.\n \t */\n \tuint16_t\tint_lat_tmr_max;\n@@ -33339,78 +35054,246 @@ struct hwrm_tf_version_get_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-} __rte_packed;\n-\n-/* hwrm_tf_version_get_output (size:128b/16B) */\n-struct hwrm_tf_version_get_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Version Major number. */\n-\tuint8_t\tmajor;\n-\t/* Version Minor number. */\n-\tuint8_t\tminor;\n-\t/* Version Update number. */\n-\tuint8_t\tupdate;\n-\t/* unused. */\n-\tuint8_t\tunused0[4];\n+} __rte_packed;\n+\n+/* hwrm_tf_version_get_output (size:128b/16B) */\n+struct hwrm_tf_version_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Version Major number. */\n+\tuint8_t\tmajor;\n+\t/* Version Minor number. */\n+\tuint8_t\tminor;\n+\t/* Version Update number. */\n+\tuint8_t\tupdate;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/************************\n+ * hwrm_tf_session_open *\n+ ************************/\n+\n+\n+/* hwrm_tf_session_open_input (size:640b/80B) */\n+struct hwrm_tf_session_open_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Name of the session. */\n+\tuint8_t\tsession_name[64];\n+} __rte_packed;\n+\n+/* hwrm_tf_session_open_output (size:192b/24B) */\n+struct hwrm_tf_session_open_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/*\n+\t * Unique session client identifier for the first client on\n+\t * the newly created session.\n+\t */\n+\tuint32_t\tfw_session_client_id;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* unused. */\n+\tuint8_t\tunused1[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**************************\n+ * hwrm_tf_session_attach *\n+ **************************/\n+\n+\n+/* hwrm_tf_session_attach_input (size:704b/88B) */\n+struct hwrm_tf_session_attach_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session that the attach\n+\t * request want to attach to. This value originates from the\n+\t * shared session memory that the attach request opened by\n+\t * way of the 'attach name' that was passed in to the core\n+\t * attach API.\n+\t * The fw_session_id of the attach session includes PCIe bus\n+\t * info to distinguish the PF and session info to identify\n+\t * the associated TruFlow session.\n+\t */\n+\tuint32_t\tattach_fw_session_id;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Name of the session it self. */\n+\tuint8_t\tsession_name[64];\n+} __rte_packed;\n+\n+/* hwrm_tf_session_attach_output (size:128b/16B) */\n+struct hwrm_tf_session_attach_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. It includes PCIe bus info to distinguish the PF\n+\t * and session info to identify the associated TruFlow\n+\t * session. This fw_session_id is unique to the attach\n+\t * request.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_tf_session_register *\n+ ****************************/\n+\n+\n+/* hwrm_tf_session_register_input (size:704b/88B) */\n+struct hwrm_tf_session_register_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field is\n-\t * written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/************************\n- * hwrm_tf_session_open *\n- ************************/\n-\n-\n-/* hwrm_tf_session_open_input (size:640b/80B) */\n-struct hwrm_tf_session_open_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Unique session identifier for the session that the\n+\t * register request want to create a new client on. This\n+\t * value originates from the first open request.\n+\t * The fw_session_id of the attach session includes PCIe bus\n+\t * info to distinguish the PF and session info to identify\n+\t * the associated TruFlow session.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Name of the session. */\n-\tuint8_t\tsession_name[64];\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Name of the session client. */\n+\tuint8_t\tsession_client_name[64];\n } __rte_packed;\n \n-/* hwrm_tf_session_open_output (size:128b/16B) */\n-struct hwrm_tf_session_open_output {\n+/* hwrm_tf_session_register_output (size:128b/16B) */\n+struct hwrm_tf_session_register_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -33420,12 +35303,11 @@ struct hwrm_tf_session_open_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Unique session identifier for the session created by the\n-\t * firmware. It includes PCIe bus info to distinguish the PF\n-\t * and session info to identify the associated TruFlow\n-\t * session.\n+\t * Unique session client identifier for the session created\n+\t * by the firmware. It includes the session the client it\n+\t * attached to and session client info.\n \t */\n-\tuint32_t\tfw_session_id;\n+\tuint32_t\tfw_session_client_id;\n \t/* unused. */\n \tuint8_t\tunused0[3];\n \t/*\n@@ -33439,13 +35321,13 @@ struct hwrm_tf_session_open_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/**************************\n- * hwrm_tf_session_attach *\n- **************************/\n+/******************************\n+ * hwrm_tf_session_unregister *\n+ ******************************/\n \n \n-/* hwrm_tf_session_attach_input (size:704b/88B) */\n-struct hwrm_tf_session_attach_input {\n+/* hwrm_tf_session_unregister_input (size:192b/24B) */\n+struct hwrm_tf_session_unregister_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -33475,24 +35357,19 @@ struct hwrm_tf_session_attach_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Unique session identifier for the session that the attach\n-\t * request want to attach to. This value originates from the\n-\t * shared session memory that the attach request opened by\n-\t * way of the 'attach name' that was passed in to the core\n-\t * attach API.\n-\t * The fw_session_id of the attach session includes PCIe bus\n-\t * info to distinguish the PF and session info to identify\n-\t * the associated TruFlow session.\n+\t * Unique session identifier for the session that the\n+\t * unregister request want to close a session client on.\n \t */\n-\tuint32_t\tattach_fw_session_id;\n-\t/* unused. */\n-\tuint32_t\tunused0;\n-\t/* Name of the session it self. */\n-\tuint8_t\tsession_name[64];\n+\tuint32_t\tfw_session_id;\n+\t/*\n+\t * Unique session client identifier for the session that the\n+\t * unregister request want to close.\n+\t */\n+\tuint32_t\tfw_session_client_id;\n } __rte_packed;\n \n-/* hwrm_tf_session_attach_output (size:128b/16B) */\n-struct hwrm_tf_session_attach_output {\n+/* hwrm_tf_session_unregister_output (size:128b/16B) */\n+struct hwrm_tf_session_unregister_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -33501,16 +35378,8 @@ struct hwrm_tf_session_attach_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Unique session identifier for the session created by the\n-\t * firmware. It includes PCIe bus info to distinguish the PF\n-\t * and session info to identify the associated TruFlow\n-\t * session. This fw_session_id is unique to the attach\n-\t * request.\n-\t */\n-\tuint32_t\tfw_session_id;\n \t/* unused. */\n-\tuint8_t\tunused0[3];\n+\tuint8_t\tunused0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -33746,15 +35615,17 @@ struct hwrm_tf_session_resc_qcaps_input {\n \t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * Defines the size, in bytes, of the provided qcaps_addr\n+\t * Defines the size of the provided qcaps_addr array\n \t * buffer. The size should be set to the Resource Manager\n-\t * provided max qcaps value that is device specific. This is\n-\t * the max size possible.\n+\t * provided max number of qcaps entries which is device\n+\t * specific. Resource Manager gets the max size from HCAPI\n+\t * RM.\n \t */\n-\tuint16_t\tsize;\n+\tuint16_t\tqcaps_size;\n \t/*\n-\t * This is the DMA address for the qcaps output data\n-\t * array. Array is of tf_rm_cap type and is device specific.\n+\t * This is the DMA address for the qcaps output data array\n+\t * buffer. Array is of tf_rm_resc_req_entry type and is\n+\t * device specific.\n \t */\n \tuint64_t\tqcaps_addr;\n } __rte_packed;\n@@ -33772,29 +35643,28 @@ struct hwrm_tf_session_resc_qcaps_output {\n \t/* Control flags. */\n \tuint32_t\tflags;\n \t/* Session reservation strategy. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK \\\n \t\tUINT32_C(0x3)\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT \\\n \t\t0\n \t/* Static partitioning. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC \\\n \t\tUINT32_C(0x0)\n \t/* Strategy 1. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 \\\n \t\tUINT32_C(0x1)\n \t/* Strategy 2. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 \\\n \t\tUINT32_C(0x2)\n \t/* Strategy 3. */\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \\\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 \\\n \t\tUINT32_C(0x3)\n-\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \\\n-\t\tHWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3\n \t/*\n-\t * Size of the returned tf_rm_cap data array. The value\n-\t * cannot exceed the size defined by the input msg. The data\n-\t * array is returned using the qcaps_addr specified DMA\n-\t * address also provided by the input msg.\n+\t * Size of the returned qcaps_addr data array buffer. The\n+\t * value cannot exceed the size defined by the input msg,\n+\t * qcaps_size.\n \t */\n \tuint16_t\tsize;\n \t/* unused. */\n@@ -33817,7 +35687,7 @@ struct hwrm_tf_session_resc_qcaps_output {\n ******************************/\n \n \n-/* hwrm_tf_session_resc_alloc_input (size:256b/32B) */\n+/* hwrm_tf_session_resc_alloc_input (size:320b/40B) */\n struct hwrm_tf_session_resc_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -33860,16 +35730,25 @@ struct hwrm_tf_session_resc_alloc_input {\n \t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * Defines the size, in bytes, of the provided num_addr\n-\t * buffer.\n+\t * Defines the array size of the provided req_addr and\n+\t * resv_addr array buffers. Should be set to the number of\n+\t * request entries.\n \t */\n-\tuint16_t\tsize;\n+\tuint16_t\treq_size;\n+\t/*\n+\t * This is the DMA address for the request input data array\n+\t * buffer. Array is of tf_rm_resc_req_entry type. Size of the\n+\t * array buffer is provided by the 'req_size' field in this\n+\t * message.\n+\t */\n+\tuint64_t\treq_addr;\n \t/*\n-\t * This is the DMA address for the num input data array\n-\t * buffer. Array is of tf_rm_num type. Size of the buffer is\n-\t * provided by the 'size' field in this message.\n+\t * This is the DMA address for the resc output data array\n+\t * buffer. Array is of tf_rm_resc_entry type. Size of the array\n+\t * buffer is provided by the 'req_size' field in this\n+\t * message.\n \t */\n-\tuint64_t\tnum_addr;\n+\tuint64_t\tresc_addr;\n } __rte_packed;\n \n /* hwrm_tf_session_resc_alloc_output (size:128b/16B) */\n@@ -33882,8 +35761,15 @@ struct hwrm_tf_session_resc_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * Size of the returned tf_rm_resc_entry data array. The value\n+\t * cannot exceed the req_size defined by the input msg. The data\n+\t * array is returned using the resv_addr specified DMA\n+\t * address also provided by the input msg.\n+\t */\n+\tuint16_t\tsize;\n \t/* unused. */\n-\tuint8_t\tunused0[7];\n+\tuint8_t\tunused0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -33946,11 +35832,12 @@ struct hwrm_tf_session_resc_free_input {\n \t * Defines the size, in bytes, of the provided free_addr\n \t * buffer.\n \t */\n-\tuint16_t\tsize;\n+\tuint16_t\tfree_size;\n \t/*\n \t * This is the DMA address for the free input data array\n-\t * buffer. Array of tf_rm_res type. Size of the buffer is\n-\t * provided by the 'size field of this message.\n+\t * buffer. Array is of tf_rm_resc_entry type. Size of the\n+\t * buffer is provided by the 'free_size' field of this\n+\t * message.\n \t */\n \tuint64_t\tfree_addr;\n } __rte_packed;\n@@ -34029,11 +35916,12 @@ struct hwrm_tf_session_resc_flush_input {\n \t * Defines the size, in bytes, of the provided flush_addr\n \t * buffer.\n \t */\n-\tuint16_t\tsize;\n+\tuint16_t\tflush_size;\n \t/*\n \t * This is the DMA address for the flush input data array\n-\t * buffer. Array of tf_rm_res type. Size of the buffer is\n-\t * provided by the 'size' field in this message.\n+\t * buffer. Array of tf_rm_resc_entry type. Size of the\n+\t * buffer is provided by the 'flush_size' field in this\n+\t * message.\n \t */\n \tuint64_t\tflush_addr;\n } __rte_packed;\n@@ -34062,12 +35950,9 @@ struct hwrm_tf_session_resc_flush_output {\n } __rte_packed;\n \n /* TruFlow RM capability of a resource. */\n-/* tf_rm_cap (size:64b/8B) */\n-struct tf_rm_cap {\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n+/* tf_rm_resc_req_entry (size:64b/8B) */\n+struct tf_rm_resc_req_entry {\n+\t/* Type of the resource, defined globally in HCAPI RM. */\n \tuint32_t\ttype;\n \t/* Minimum value. */\n \tuint16_t\tmin;\n@@ -34075,25 +35960,10 @@ struct tf_rm_cap {\n \tuint16_t\tmax;\n } __rte_packed;\n \n-/* TruFlow RM number of a resource. */\n-/* tf_rm_num (size:64b/8B) */\n-struct tf_rm_num {\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n-\tuint32_t\ttype;\n-\t/* Number of resources. */\n-\tuint32_t\tnum;\n-} __rte_packed;\n-\n /* TruFlow RM reservation information. */\n-/* tf_rm_res (size:64b/8B) */\n-struct tf_rm_res {\n-\t/*\n-\t * Type of the resource, defined globally in the\n-\t * hwrm_tf_resc_type enum.\n-\t */\n+/* tf_rm_resc_entry (size:64b/8B) */\n+struct tf_rm_resc_entry {\n+\t/* Type of the resource, defined globally in HCAPI RM. */\n \tuint32_t\ttype;\n \t/* Start offset. */\n \tuint16_t\tstart;\n@@ -34925,6 +36795,162 @@ struct hwrm_tf_ext_em_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/*********************\n+ * hwrm_tf_em_insert *\n+ *********************/\n+\n+\n+/* hwrm_tf_em_insert_input (size:832b/104B) */\n+struct hwrm_tf_em_insert_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware Session Id. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control Flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX\n+\t/* Reported match strength. */\n+\tuint16_t\tstrength;\n+\t/* Index to action. */\n+\tuint32_t\taction_ptr;\n+\t/* Index of EM record. */\n+\tuint32_t\tem_record_idx;\n+\t/* EM Key value. */\n+\tuint64_t\tem_key[8];\n+\t/* Number of bits in em_key. */\n+\tuint16_t\tem_key_bitlen;\n+\t/* unused. */\n+\tuint16_t\tunused0[3];\n+} __rte_packed;\n+\n+/* hwrm_tf_em_insert_output (size:128b/16B) */\n+struct hwrm_tf_em_insert_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* EM record pointer index. */\n+\tuint16_t\trptr_index;\n+\t/* EM record offset 0~3. */\n+\tuint8_t\trptr_entry;\n+\t/* Number of word entries consumed by the key. */\n+\tuint8_t\tnum_of_entries;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+} __rte_packed;\n+\n+/*********************\n+ * hwrm_tf_em_delete *\n+ *********************/\n+\n+\n+/* hwrm_tf_em_delete_input (size:832b/104B) */\n+struct hwrm_tf_em_delete_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Session Id. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)\n+\t#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX\n+\t/* Unused0 */\n+\tuint16_t\tunused0;\n+\t/* EM internal flow hanndle. */\n+\tuint64_t\tflow_handle;\n+\t/* EM Key value */\n+\tuint64_t\tem_key[8];\n+\t/* Number of bits in em_key. */\n+\tuint16_t\tem_key_bitlen;\n+\t/* unused. */\n+\tuint16_t\tunused1[3];\n+} __rte_packed;\n+\n+/* hwrm_tf_em_delete_output (size:128b/16B) */\n+struct hwrm_tf_em_delete_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Original stack allocation index. */\n+\tuint16_t\tem_index;\n+\t/* unused. */\n+\tuint16_t\tunused0[3];\n+} __rte_packed;\n+\n /********************\n * hwrm_tf_tcam_set *\n ********************/\n@@ -35582,10 +37608,10 @@ struct ctx_hw_stats {\n \tuint64_t\trx_mcast_pkts;\n \t/* Number of received broadcast packets */\n \tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on received path */\n+\t/* Number of discarded packets on receive path */\n \tuint64_t\trx_discard_pkts;\n-\t/* Number of dropped packets on received path */\n-\tuint64_t\trx_drop_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n \t/* Number of received bytes for unicast traffic */\n \tuint64_t\trx_ucast_bytes;\n \t/* Number of received bytes for multicast traffic */\n@@ -35598,10 +37624,10 @@ struct ctx_hw_stats {\n \tuint64_t\ttx_mcast_pkts;\n \t/* Number of transmitted broadcast packets */\n \tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n \t/* Number of discarded packets on transmit path */\n \tuint64_t\ttx_discard_pkts;\n-\t/* Number of dropped packets on transmit path */\n-\tuint64_t\ttx_drop_pkts;\n \t/* Number of transmitted bytes for unicast traffic */\n \tuint64_t\ttx_ucast_bytes;\n \t/* Number of transmitted bytes for multicast traffic */\n@@ -35618,7 +37644,11 @@ struct ctx_hw_stats {\n \tuint64_t\ttpa_aborts;\n } __rte_packed;\n \n-/* Periodic statistics context DMA to host. */\n+/*\n+ * Extended periodic statistics context DMA to host. On cards that\n+ * support TPA v2, additional TPA related stats exist and can be retrieved\n+ * by DMA of ctx_hw_stats_ext, rather than legacy ctx_hw_stats structure.\n+ */\n /* ctx_hw_stats_ext (size:1344b/168B) */\n struct ctx_hw_stats_ext {\n \t/* Number of received unicast packets */\n@@ -35627,10 +37657,10 @@ struct ctx_hw_stats_ext {\n \tuint64_t\trx_mcast_pkts;\n \t/* Number of received broadcast packets */\n \tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on received path */\n+\t/* Number of discarded packets on receive path */\n \tuint64_t\trx_discard_pkts;\n-\t/* Number of dropped packets on received path */\n-\tuint64_t\trx_drop_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n \t/* Number of received bytes for unicast traffic */\n \tuint64_t\trx_ucast_bytes;\n \t/* Number of received bytes for multicast traffic */\n@@ -35643,10 +37673,10 @@ struct ctx_hw_stats_ext {\n \tuint64_t\ttx_mcast_pkts;\n \t/* Number of transmitted broadcast packets */\n \tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n \t/* Number of discarded packets on transmit path */\n \tuint64_t\ttx_discard_pkts;\n-\t/* Number of dropped packets on transmit path */\n-\tuint64_t\ttx_drop_pkts;\n \t/* Number of transmitted bytes for unicast traffic */\n \tuint64_t\ttx_ucast_bytes;\n \t/* Number of transmitted bytes for multicast traffic */\n@@ -35912,7 +37942,14 @@ struct hwrm_stat_ctx_query_input {\n \tuint64_t\tresp_addr;\n \t/* ID of the statistics context that is being queried. */\n \tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\tuint8_t\tflags;\n+\t/*\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n } __rte_packed;\n \n /* hwrm_stat_ctx_query_output (size:1408b/176B) */\n@@ -35949,7 +37986,7 @@ struct hwrm_stat_ctx_query_output {\n \tuint64_t\trx_bcast_pkts;\n \t/* Number of received packets with error */\n \tuint64_t\trx_err_pkts;\n-\t/* Number of dropped packets on received path */\n+\t/* Number of dropped packets on receive path */\n \tuint64_t\trx_drop_pkts;\n \t/* Number of received bytes for unicast traffic */\n \tuint64_t\trx_ucast_bytes;\n@@ -35976,6 +38013,117 @@ struct hwrm_stat_ctx_query_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/***************************\n+ * hwrm_stat_ext_ctx_query *\n+ ***************************/\n+\n+\n+/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */\n+struct hwrm_stat_ext_ctx_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* ID of the extended statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tflags;\n+\t/*\n+\t * This bit is set to 1 when request is for a counter mask,\n+\t * representing the width of each of the stats counters, rather\n+\t * than counters themselves.\n+\t */\n+\t#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n+} __rte_packed;\n+\n+/* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */\n+struct hwrm_stat_ext_ctx_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on receive path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of packets on receive path with error */\n+\tuint64_t\trx_error_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of packets on transmit path with error */\n+\tuint64_t\ttx_error_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA eligible packets */\n+\tuint64_t\trx_tpa_eligible_pkt;\n+\t/* Number of TPA eligible bytes */\n+\tuint64_t\trx_tpa_eligible_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\trx_tpa_pkt;\n+\t/* Number of TPA bytes */\n+\tuint64_t\trx_tpa_bytes;\n+\t/* Number of TPA errors */\n+\tuint64_t\trx_tpa_errors;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /***************************\n * hwrm_stat_ctx_eng_query *\n ***************************/\n@@ -37565,6 +39713,13 @@ struct hwrm_nvm_install_update_input {\n \t */\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, FW will verify the package in the \"UPDATE\" NVM item\n+\t * without installing it. This flag is for FW internal use only.\n+\t * Users should not set this flag. The request will otherwise fail.\n+\t */\n+\t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY \\\n+\t\tUINT32_C(0x8)\n \tuint8_t\tunused_0[2];\n } __rte_packed;\n \n@@ -38115,6 +40270,72 @@ struct hwrm_nvm_validate_option_cmd_err {\n \tuint8_t\tunused_0[7];\n } __rte_packed;\n \n+/****************\n+ * hwrm_oem_cmd *\n+ ****************/\n+\n+\n+/* hwrm_oem_cmd_input (size:1024b/128B) */\n+struct hwrm_oem_cmd_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tIANA;\n+\tuint32_t\tunused_0;\n+\t/* This field contains the vendor specific command data. */\n+\tuint32_t\toem_data[26];\n+} __rte_packed;\n+\n+/* hwrm_oem_cmd_output (size:768b/96B) */\n+struct hwrm_oem_cmd_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tIANA;\n+\tuint32_t\tunused_0;\n+\t/* This field contains the vendor specific response data. */\n+\tuint32_t\toem_data[18];\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /*****************\n * hwrm_fw_reset *\n ******************/\n@@ -38338,6 +40559,55 @@ struct hwrm_port_ts_query_output {\n \tuint8_t\t\tvalid;\n } __rte_packed;\n \n+/*\n+ * This structure is fixed at the beginning of the ChiMP SRAM (GRC\n+ * offset: 0x31001F0). Host software is expected to read from this\n+ * location for a defined signature. If it exists, the software can\n+ * assume the presence of this structure and the validity of the\n+ * FW_STATUS location in the next field.\n+ */\n+/* hcomm_status (size:64b/8B) */\n+struct hcomm_status {\n+\tuint32_t\tsig_ver;\n+\t/*\n+\t * This field defines the version of the structure. The latest\n+\t * version value is 1.\n+\t */\n+\t#define HCOMM_STATUS_VER_MASK\t\tUINT32_C(0xff)\n+\t#define HCOMM_STATUS_VER_SFT\t\t0\n+\t#define HCOMM_STATUS_VER_LATEST\t\tUINT32_C(0x1)\n+\t#define HCOMM_STATUS_VER_LAST\t\tHCOMM_STATUS_VER_LATEST\n+\t/*\n+\t * This field is to store the signature value to indicate the\n+\t * presence of the structure.\n+\t */\n+\t#define HCOMM_STATUS_SIGNATURE_MASK\tUINT32_C(0xffffff00)\n+\t#define HCOMM_STATUS_SIGNATURE_SFT\t8\n+\t#define HCOMM_STATUS_SIGNATURE_VAL\t(UINT32_C(0x484353) << 8)\n+\t#define HCOMM_STATUS_SIGNATURE_LAST\tHCOMM_STATUS_SIGNATURE_VAL\n+\tuint32_t\tfw_status_loc;\n+\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK\tUINT32_C(0x3)\n+\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT\t0\n+\t/* PCIE configuration space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG\tUINT32_C(0x0)\n+\t/* GRC space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC\tUINT32_C(0x1)\n+\t/* BAR0 space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0\tUINT32_C(0x2)\n+\t/* BAR1 space */\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\tUINT32_C(0x3)\n+\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST\t\\\n+\t\tHCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\n+\t/*\n+\t * This offset where the fw_status register is located. The value\n+\t * is generally 4-byte aligned.\n+\t */\n+\t#define HCOMM_STATUS_TRUE_OFFSET_MASK\t\tUINT32_C(0xfffffffc)\n+\t#define HCOMM_STATUS_TRUE_OFFSET_SFT\t\t2\n+} __rte_packed;\n+/* This is the GRC offset where the hcomm_status struct resides. */\n+#define HCOMM_STATUS_STRUCT_LOC\t\t0x31001F0UL\n+\n /**************************\n * hwrm_cfa_counter_qcaps *\n **************************/\n@@ -38622,53 +40892,4 @@ struct hwrm_cfa_counter_qstats_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*\n- * This structure is fixed at the beginning of the ChiMP SRAM (GRC\n- * offset: 0x31001F0). Host software is expected to read from this\n- * location for a defined signature. If it exists, the software can\n- * assume the presence of this structure and the validity of the\n- * FW_STATUS location in the next field.\n- */\n-/* hcomm_status (size:64b/8B) */\n-struct hcomm_status {\n-\tuint32_t\tsig_ver;\n-\t/*\n-\t * This field defines the version of the structure. The latest\n-\t * version value is 1.\n-\t */\n-\t#define HCOMM_STATUS_VER_MASK\t\tUINT32_C(0xff)\n-\t#define HCOMM_STATUS_VER_SFT\t\t0\n-\t#define HCOMM_STATUS_VER_LATEST\t\tUINT32_C(0x1)\n-\t#define HCOMM_STATUS_VER_LAST\t\tHCOMM_STATUS_VER_LATEST\n-\t/*\n-\t * This field is to store the signature value to indicate the\n-\t * presence of the structure.\n-\t */\n-\t#define HCOMM_STATUS_SIGNATURE_MASK\tUINT32_C(0xffffff00)\n-\t#define HCOMM_STATUS_SIGNATURE_SFT\t8\n-\t#define HCOMM_STATUS_SIGNATURE_VAL\t(UINT32_C(0x484353) << 8)\n-\t#define HCOMM_STATUS_SIGNATURE_LAST\tHCOMM_STATUS_SIGNATURE_VAL\n-\tuint32_t\tfw_status_loc;\n-\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK\tUINT32_C(0x3)\n-\t#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT\t0\n-\t/* PCIE configuration space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG\tUINT32_C(0x0)\n-\t/* GRC space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC\tUINT32_C(0x1)\n-\t/* BAR0 space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0\tUINT32_C(0x2)\n-\t/* BAR1 space */\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\tUINT32_C(0x3)\n-\t#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST\t\\\n-\t\tHCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1\n-\t/*\n-\t * This offset where the fw_status register is located. The value\n-\t * is generally 4-byte aligned.\n-\t */\n-\t#define HCOMM_STATUS_TRUE_OFFSET_MASK\t\tUINT32_C(0xfffffffc)\n-\t#define HCOMM_STATUS_TRUE_OFFSET_SFT\t\t2\n-} __rte_packed;\n-/* This is the GRC offset where the hcomm_status struct resides. */\n-#define HCOMM_STATUS_STRUCT_LOC\t\t0x31001F0UL\n-\n #endif /* _HSI_STRUCT_DEF_DPDK_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/hwrm_tf.h b/drivers/net/bnxt/tf_core/hwrm_tf.h\nindex 341909573..439950e02 100644\n--- a/drivers/net/bnxt/tf_core/hwrm_tf.h\n+++ b/drivers/net/bnxt/tf_core/hwrm_tf.h\n@@ -86,6 +86,7 @@ struct tf_tbl_type_get_output;\n struct tf_em_internal_insert_input;\n struct tf_em_internal_insert_output;\n struct tf_em_internal_delete_input;\n+struct tf_em_internal_delete_output;\n /* Input params for session attach */\n typedef struct tf_session_attach_input {\n \t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent */\n@@ -949,6 +950,8 @@ typedef struct tf_em_internal_insert_output {\n \tuint16_t\t\t\t rptr_index;\n \t/* EM record offset 0~3 */\n \tuint8_t\t\t\t rptr_entry;\n+\t/* Number of word entries consumed by the key */\n+\tuint8_t\t\t\t num_of_entries;\n } tf_em_internal_insert_output_t, *ptf_em_internal_insert_output_t;\n \n /* Input params for EM INTERNAL rule delete */\n@@ -969,4 +972,10 @@ typedef struct tf_em_internal_delete_input {\n \tuint16_t\t\t\t em_key_bitlen;\n } tf_em_internal_delete_input_t, *ptf_em_internal_delete_input_t;\n \n+/* Input params for EM INTERNAL rule delete */\n+typedef struct tf_em_internal_delete_output {\n+\t/* Original stack allocation index */\n+\tuint16_t\t\t\t em_index;\n+} tf_em_internal_delete_output_t, *ptf_em_internal_delete_output_t;\n+\n #endif /* _HWRM_TF_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/lookup3.h b/drivers/net/bnxt/tf_core/lookup3.h\nindex e5abcc2f2..b1fd2cd43 100644\n--- a/drivers/net/bnxt/tf_core/lookup3.h\n+++ b/drivers/net/bnxt/tf_core/lookup3.h\n@@ -152,7 +152,6 @@ static inline uint32_t hashword(const uint32_t *k,\n \t\tfinal(a, b, c);\n \t\t/* Falls through. */\n \tcase 0:\t /* case 0: nothing left to add */\n-\t\t/* FALLTHROUGH */\n \t\tbreak;\n \t}\n \t/*------------------------------------------------- report the result */\ndiff --git a/drivers/net/bnxt/tf_core/stack.c b/drivers/net/bnxt/tf_core/stack.c\nindex 9cfbd244f..954806377 100644\n--- a/drivers/net/bnxt/tf_core/stack.c\n+++ b/drivers/net/bnxt/tf_core/stack.c\n@@ -27,6 +27,14 @@ stack_init(int num_entries, uint32_t *items, struct stack *st)\n \treturn 0;\n }\n \n+/*\n+ * Return the address of the items\n+ */\n+uint32_t *stack_items(struct stack *st)\n+{\n+\treturn st->items;\n+}\n+\n /* Return the size of the stack\n */\n int32_t\ndiff --git a/drivers/net/bnxt/tf_core/stack.h b/drivers/net/bnxt/tf_core/stack.h\nindex ebd055592..6732e0313 100644\n--- a/drivers/net/bnxt/tf_core/stack.h\n+++ b/drivers/net/bnxt/tf_core/stack.h\n@@ -36,6 +36,16 @@ int stack_init(int num_entries,\n \t uint32_t *items,\n \t struct stack *st);\n \n+/** Return the address of the stack contents\n+ *\n+ * [in] st\n+ * pointer to the stack\n+ *\n+ * return\n+ * pointer to the stack contents\n+ */\n+uint32_t *stack_items(struct stack *st);\n+\n /** Return the size of the stack\n *\n * [in] st\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex cf9f36adb..1f6c33ab5 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -45,6 +45,100 @@ static void tf_seeds_init(struct tf_session *session)\n \t}\n }\n \n+/**\n+ * Create EM Tbl pool of memory indexes.\n+ *\n+ * [in] session\n+ * Pointer to session\n+ * [in] dir\n+ * direction\n+ * [in] num_entries\n+ * number of entries to write\n+ *\n+ * Return:\n+ * 0 - Success, entry allocated - no search support\n+ * -ENOMEM -EINVAL -EOPNOTSUPP\n+ * - Failure, entry not allocated, out of resources\n+ */\n+static int\n+tf_create_em_pool(struct tf_session *session,\n+\t\t enum tf_dir dir,\n+\t\t uint32_t num_entries)\n+{\n+\tstruct tfp_calloc_parms parms;\n+\tuint32_t i, j;\n+\tint rc = 0;\n+\tstruct stack *pool = &session->em_pool[dir];\n+\n+\tparms.nitems = num_entries;\n+\tparms.size = sizeof(uint32_t);\n+\tparms.alignment = 0;\n+\n+\tif (tfp_calloc(&parms) != 0) {\n+\t\tTFP_DRV_LOG(ERR, \"EM pool allocation failure %s\\n\",\n+\t\t\t strerror(-ENOMEM));\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Create empty stack\n+\t */\n+\trc = stack_init(num_entries, parms.mem_va, pool);\n+\n+\tif (rc != 0) {\n+\t\tTFP_DRV_LOG(ERR, \"EM pool stack init failure %s\\n\",\n+\t\t\t strerror(-rc));\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Fill pool with indexes\n+\t */\n+\tj = num_entries - 1;\n+\n+\tfor (i = 0; i < num_entries; i++) {\n+\t\trc = stack_push(pool, j);\n+\t\tif (rc != 0) {\n+\t\t\tTFP_DRV_LOG(ERR, \"EM pool stack push failure %s\\n\",\n+\t\t\t\t strerror(-rc));\n+\t\t\tgoto cleanup;\n+\t\t}\n+\t\tj--;\n+\t}\n+\n+\tif (!stack_is_full(pool)) {\n+\t\trc = -EINVAL;\n+\t\tTFP_DRV_LOG(ERR, \"EM pool stack failure %s\\n\",\n+\t\t\t strerror(-rc));\n+\t\tgoto cleanup;\n+\t}\n+\n+\treturn 0;\n+cleanup:\n+\ttfp_free((void *)parms.mem_va);\n+\treturn rc;\n+}\n+\n+/**\n+ * Create EM Tbl pool of memory indexes.\n+ *\n+ * [in] session\n+ * Pointer to session\n+ * [in] dir\n+ * direction\n+ *\n+ * Return:\n+ */\n+static void\n+tf_free_em_pool(struct tf_session *session,\n+\t\tenum tf_dir dir)\n+{\n+\tstruct stack *pool = &session->em_pool[dir];\n+\tuint32_t *ptr;\n+\n+\tptr = stack_items(pool);\n+\n+\ttfp_free(ptr);\n+}\n+\n int\n tf_open_session(struct tf *tfp,\n \t\tstruct tf_open_session_parms *parms)\n@@ -54,6 +148,7 @@ tf_open_session(struct tf *tfp,\n \tstruct tfp_calloc_parms alloc_parms;\n \tunsigned int domain, bus, slot, device;\n \tuint8_t fw_session_id;\n+\tint dir;\n \n \tif (tfp == NULL || parms == NULL)\n \t\treturn -EINVAL;\n@@ -110,7 +205,7 @@ tf_open_session(struct tf *tfp,\n \t\tgoto cleanup;\n \t}\n \n-\ttfp->session = (struct tf_session_info *)alloc_parms.mem_va;\n+\ttfp->session = alloc_parms.mem_va;\n \n \t/* Allocate core data for the session */\n \talloc_parms.nitems = 1;\n@@ -175,6 +270,16 @@ tf_open_session(struct tf *tfp,\n \t/* Setup hash seeds */\n \ttf_seeds_init(session);\n \n+\t/* Initialize EM pool */\n+\tfor (dir = 0; dir < TF_DIR_MAX; dir++) {\n+\t\trc = tf_create_em_pool(session, dir, TF_SESSION_EM_POOL_SIZE);\n+\t\tif (rc) {\n+\t\t\tTFP_DRV_LOG(ERR,\n+\t\t\t\t \"EM Pool initialization failed\\n\");\n+\t\t\tgoto cleanup_close;\n+\t\t}\n+\t}\n+\n \tsession->ref_count++;\n \n \t/* Return session ID */\n@@ -239,6 +344,7 @@ tf_close_session(struct tf *tfp)\n \tint rc_close = 0;\n \tstruct tf_session *tfs;\n \tunion tf_session_id session_id;\n+\tint dir;\n \n \tif (tfp == NULL || tfp->session == NULL)\n \t\treturn -EINVAL;\n@@ -268,6 +374,10 @@ tf_close_session(struct tf *tfp)\n \n \t/* Final cleanup as we're last user of the session */\n \tif (tfs->ref_count == 0) {\n+\t\t/* Free EM pool */\n+\t\tfor (dir = 0; dir < TF_DIR_MAX; dir++)\n+\t\t\ttf_free_em_pool(tfs, dir);\n+\n \t\ttfp_free(tfp->session->core_data);\n \t\ttfp_free(tfp->session);\n \t\ttfp->session = NULL;\n@@ -301,16 +411,25 @@ int tf_insert_em_entry(struct tf *tfp,\n \tif (tfp == NULL || parms == NULL)\n \t\treturn -EINVAL;\n \n-\ttbl_scope_cb =\n-\t\ttbl_scope_cb_find((struct tf_session *)tfp->session->core_data,\n-\t\t\t\t parms->tbl_scope_id);\n+\ttbl_scope_cb = tbl_scope_cb_find((struct tf_session *)\n+\t\t\t\t\t (tfp->session->core_data),\n+\t\t\t\t\t parms->tbl_scope_id);\n \tif (tbl_scope_cb == NULL)\n \t\treturn -EINVAL;\n \n \t/* Process the EM entry per Table Scope type */\n-\treturn tf_insert_eem_entry((struct tf_session *)tfp->session->core_data,\n-\t\t\t\t tbl_scope_cb,\n-\t\t\t\t parms);\n+\tif (parms->mem == TF_MEM_EXTERNAL) {\n+\t\t/* External EEM */\n+\t\treturn tf_insert_eem_entry((struct tf_session *)\n+\t\t\t\t\t (tfp->session->core_data),\n+\t\t\t\t\t tbl_scope_cb,\n+\t\t\t\t\t parms);\n+\t} else if (parms->mem == TF_MEM_INTERNAL) {\n+\t\t/* Internal EM */\n+\t\treturn tf_insert_em_internal_entry(tfp,\tparms);\n+\t}\n+\n+\treturn -EINVAL;\n }\n \n /** Delete EM hash entry API\n@@ -327,13 +446,16 @@ int tf_delete_em_entry(struct tf *tfp,\n \tif (tfp == NULL || parms == NULL)\n \t\treturn -EINVAL;\n \n-\ttbl_scope_cb =\n-\t\ttbl_scope_cb_find((struct tf_session *)tfp->session->core_data,\n-\t\t\t\t parms->tbl_scope_id);\n+\ttbl_scope_cb = tbl_scope_cb_find((struct tf_session *)\n+\t\t\t\t\t (tfp->session->core_data),\n+\t\t\t\t\t parms->tbl_scope_id);\n \tif (tbl_scope_cb == NULL)\n \t\treturn -EINVAL;\n \n-\treturn tf_delete_eem_entry(tfp, parms);\n+\tif (parms->mem == TF_MEM_EXTERNAL)\n+\t\treturn tf_delete_eem_entry(tfp, parms);\n+\telse\n+\t\treturn tf_delete_em_internal_entry(tfp, parms);\n }\n \n /** allocate identifier resource\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex 1eedd80e7..81ff7602f 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -44,44 +44,7 @@ enum tf_mem {\n };\n \n /**\n- * The size of the external action record (Wh+/Brd2)\n- *\n- * Currently set to 512.\n- *\n- * AR (16B) + encap (256B) + stats_ptrs (8) + resvd (8)\n- * + stats (16) = 304 aligned on a 16B boundary\n- *\n- * Theoretically, the size should be smaller. ~304B\n- */\n-#define TF_ACTION_RECORD_SZ 512\n-\n-/**\n- * External pool size\n- *\n- * Defines a single pool of external action records of\n- * fixed size. Currently, this is an index.\n- */\n-#define TF_EXT_POOL_ENTRY_SZ_BYTES 1\n-\n-/**\n- * External pool entry count\n- *\n- * Defines the number of entries in the external action pool\n- */\n-#define TF_EXT_POOL_ENTRY_CNT (1 * 1024)\n-\n-/**\n- * Number of external pools\n- */\n-#define TF_EXT_POOL_CNT_MAX 1\n-\n-/**\n- * External pool Id\n- */\n-#define TF_EXT_POOL_0 0 /**< matches TF_TBL_TYPE_EXT */\n-#define TF_EXT_POOL_1 1 /**< matches TF_TBL_TYPE_EXT_0 */\n-\n-/** EEM record AR helper\n+ * EEM record AR helper\n *\n * Helper to handle the Action Record Pointer in the EEM Record Entry.\n *\n@@ -109,7 +72,8 @@ enum tf_mem {\n */\n \n \n-/** Session Version defines\n+/**\n+ * Session Version defines\n *\n * The version controls the format of the tf_session and\n * tf_session_info structure. This is to assure upgrade between\n@@ -119,7 +83,8 @@ enum tf_mem {\n #define TF_SESSION_VER_MINOR 0 /**< Minor Version */\n #define TF_SESSION_VER_UPDATE 0 /**< Update Version */\n \n-/** Session Name\n+/**\n+ * Session Name\n *\n * Name of the TruFlow control channel interface. Expects\n * format to be RTE Name specific, i.e. rte_eth_dev_get_name_by_port()\n@@ -128,7 +93,8 @@ enum tf_mem {\n \n #define TF_FW_SESSION_ID_INVALID 0xFF /**< Invalid FW Session ID define */\n \n-/** Session Identifier\n+/**\n+ * Session Identifier\n *\n * Unique session identifier which includes PCIe bus info to\n * distinguish the PF and session info to identify the associated\n@@ -146,7 +112,8 @@ union tf_session_id {\n \t} internal;\n };\n \n-/** Session Version\n+/**\n+ * Session Version\n *\n * The version controls the format of the tf_session and\n * tf_session_info structure. This is to assure upgrade between\n@@ -160,8 +127,8 @@ struct tf_session_version {\n \tuint8_t update;\n };\n \n-/** Session supported device types\n- *\n+/**\n+ * Session supported device types\n */\n enum tf_device_type {\n \tTF_DEVICE_TYPE_WH = 0, /**< Whitney+ */\n@@ -171,6 +138,147 @@ enum tf_device_type {\n \tTF_DEVICE_TYPE_MAX /**< Maximum */\n };\n \n+/** Identifier resource types\n+ */\n+enum tf_identifier_type {\n+\t/** The L2 Context is returned from the L2 Ctxt TCAM lookup\n+\t * and can be used in WC TCAM or EM keys to virtualize further\n+\t * lookups.\n+\t */\n+\tTF_IDENT_TYPE_L2_CTXT,\n+\t/** The WC profile func is returned from the L2 Ctxt TCAM lookup\n+\t * to enable virtualization of the profile TCAM.\n+\t */\n+\tTF_IDENT_TYPE_PROF_FUNC,\n+\t/** The WC profile ID is included in the WC lookup key\n+\t * to enable virtualization of the WC TCAM hardware.\n+\t */\n+\tTF_IDENT_TYPE_WC_PROF,\n+\t/** The EM profile ID is included in the EM lookup key\n+\t * to enable virtualization of the EM hardware. (not required for SR2\n+\t * as it has table scope)\n+\t */\n+\tTF_IDENT_TYPE_EM_PROF,\n+\t/** The L2 func is included in the ILT result and from recycling to\n+\t * enable virtualization of further lookups.\n+\t */\n+\tTF_IDENT_TYPE_L2_FUNC,\n+\tTF_IDENT_TYPE_MAX\n+};\n+\n+/**\n+ * Enumeration of TruFlow table types. A table type is used to identify a\n+ * resource object.\n+ *\n+ * NOTE: The table type TF_TBL_TYPE_EXT is unique in that it is\n+ * the only table type that is connected with a table scope.\n+ */\n+enum tf_tbl_type {\n+\t/* Internal */\n+\n+\t/** Wh+/SR Action Record */\n+\tTF_TBL_TYPE_FULL_ACT_RECORD,\n+\t/** Wh+/SR/Th Multicast Groups */\n+\tTF_TBL_TYPE_MCAST_GROUPS,\n+\t/** Wh+/SR Action Encap 8 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_8B,\n+\t/** Wh+/SR Action Encap 16 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_16B,\n+\t/** Action Encap 32 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_32B,\n+\t/** Wh+/SR Action Encap 64 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_64B,\n+\t/** Action Source Properties SMAC */\n+\tTF_TBL_TYPE_ACT_SP_SMAC,\n+\t/** Wh+/SR Action Source Properties SMAC IPv4 */\n+\tTF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t/** Action Source Properties SMAC IPv6 */\n+\tTF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n+\t/** Wh+/SR Action Statistics 64 Bits */\n+\tTF_TBL_TYPE_ACT_STATS_64,\n+\t/** Wh+/SR Action Modify L4 Src Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_SPORT,\n+\t/** Wh+/SR Action Modify L4 Dest Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_DPORT,\n+\t/** Wh+/SR Action Modify IPv4 Source */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV4_SRC,\n+\t/** Wh+/SR Action _Modify L4 Dest Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV4_DEST,\n+\t/** Action Modify IPv6 Source */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV6_SRC,\n+\t/** Action Modify IPv6 Destination */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV6_DEST,\n+\t/** Meter Profiles */\n+\tTF_TBL_TYPE_METER_PROF,\n+\t/** Meter Instance */\n+\tTF_TBL_TYPE_METER_INST,\n+\t/** Mirror Config */\n+\tTF_TBL_TYPE_MIRROR_CONFIG,\n+\t/** UPAR */\n+\tTF_TBL_TYPE_UPAR,\n+\t/** SR2 Epoch 0 table */\n+\tTF_TBL_TYPE_EPOCH0,\n+\t/** SR2 Epoch 1 table */\n+\tTF_TBL_TYPE_EPOCH1,\n+\t/** SR2 Metadata */\n+\tTF_TBL_TYPE_METADATA,\n+\t/** SR2 CT State */\n+\tTF_TBL_TYPE_CT_STATE,\n+\t/** SR2 Range Profile */\n+\tTF_TBL_TYPE_RANGE_PROF,\n+\t/** SR2 Range Entry */\n+\tTF_TBL_TYPE_RANGE_ENTRY,\n+\t/** SR2 LAG Entry */\n+\tTF_TBL_TYPE_LAG,\n+\t/** SR2 VNIC/SVIF Table */\n+\tTF_TBL_TYPE_VNIC_SVIF,\n+\t/** Th/SR2 EM Flexible Key builder */\n+\tTF_TBL_TYPE_EM_FKB,\n+\t/** Th/SR2 WC Flexible Key builder */\n+\tTF_TBL_TYPE_WC_FKB,\n+\n+\t/* External */\n+\n+\t/** External table type - initially 1 poolsize entries.\n+\t * All External table types are associated with a table\n+\t * scope. Internal types are not.\n+\t */\n+\tTF_TBL_TYPE_EXT,\n+\tTF_TBL_TYPE_MAX\n+};\n+\n+/**\n+ * TCAM table type\n+ */\n+enum tf_tcam_tbl_type {\n+\t/** L2 Context TCAM */\n+\tTF_TCAM_TBL_TYPE_L2_CTXT_TCAM,\n+\t/** Profile TCAM */\n+\tTF_TCAM_TBL_TYPE_PROF_TCAM,\n+\t/** Wildcard TCAM */\n+\tTF_TCAM_TBL_TYPE_WC_TCAM,\n+\t/** Source Properties TCAM */\n+\tTF_TCAM_TBL_TYPE_SP_TCAM,\n+\t/** Connection Tracking Rule TCAM */\n+\tTF_TCAM_TBL_TYPE_CT_RULE_TCAM,\n+\t/** Virtual Edge Bridge TCAM */\n+\tTF_TCAM_TBL_TYPE_VEB_TCAM,\n+\tTF_TCAM_TBL_TYPE_MAX\n+};\n+\n+/**\n+ * EM Resources\n+ * These defines are provisioned during\n+ * tf_open_session()\n+ */\n+enum tf_em_tbl_type {\n+\t/** The number of internal EM records for the session */\n+\tTF_EM_TBL_TYPE_EM_RECORD,\n+\t/** The number of table scopes reequested */\n+\tTF_EM_TBL_TYPE_TBL_SCOPE,\n+\tTF_EM_TBL_TYPE_MAX\n+};\n+\n /** TruFlow Session Information\n *\n * Structure defining a TruFlow Session, also known as a Management\n@@ -309,6 +417,30 @@ struct tf_open_session_parms {\n \t * Device type is passed, one of Wh+, Brd2, Brd3, Brd4\n \t */\n \tenum tf_device_type device_type;\n+\t/** [in] Requested Identifier Resources\n+\t *\n+\t * The number of identifier resources requested for the session.\n+\t * The index used is tf_identifier_type.\n+\t */\n+\tuint16_t identifer_cnt[TF_IDENT_TYPE_MAX];\n+\t/** [in] Requested Index Table resource counts\n+\t *\n+\t * The number of index table resources requested for the session.\n+\t * The index used is tf_tbl_type.\n+\t */\n+\tuint16_t tbl_cnt[TF_TBL_TYPE_MAX];\n+\t/** [in] Requested TCAM Table resource counts\n+\t *\n+\t * The number of TCAM table resources requested for the session.\n+\t * The index used is tf_tcam_tbl_type.\n+\t */\n+\tuint16_t tcam_tbl_cnt[TF_TCAM_TBL_TYPE_MAX];\n+\t/** [in] Requested EM resource counts\n+\t *\n+\t * The number of internal EM table resources requested for the session\n+\t * The index used is tf_em_tbl_type.\n+\t */\n+\tuint16_t em_tbl_cnt[TF_EM_TBL_TYPE_MAX];\n };\n \n /**\n@@ -417,31 +549,6 @@ int tf_close_session(struct tf *tfp);\n *\n * @ref tf_free_identifier\n */\n-enum tf_identifier_type {\n-\t/** The L2 Context is returned from the L2 Ctxt TCAM lookup\n-\t * and can be used in WC TCAM or EM keys to virtualize further\n-\t * lookups.\n-\t */\n-\tTF_IDENT_TYPE_L2_CTXT,\n-\t/** The WC profile func is returned from the L2 Ctxt TCAM lookup\n-\t * to enable virtualization of the profile TCAM.\n-\t */\n-\tTF_IDENT_TYPE_PROF_FUNC,\n-\t/** The WC profile ID is included in the WC lookup key\n-\t * to enable virtualization of the WC TCAM hardware.\n-\t */\n-\tTF_IDENT_TYPE_WC_PROF,\n-\t/** The EM profile ID is included in the EM lookup key\n-\t * to enable virtualization of the EM hardware. (not required for Brd4\n-\t * as it has table scope)\n-\t */\n-\tTF_IDENT_TYPE_EM_PROF,\n-\t/** The L2 func is included in the ILT result and from recycling to\n-\t * enable virtualization of further lookups.\n-\t */\n-\tTF_IDENT_TYPE_L2_FUNC\n-};\n-\n /** tf_alloc_identifier parameter definition\n */\n struct tf_alloc_identifier_parms {\n@@ -631,19 +738,6 @@ int tf_alloc_tbl_scope(struct tf *tfp,\n int tf_free_tbl_scope(struct tf *tfp,\n \t\t struct tf_free_tbl_scope_parms *parms);\n \n-/**\n- * TCAM table type\n- */\n-enum tf_tcam_tbl_type {\n-\tTF_TCAM_TBL_TYPE_L2_CTXT_TCAM,\n-\tTF_TCAM_TBL_TYPE_PROF_TCAM,\n-\tTF_TCAM_TBL_TYPE_WC_TCAM,\n-\tTF_TCAM_TBL_TYPE_SP_TCAM,\n-\tTF_TCAM_TBL_TYPE_CT_RULE_TCAM,\n-\tTF_TCAM_TBL_TYPE_VEB_TCAM,\n-\tTF_TCAM_TBL_TYPE_MAX\n-\n-};\n \n /**\n * @page tcam TCAM Access\n@@ -813,7 +907,8 @@ struct tf_get_tcam_entry_parms {\n \tuint16_t result_sz_in_bits;\n };\n \n-/** get TCAM entry\n+/*\n+ * get TCAM entry\n *\n * Program a TCAM table entry for a TruFlow session.\n *\n@@ -824,7 +919,8 @@ struct tf_get_tcam_entry_parms {\n int tf_get_tcam_entry(struct tf *tfp,\n \t\t struct tf_get_tcam_entry_parms *parms);\n \n-/** tf_free_tcam_entry parameter definition\n+/*\n+ * tf_free_tcam_entry parameter definition\n */\n struct tf_free_tcam_entry_parms {\n \t/**\n@@ -845,8 +941,7 @@ struct tf_free_tcam_entry_parms {\n \tuint16_t ref_cnt;\n };\n \n-/** free TCAM entry\n- *\n+/*\n * Free TCAM entry.\n *\n * Firmware checks to ensure the TCAM entries are owned by the TruFlow\n@@ -873,84 +968,7 @@ int tf_free_tcam_entry(struct tf *tfp,\n */\n \n /**\n- * Enumeration of TruFlow table types. A table type is used to identify a\n- * resource object.\n- *\n- * NOTE: The table type TF_TBL_TYPE_EXT is unique in that it is\n- * the only table type that is connected with a table scope.\n- */\n-enum tf_tbl_type {\n-\t/** Wh+/Brd2 Action Record */\n-\tTF_TBL_TYPE_FULL_ACT_RECORD,\n-\t/** Multicast Groups */\n-\tTF_TBL_TYPE_MCAST_GROUPS,\n-\t/** Action Encap 8 Bytes */\n-\tTF_TBL_TYPE_ACT_ENCAP_8B,\n-\t/** Action Encap 16 Bytes */\n-\tTF_TBL_TYPE_ACT_ENCAP_16B,\n-\t/** Action Encap 64 Bytes */\n-\tTF_TBL_TYPE_ACT_ENCAP_32B,\n-\t/** Action Encap 64 Bytes */\n-\tTF_TBL_TYPE_ACT_ENCAP_64B,\n-\t/** Action Source Properties SMAC */\n-\tTF_TBL_TYPE_ACT_SP_SMAC,\n-\t/** Action Source Properties SMAC IPv4 */\n-\tTF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n-\t/** Action Source Properties SMAC IPv6 */\n-\tTF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n-\t/** Action Statistics 64 Bits */\n-\tTF_TBL_TYPE_ACT_STATS_64,\n-\t/** Action Modify L4 Src Port */\n-\tTF_TBL_TYPE_ACT_MODIFY_SPORT,\n-\t/** Action Modify L4 Dest Port */\n-\tTF_TBL_TYPE_ACT_MODIFY_DPORT,\n-\t/** Action Modify IPv4 Source */\n-\tTF_TBL_TYPE_ACT_MODIFY_IPV4_SRC,\n-\t/** Action _Modify L4 Dest Port */\n-\tTF_TBL_TYPE_ACT_MODIFY_IPV4_DEST,\n-\t/** Action Modify IPv6 Source */\n-\tTF_TBL_TYPE_ACT_MODIFY_IPV6_SRC,\n-\t/** Action Modify IPv6 Destination */\n-\tTF_TBL_TYPE_ACT_MODIFY_IPV6_DEST,\n-\n-\t/* HW */\n-\n-\t/** Meter Profiles */\n-\tTF_TBL_TYPE_METER_PROF,\n-\t/** Meter Instance */\n-\tTF_TBL_TYPE_METER_INST,\n-\t/** Mirror Config */\n-\tTF_TBL_TYPE_MIRROR_CONFIG,\n-\t/** UPAR */\n-\tTF_TBL_TYPE_UPAR,\n-\t/** Brd4 Epoch 0 table */\n-\tTF_TBL_TYPE_EPOCH0,\n-\t/** Brd4 Epoch 1 table */\n-\tTF_TBL_TYPE_EPOCH1,\n-\t/** Brd4 Metadata */\n-\tTF_TBL_TYPE_METADATA,\n-\t/** Brd4 CT State */\n-\tTF_TBL_TYPE_CT_STATE,\n-\t/** Brd4 Range Profile */\n-\tTF_TBL_TYPE_RANGE_PROF,\n-\t/** Brd4 Range Entry */\n-\tTF_TBL_TYPE_RANGE_ENTRY,\n-\t/** Brd4 LAG Entry */\n-\tTF_TBL_TYPE_LAG,\n-\t/** Brd4 only VNIC/SVIF Table */\n-\tTF_TBL_TYPE_VNIC_SVIF,\n-\n-\t/* External */\n-\n-\t/** External table type - initially 1 poolsize entries.\n-\t * All External table types are associated with a table\n-\t * scope. Internal types are not.\n-\t */\n-\tTF_TBL_TYPE_EXT,\n-\tTF_TBL_TYPE_MAX\n-};\n-\n-/** tf_alloc_tbl_entry parameter definition\n+ * tf_alloc_tbl_entry parameter definition\n */\n struct tf_alloc_tbl_entry_parms {\n \t/**\n@@ -993,7 +1011,8 @@ struct tf_alloc_tbl_entry_parms {\n \tuint32_t idx;\n };\n \n-/** allocate index table entries\n+/**\n+ * allocate index table entries\n *\n * Internal types:\n *\n@@ -1023,7 +1042,8 @@ struct tf_alloc_tbl_entry_parms {\n int tf_alloc_tbl_entry(struct tf *tfp,\n \t\t struct tf_alloc_tbl_entry_parms *parms);\n \n-/** tf_free_tbl_entry parameter definition\n+/**\n+ * tf_free_tbl_entry parameter definition\n */\n struct tf_free_tbl_entry_parms {\n \t/**\n@@ -1049,7 +1069,8 @@ struct tf_free_tbl_entry_parms {\n \tuint16_t ref_cnt;\n };\n \n-/** free index table entry\n+/**\n+ * free index table entry\n *\n * Used to free a previously allocated table entry.\n *\n@@ -1075,7 +1096,8 @@ struct tf_free_tbl_entry_parms {\n int tf_free_tbl_entry(struct tf *tfp,\n \t\t struct tf_free_tbl_entry_parms *parms);\n \n-/** tf_set_tbl_entry parameter definition\n+/**\n+ * tf_set_tbl_entry parameter definition\n */\n struct tf_set_tbl_entry_parms {\n \t/**\n@@ -1104,7 +1126,8 @@ struct tf_set_tbl_entry_parms {\n \tuint32_t idx;\n };\n \n-/** set index table entry\n+/**\n+ * set index table entry\n *\n * Used to insert an application programmed index table entry into a\n * previous allocated table location. A shadow copy of the table\n@@ -1115,7 +1138,8 @@ struct tf_set_tbl_entry_parms {\n int tf_set_tbl_entry(struct tf *tfp,\n \t\t struct tf_set_tbl_entry_parms *parms);\n \n-/** tf_get_tbl_entry parameter definition\n+/**\n+ * tf_get_tbl_entry parameter definition\n */\n struct tf_get_tbl_entry_parms {\n \t/**\n@@ -1140,7 +1164,8 @@ struct tf_get_tbl_entry_parms {\n \tuint32_t idx;\n };\n \n-/** get index table entry\n+/**\n+ * get index table entry\n *\n * Used to retrieve a previous set index table entry.\n *\n@@ -1163,7 +1188,8 @@ int tf_get_tbl_entry(struct tf *tfp,\n * @ref tf_search_em_entry\n *\n */\n-/** tf_insert_em_entry parameter definition\n+/**\n+ * tf_insert_em_entry parameter definition\n */\n struct tf_insert_em_entry_parms {\n \t/**\n@@ -1239,6 +1265,10 @@ struct tf_delete_em_entry_parms {\n \t * 2 element array with 2 ids. (Brd4 only)\n \t */\n \tuint16_t *epochs;\n+\t/**\n+\t * [out] The index of the entry\n+\t */\n+\tuint16_t index;\n \t/**\n \t * [in] structure containing flow delete handle information\n \t */\n@@ -1291,7 +1321,8 @@ struct tf_search_em_entry_parms {\n \tuint64_t flow_handle;\n };\n \n-/** insert em hash entry in internal table memory\n+/**\n+ * insert em hash entry in internal table memory\n *\n * Internal:\n *\n@@ -1328,7 +1359,8 @@ struct tf_search_em_entry_parms {\n int tf_insert_em_entry(struct tf *tfp,\n \t\t struct tf_insert_em_entry_parms *parms);\n \n-/** delete em hash entry table memory\n+/**\n+ * delete em hash entry table memory\n *\n * Internal:\n *\n@@ -1353,7 +1385,8 @@ int tf_insert_em_entry(struct tf *tfp,\n int tf_delete_em_entry(struct tf *tfp,\n \t\t struct tf_delete_em_entry_parms *parms);\n \n-/** search em hash entry table memory\n+/**\n+ * search em hash entry table memory\n *\n * Internal:\n \ndiff --git a/drivers/net/bnxt/tf_core/tf_em.c b/drivers/net/bnxt/tf_core/tf_em.c\nindex bd8e2ba8a..fd1797e39 100644\n--- a/drivers/net/bnxt/tf_core/tf_em.c\n+++ b/drivers/net/bnxt/tf_core/tf_em.c\n@@ -287,7 +287,7 @@ static int tf_em_entry_exists(struct tf_tbl_scope_cb *tbl_scope_cb,\n }\n \n static void tf_em_create_key_entry(struct tf_eem_entry_hdr *result,\n-\t\t\t\t uint8_t\t *in_key,\n+\t\t\t\t uint8_t *in_key,\n \t\t\t\t struct tf_eem_64b_entry *key_entry)\n {\n \tkey_entry->hdr.word1 = result->word1;\n@@ -308,7 +308,7 @@ static void tf_em_create_key_entry(struct tf_eem_entry_hdr *result,\n * EEXIST - Key does exist in table at \"index\" in table \"table\".\n * TF_ERR - Something went horribly wrong.\n */\n-static int tf_em_select_inject_table(struct tf_tbl_scope_cb\t*tbl_scope_cb,\n+static int tf_em_select_inject_table(struct tf_tbl_scope_cb *tbl_scope_cb,\n \t\t\t\t\t enum tf_dir dir,\n \t\t\t\t\t struct tf_eem_64b_entry *entry,\n \t\t\t\t\t uint32_t key0_hash,\n@@ -368,8 +368,8 @@ static int tf_em_select_inject_table(struct tf_tbl_scope_cb\t*tbl_scope_cb,\n * 0\n * TF_ERR_EM_DUP - key is already in table\n */\n-int tf_insert_eem_entry(struct tf_session\t *session,\n-\t\t\tstruct tf_tbl_scope_cb\t *tbl_scope_cb,\n+int tf_insert_eem_entry(struct tf_session *session,\n+\t\t\tstruct tf_tbl_scope_cb *tbl_scope_cb,\n \t\t\tstruct tf_insert_em_entry_parms *parms)\n {\n \tuint32_t\t mask;\n@@ -457,6 +457,96 @@ int tf_insert_eem_entry(struct tf_session\t *session,\n \treturn -EINVAL;\n }\n \n+/**\n+ * Insert EM internal entry API\n+ *\n+ * returns:\n+ * 0 - Success\n+ */\n+int tf_insert_em_internal_entry(struct tf *tfp,\n+\t\t\t\tstruct tf_insert_em_entry_parms *parms)\n+{\n+\tint rc;\n+\tuint32_t gfid;\n+\tuint16_t rptr_index = 0;\n+\tuint8_t rptr_entry = 0;\n+\tuint8_t num_of_entries = 0;\n+\tstruct tf_session *session =\n+\t\t(struct tf_session *)(tfp->session->core_data);\n+\tstruct stack *pool = &session->em_pool[parms->dir];\n+\tuint32_t index;\n+\n+\trc = stack_pop(pool, &index);\n+\n+\tif (rc != 0) {\n+\t\tPMD_DRV_LOG\n+\t\t (ERR,\n+\t\t \"dir:%d, EM entry index allocation failed\\n\",\n+\t\t parms->dir);\n+\t\treturn rc;\n+\t}\n+\n+\trptr_index = index * TF_SESSION_EM_ENTRY_SIZE;\n+\trc = tf_msg_insert_em_internal_entry(tfp,\n+\t\t\t\t\t parms,\n+\t\t\t\t\t &rptr_index,\n+\t\t\t\t\t &rptr_entry,\n+\t\t\t\t\t &num_of_entries);\n+\tif (rc != 0)\n+\t\treturn -1;\n+\n+\tPMD_DRV_LOG\n+\t\t (ERR,\n+\t\t \"Internal entry @ Index:%d rptr_index:0x%x rptr_entry:0x%x num_of_entries:%d\\n\",\n+\t\t index * TF_SESSION_EM_ENTRY_SIZE,\n+\t\t rptr_index,\n+\t\t rptr_entry,\n+\t\t num_of_entries);\n+\n+\tTF_SET_GFID(gfid,\n+\t\t ((rptr_index << TF_EM_INTERNAL_INDEX_SHIFT) |\n+\t\t rptr_entry),\n+\t\t 0); /* N/A for internal table */\n+\n+\tTF_SET_FLOW_ID(parms->flow_id,\n+\t\t gfid,\n+\t\t TF_GFID_TABLE_INTERNAL,\n+\t\t parms->dir);\n+\n+\tTF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle,\n+\t\t\t\t num_of_entries,\n+\t\t\t\t 0,\n+\t\t\t\t 0,\n+\t\t\t\t rptr_index,\n+\t\t\t\t rptr_entry,\n+\t\t\t\t 0);\n+\treturn 0;\n+}\n+\n+/** Delete EM internal entry API\n+ *\n+ * returns:\n+ * 0\n+ * -EINVAL\n+ */\n+int tf_delete_em_internal_entry(struct tf *tfp,\n+\t\t\t\tstruct tf_delete_em_entry_parms *parms)\n+{\n+\tint rc;\n+\tstruct tf_session *session =\n+\t\t(struct tf_session *)(tfp->session->core_data);\n+\tstruct stack *pool = &session->em_pool[parms->dir];\n+\n+\trc = tf_msg_delete_em_entry(tfp, parms);\n+\n+\t/* Return resource to pool */\n+\tif (rc == 0)\n+\t\tstack_push(pool, parms->index / TF_SESSION_EM_ENTRY_SIZE);\n+\n+\treturn rc;\n+}\n+\n+\n /** delete EEM hash entry API\n *\n * returns:\ndiff --git a/drivers/net/bnxt/tf_core/tf_em.h b/drivers/net/bnxt/tf_core/tf_em.h\nindex 8a3584fbd..c1805df73 100644\n--- a/drivers/net/bnxt/tf_core/tf_em.h\n+++ b/drivers/net/bnxt/tf_core/tf_em.h\n@@ -12,6 +12,20 @@\n #define TF_HW_EM_KEY_MAX_SIZE 52\n #define TF_EM_KEY_RECORD_SIZE 64\n \n+/*\n+ * Used to build GFID:\n+ *\n+ * 15 2 0\n+ * +--------------+--+\n+ * | Index |E |\n+ * +--------------+--+\n+ *\n+ * E = Entry (bucket inndex)\n+ */\n+#define TF_EM_INTERNAL_INDEX_SHIFT 2\n+#define TF_EM_INTERNAL_INDEX_MASK 0xFFFC\n+#define TF_EM_INTERNAL_ENTRY_MASK 0x3\n+\n /** EEM Entry header\n *\n */\n@@ -53,6 +67,17 @@ struct tf_eem_64b_entry {\n \tstruct tf_eem_entry_hdr hdr;\n };\n \n+/** EM Entry\n+ * Each EM entry is 512-bit (64-bytes) but ordered differently to\n+ * EEM.\n+ */\n+struct tf_em_64b_entry {\n+\t/** Header is 8 bytes long */\n+\tstruct tf_eem_entry_hdr hdr;\n+\t/** Key is 448 bits - 56 bytes */\n+\tuint8_t key[TF_EM_KEY_RECORD_SIZE - sizeof(struct tf_eem_entry_hdr)];\n+};\n+\n /**\n * Allocates EEM Table scope\n *\n@@ -106,9 +131,15 @@ int tf_insert_eem_entry(struct tf_session *session,\n \t\t\tstruct tf_tbl_scope_cb *tbl_scope_cb,\n \t\t\tstruct tf_insert_em_entry_parms *parms);\n \n+int tf_insert_em_internal_entry(struct tf *tfp,\n+\t\t\t\tstruct tf_insert_em_entry_parms *parms);\n+\n int tf_delete_eem_entry(struct tf *tfp,\n \t\t\tstruct tf_delete_em_entry_parms *parms);\n \n+int tf_delete_em_internal_entry(struct tf *tfp,\n+\t\t\t\tstruct tf_delete_em_entry_parms *parms);\n+\n void *tf_em_get_table_page(struct tf_tbl_scope_cb *tbl_scope_cb,\n \t\t\t enum tf_dir dir,\n \t\t\t uint32_t offset,\ndiff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\nindex 417a99cda..1491539ca 100644\n--- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\n+++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h\n@@ -90,6 +90,18 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\t TF_HASH_TYPE_FLOW_HANDLE_SFT);\t\t\t\\\n } while (0)\n \n+#define TF_GET_NUM_KEY_ENTRIES_FROM_FLOW_HANDLE(flow_handle,\t\t\\\n+\t\t\t\t\t num_key_entries)\t\t\\\n+\t(num_key_entries =\t\t\t\t\t\t\\\n+\t\t(((flow_handle) & TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK) >> \\\n+\t\t TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT))\t\t\\\n+\n+#define TF_GET_ENTRY_NUM_FROM_FLOW_HANDLE(flow_handle,\t\t\\\n+\t\t\t\t\t entry_num)\t\t\\\n+\t(entry_num =\t\t\t\t\t\t\\\n+\t\t(((flow_handle) & TF_ENTRY_NUM_FLOW_HANDLE_MASK) >> \\\n+\t\t TF_ENTRY_NUM_FLOW_HANDLE_SFT))\t\t\\\n+\n /*\n * 32 bit Flow ID handlers\n */\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c\nindex beecafdeb..554a8491d 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.c\n+++ b/drivers/net/bnxt/tf_core/tf_msg.c\n@@ -16,6 +16,7 @@\n #include \"tf_msg.h\"\n #include \"hsi_struct_def_dpdk.h\"\n #include \"hwrm_tf.h\"\n+#include \"tf_em.h\"\n \n /**\n * Endian converts min and max values from the HW response to the query\n@@ -1013,15 +1014,94 @@ int tf_msg_em_cfg(struct tf *tfp,\n \treturn rc;\n }\n \n+/**\n+ * Sends EM internal insert request to Firmware\n+ */\n+int tf_msg_insert_em_internal_entry(struct tf *tfp,\n+\t\t\t\tstruct tf_insert_em_entry_parms *em_parms,\n+\t\t\t\tuint16_t *rptr_index,\n+\t\t\t\tuint8_t *rptr_entry,\n+\t\t\t\tuint8_t *num_of_entries)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_em_internal_insert_input req = { 0 };\n+\tstruct tf_em_internal_insert_output resp = { 0 };\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\tstruct tf_em_64b_entry *em_result =\n+\t\t(struct tf_em_64b_entry *)em_parms->em_record;\n+\n+\treq.fw_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\tmemcpy(req.em_key, em_parms->key, ((em_parms->key_sz_in_bits + 7) / 8));\n+\treq.flags = tfp_cpu_to_le_16(em_parms->dir);\n+\treq.strength = (em_result->hdr.word1 & TF_LKUP_RECORD_STRENGTH_MASK) >>\n+\t\tTF_LKUP_RECORD_STRENGTH_SHIFT;\n+\treq.em_key_bitlen = em_parms->key_sz_in_bits;\n+\treq.action_ptr = em_result->hdr.pointer;\n+\treq.em_record_idx = *rptr_index;\n+\n+\tMSG_PREP(parms,\n+\t\t TF_KONG_MB,\n+\t\t HWRM_TF,\n+\t\t HWRM_TFT_EM_RULE_INSERT,\n+\t\t req,\n+\t\t resp);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t*rptr_entry = resp.rptr_entry;\n+\t*rptr_index = resp.rptr_index;\n+\t*num_of_entries = resp.num_of_entries;\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n+/**\n+ * Sends EM delete insert request to Firmware\n+ */\n+int tf_msg_delete_em_entry(struct tf *tfp,\n+\t\t\t struct tf_delete_em_entry_parms *em_parms)\n+{\n+\tint rc;\n+\tstruct tfp_send_msg_parms parms = { 0 };\n+\tstruct tf_em_internal_delete_input req = { 0 };\n+\tstruct tf_em_internal_delete_output resp = { 0 };\n+\tstruct tf_session *tfs =\n+\t\t(struct tf_session *)(tfp->session->core_data);\n+\n+\treq.tf_session_id =\n+\t\ttfp_cpu_to_le_32(tfs->session_id.internal.fw_session_id);\n+\treq.flags = tfp_cpu_to_le_16(em_parms->dir);\n+\treq.flow_handle = tfp_cpu_to_le_64(em_parms->flow_handle);\n+\n+\tMSG_PREP(parms,\n+\t\t TF_KONG_MB,\n+\t\t HWRM_TF,\n+\t\t HWRM_TFT_EM_RULE_DELETE,\n+\t\t req,\n+\t\tresp);\n+\n+\trc = tfp_send_msg_tunneled(tfp, &parms);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tem_parms->index = tfp_le_to_cpu_16(resp.em_index);\n+\n+\treturn tfp_le_to_cpu_32(parms.tf_resp_code);\n+}\n+\n /**\n * Sends EM operation request to Firmware\n */\n int tf_msg_em_op(struct tf *tfp,\n-\t\t int dir,\n-\t\t uint16_t op)\n+\t\t int dir,\n+\t\t uint16_t op)\n {\n \tint rc;\n-\tstruct hwrm_tf_ext_em_op_input req = {0};\n+\tstruct hwrm_tf_ext_em_op_input req = {0};\n \tstruct hwrm_tf_ext_em_op_output resp = {0};\n \tuint32_t flags;\n \tstruct tfp_send_msg_parms parms = { 0 };\ndiff --git a/drivers/net/bnxt/tf_core/tf_msg.h b/drivers/net/bnxt/tf_core/tf_msg.h\nindex 030d1881e..89f7370cc 100644\n--- a/drivers/net/bnxt/tf_core/tf_msg.h\n+++ b/drivers/net/bnxt/tf_core/tf_msg.h\n@@ -121,6 +121,19 @@ int tf_msg_session_sram_resc_flush(struct tf *tfp,\n \t\t\t\t enum tf_dir dir,\n \t\t\t\t struct tf_rm_entry *sram_entry);\n \n+/**\n+ * Sends EM internal insert request to Firmware\n+ */\n+int tf_msg_insert_em_internal_entry(struct tf *tfp,\n+\t\t\t\t struct tf_insert_em_entry_parms *params,\n+\t\t\t\t uint16_t *rptr_index,\n+\t\t\t\t uint8_t *rptr_entry,\n+\t\t\t\t uint8_t *num_of_entries);\n+/**\n+ * Sends EM internal delete request to Firmware\n+ */\n+int tf_msg_delete_em_entry(struct tf *tfp,\n+\t\t\t struct tf_delete_em_entry_parms *em_parms);\n /**\n * Sends EM mem register request to Firmware\n */\ndiff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h\nindex 50ef2d530..c9f4f8f04 100644\n--- a/drivers/net/bnxt/tf_core/tf_session.h\n+++ b/drivers/net/bnxt/tf_core/tf_session.h\n@@ -13,12 +13,25 @@\n #include \"tf_core.h\"\n #include \"tf_rm.h\"\n #include \"tf_tbl.h\"\n+#include \"stack.h\"\n \n /** Session defines\n */\n #define TF_SESSIONS_MAX\t 1 /** max # sessions */\n #define TF_SESSION_ID_INVALID 0xFFFFFFFF /** Invalid Session ID define */\n \n+/**\n+ * Number of EM entries. Static for now will be removed\n+ * when parameter added at a later date. At this stage we\n+ * are using fixed size entries so that each stack entry\n+ * represents 4 RT (f/n)blocks. So we take the total block\n+ * allocation for truflow and divide that by 4.\n+ */\n+#define TF_SESSION_TOTAL_FN_BLOCKS (1024 * 8) /* 8K blocks */\n+#define TF_SESSION_EM_ENTRY_SIZE 4 /* 4 blocks per entry */\n+#define TF_SESSION_EM_POOL_SIZE \\\n+\t(TF_SESSION_TOTAL_FN_BLOCKS / TF_SESSION_EM_ENTRY_SIZE)\n+\n /** Session\n *\n * Shared memory containing private TruFlow session information.\n@@ -289,6 +302,11 @@ struct tf_session {\n \n \t/** Table scope array */\n \tstruct tf_tbl_scope_cb tbl_scopes[TF_NUM_TBL_SCOPE];\n+\n+\t/**\n+\t * EM Pools\n+\t */\n+\tstruct stack em_pool[TF_DIR_MAX];\n };\n \n #endif /* _TF_SESSION_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_tbl.c b/drivers/net/bnxt/tf_core/tf_tbl.c\nindex d900c9c09..dda72c3d5 100644\n--- a/drivers/net/bnxt/tf_core/tf_tbl.c\n+++ b/drivers/net/bnxt/tf_core/tf_tbl.c\n@@ -156,7 +156,7 @@ tf_em_alloc_pg_tbl(struct tf_em_page_tbl *tp,\n \t\tif (tfp_calloc(&parms) != 0)\n \t\t\tgoto cleanup;\n \n-\t\ttp->pg_pa_tbl[i] = (uint64_t)(uintptr_t)parms.mem_pa;\n+\t\ttp->pg_pa_tbl[i] = (uintptr_t)parms.mem_pa;\n \t\ttp->pg_va_tbl[i] = parms.mem_va;\n \n \t\tmemset(tp->pg_va_tbl[i], 0, pg_size);\n@@ -792,7 +792,8 @@ tf_set_tbl_entry_internal(struct tf *tfp,\n \tindex = parms->idx;\n \n \tif (parms->type != TF_TBL_TYPE_FULL_ACT_RECORD &&\n-\t parms->type != TF_TBL_TYPE_ACT_SP_SMAC_IPV4) {\n+\t parms->type != TF_TBL_TYPE_ACT_SP_SMAC_IPV4 &&\n+\t parms->type != TF_TBL_TYPE_ACT_STATS_64) {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t \"dir:%d, Type not supported, type:%d\\n\",\n \t\t\t parms->dir,\n@@ -1179,7 +1180,8 @@ tf_alloc_tbl_entry_pool_internal(struct tf *tfp,\n \t parms->type != TF_TBL_TYPE_ACT_SP_SMAC_IPV4 &&\n \t parms->type != TF_TBL_TYPE_ACT_ENCAP_8B &&\n \t parms->type != TF_TBL_TYPE_ACT_ENCAP_16B &&\n-\t parms->type != TF_TBL_TYPE_ACT_ENCAP_64B) {\n+\t parms->type != TF_TBL_TYPE_ACT_ENCAP_64B &&\n+\t parms->type != TF_TBL_TYPE_ACT_STATS_64) {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t \"dir:%d, Type not supported, type:%d\\n\",\n \t\t\t parms->dir,\n@@ -1330,7 +1332,8 @@ tf_free_tbl_entry_pool_internal(struct tf *tfp,\n \t parms->type != TF_TBL_TYPE_ACT_SP_SMAC_IPV4 &&\n \t parms->type != TF_TBL_TYPE_ACT_ENCAP_8B &&\n \t parms->type != TF_TBL_TYPE_ACT_ENCAP_16B &&\n-\t parms->type != TF_TBL_TYPE_ACT_ENCAP_64B) {\n+\t parms->type != TF_TBL_TYPE_ACT_ENCAP_64B &&\n+\t parms->type != TF_TBL_TYPE_ACT_STATS_64) {\n \t\tPMD_DRV_LOG(ERR,\n \t\t\t \"dir:%d, Type not supported, type:%d\\n\",\n \t\t\t parms->dir,\n@@ -1801,3 +1804,91 @@ tf_free_tbl_entry(struct tf *tfp,\n \t\t\t rc);\n \treturn rc;\n }\n+\n+\n+static void\n+tf_dump_link_page_table(struct tf_em_page_tbl *tp,\n+\t\t\tstruct tf_em_page_tbl *tp_next)\n+{\n+\tuint64_t *pg_va;\n+\tuint32_t i;\n+\tuint32_t j;\n+\tuint32_t k = 0;\n+\n+\tprintf(\"pg_count:%d pg_size:0x%x\\n\",\n+\t tp->pg_count,\n+\t tp->pg_size);\n+\tfor (i = 0; i < tp->pg_count; i++) {\n+\t\tpg_va = tp->pg_va_tbl[i];\n+\t\tprintf(\"\\t%p\\n\", (void *)pg_va);\n+\t\tfor (j = 0; j < MAX_PAGE_PTRS(tp->pg_size); j++) {\n+\t\t\tprintf(\"\\t\\t%p\\n\", (void *)(uintptr_t)pg_va[j]);\n+\t\t\tif (((pg_va[j] & 0x7) ==\n+\t\t\t tfp_cpu_to_le_64(PTU_PTE_LAST |\n+\t\t\t\t\t PTU_PTE_VALID)))\n+\t\t\t\treturn;\n+\n+\t\t\tif (!(pg_va[j] & tfp_cpu_to_le_64(PTU_PTE_VALID))) {\n+\t\t\t\tprintf(\"** Invalid entry **\\n\");\n+\t\t\t\treturn;\n+\t\t\t}\n+\n+\t\t\tif (++k >= tp_next->pg_count) {\n+\t\t\t\tprintf(\"** Shouldn't get here **\\n\");\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+void tf_dump_dma(struct tf *tfp, uint32_t tbl_scope_id);\n+\n+void tf_dump_dma(struct tf *tfp, uint32_t tbl_scope_id)\n+{\n+\tstruct tf_session *session;\n+\tstruct tf_tbl_scope_cb *tbl_scope_cb;\n+\tstruct tf_em_page_tbl *tp;\n+\tstruct tf_em_page_tbl *tp_next;\n+\tstruct tf_em_table *tbl;\n+\tint i;\n+\tint j;\n+\tint dir;\n+\n+\tprintf(\"called %s\\n\", __func__);\n+\n+\t/* find session struct */\n+\tsession = (struct tf_session *)tfp->session->core_data;\n+\n+\t/* find control block for table scope */\n+\ttbl_scope_cb = tbl_scope_cb_find(session,\n+\t\t\t\t\t tbl_scope_id);\n+\tif (tbl_scope_cb == NULL)\n+\t\tPMD_DRV_LOG(ERR, \"No table scope\\n\");\n+\n+\tfor (dir = 0; dir < TF_DIR_MAX; dir++) {\n+\t\tprintf(\"Direction %s:\\n\", (dir == TF_DIR_RX ? \"Rx\" : \"Tx\"));\n+\n+\t\tfor (j = KEY0_TABLE; j < MAX_TABLE; j++) {\n+\t\t\ttbl = &tbl_scope_cb->em_ctx_info[dir].em_tables[j];\n+\t\t\tprintf\n+\t(\"Table: j:%d type:%d num_entries:%d entry_size:0x%x num_lvl:%d \",\n+\t\t\t j,\n+\t\t\t tbl->type,\n+\t\t\t tbl->num_entries,\n+\t\t\t tbl->entry_size,\n+\t\t\t tbl->num_lvl);\n+\t\t\tif (tbl->pg_tbl[0].pg_va_tbl &&\n+\t\t\t tbl->pg_tbl[0].pg_pa_tbl)\n+\t\t\t\tprintf(\"%p %p\\n\",\n+\t\t\t tbl->pg_tbl[0].pg_va_tbl[0],\n+\t\t\t (void *)(uintptr_t)tbl->pg_tbl[0].pg_pa_tbl[0]);\n+\t\t\tfor (i = 0; i < tbl->num_lvl - 1; i++) {\n+\t\t\t\tprintf(\"Level:%d\\n\", i);\n+\t\t\t\ttp = &tbl->pg_tbl[i];\n+\t\t\t\ttp_next = &tbl->pg_tbl[i + 1];\n+\t\t\t\ttf_dump_link_page_table(tp, tp_next);\n+\t\t\t}\n+\t\t\tprintf(\"\\n\");\n+\t\t}\n+\t}\n+}\ndiff --git a/drivers/net/bnxt/tf_core/tf_tbl.h b/drivers/net/bnxt/tf_core/tf_tbl.h\nindex bdc6288ee..7a5443678 100644\n--- a/drivers/net/bnxt/tf_core/tf_tbl.h\n+++ b/drivers/net/bnxt/tf_core/tf_tbl.h\n@@ -76,38 +76,51 @@ struct tf_tbl_scope_cb {\n \tuint32_t *ext_act_pool_mem[TF_DIR_MAX];\n };\n \n-/** Hardware Page sizes supported for EEM: 4K, 8K, 64K, 256K, 1M, 2M, 4M, 1G.\n- * Round-down other page sizes to the lower hardware page size supported.\n+/**\n+ * Hardware Page sizes supported for EEM:\n+ * 4K, 8K, 64K, 256K, 1M, 2M, 4M, 1G.\n+ *\n+ * Round-down other page sizes to the lower hardware page\n+ * size supported.\n */\n-#define BNXT_PAGE_SHIFT 22 /** 2M */\n+#define TF_EM_PAGE_SIZE_4K 12\n+#define TF_EM_PAGE_SIZE_8K 13\n+#define TF_EM_PAGE_SIZE_64K 16\n+#define TF_EM_PAGE_SIZE_256K 18\n+#define TF_EM_PAGE_SIZE_1M 20\n+#define TF_EM_PAGE_SIZE_2M 21\n+#define TF_EM_PAGE_SIZE_4M 22\n+#define TF_EM_PAGE_SIZE_1G 30\n+\n+/* Set page size */\n+#define BNXT_TF_PAGE_SIZE TF_EM_PAGE_SIZE_2M\n \n-#if (BNXT_PAGE_SHIFT < 12)\t\t\t\t/** < 4K >> 4K */\n-#define TF_EM_PAGE_SHIFT 12\n+#if (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_4K)\t/** 4K */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_4K\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K\n-#elif (BNXT_PAGE_SHIFT <= 13)\t\t\t/** 4K, 8K */\n-#define TF_EM_PAGE_SHIFT 13\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_8K)\t/** 8K */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_8K\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K\n-#elif (BNXT_PAGE_SHIFT < 16)\t\t\t\t/** 16K, 32K >> 8K */\n-#define TF_EM_PAGE_SHIFT 15\n-#define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_32K\n-#elif (BNXT_PAGE_SHIFT <= 17)\t\t\t/** 64K, 128K >> 64K */\n-#define TF_EM_PAGE_SHIFT 16\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_64K)\t/** 64K */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_64K\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K\n-#elif (BNXT_PAGE_SHIFT <= 19)\t\t\t/** 256K, 512K >> 256K */\n-#define TF_EM_PAGE_SHIFT 18\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_256K)\t/** 256K */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_256K\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K\n-#elif (BNXT_PAGE_SHIFT <= 21)\t\t\t/** 1M */\n-#define TF_EM_PAGE_SHIFT 20\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_1M)\t/** 1M */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_1M\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M\n-#elif (BNXT_PAGE_SHIFT <= 22)\t\t\t/** 2M, 4M */\n-#define TF_EM_PAGE_SHIFT 21\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_2M)\t/** 2M */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_2M\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M\n-#elif (BNXT_PAGE_SHIFT <= 29)\t\t\t/** 8M ... 512M >> 4M */\n-#define TF_EM_PAGE_SHIFT 22\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_4M)\t/** 4M */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_4M\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M\n-#else\t\t\t\t\t\t/** >= 1G >> 1G */\n-#define TF_EM_PAGE_SHIFT\t30\n+#elif (BNXT_TF_PAGE_SIZE == TF_EM_PAGE_SIZE_1G)\t/** 1G */\n+#define TF_EM_PAGE_SHIFT TF_EM_PAGE_SIZE_1G\n #define TF_EM_PAGE_SIZE_ENUM HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G\n+#else\n+#error \"Invalid Page Size specified. Please use a TF_EM_PAGE_SIZE_n define\"\n #endif\n \n #define TF_EM_PAGE_SIZE\t(1 << TF_EM_PAGE_SHIFT)\ndiff --git a/drivers/net/bnxt/tf_core/tfp.h b/drivers/net/bnxt/tf_core/tfp.h\nindex 8d5e94e1a..fe49b6304 100644\n--- a/drivers/net/bnxt/tf_core/tfp.h\n+++ b/drivers/net/bnxt/tf_core/tfp.h\n@@ -3,14 +3,23 @@\n * All rights reserved.\n */\n \n-/* This header file defines the Portability structures and APIs for\n+/*\n+ * This header file defines the Portability structures and APIs for\n * TruFlow.\n */\n \n #ifndef _TFP_H_\n #define _TFP_H_\n \n+#include <rte_config.h>\n #include <rte_spinlock.h>\n+#include <rte_log.h>\n+#include <rte_byteorder.h>\n+\n+/**\n+ * DPDK/Driver specific log level for the BNXT Eth driver.\n+ */\n+extern int bnxt_logtype_driver;\n \n /** Spinlock\n */\n@@ -18,13 +27,21 @@ struct tfp_spinlock_parms {\n \trte_spinlock_t slock;\n };\n \n+#define TFP_DRV_LOG_RAW(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, bnxt_logtype_driver, \"%s(): \" fmt, \\\n+\t\t__func__, ## args)\n+\n+#define TFP_DRV_LOG(level, fmt, args...) \\\n+\tTFP_DRV_LOG_RAW(level, fmt, ## args)\n+\n /**\n * @file\n *\n * TrueFlow Portability API Header File\n */\n \n-/** send message parameter definition\n+/**\n+ * send message parameter definition\n */\n struct tfp_send_msg_parms {\n \t/**\n@@ -62,7 +79,8 @@ struct tfp_send_msg_parms {\n \tuint32_t *resp_data;\n };\n \n-/** calloc parameter definition\n+/**\n+ * calloc parameter definition\n */\n struct tfp_calloc_parms {\n \t/**\n@@ -96,43 +114,15 @@ struct tfp_calloc_parms {\n * @ref tfp_send_msg_tunneled\n *\n * @ref tfp_calloc\n- * @ref tfp_free\n * @ref tfp_memcpy\n+ * @ref tfp_free\n *\n * @ref tfp_spinlock_init\n * @ref tfp_spinlock_lock\n * @ref tfp_spinlock_unlock\n *\n- * @ref tfp_cpu_to_le_16\n- * @ref tfp_le_to_cpu_16\n- * @ref tfp_cpu_to_le_32\n- * @ref tfp_le_to_cpu_32\n- * @ref tfp_cpu_to_le_64\n- * @ref tfp_le_to_cpu_64\n- * @ref tfp_cpu_to_be_16\n- * @ref tfp_be_to_cpu_16\n- * @ref tfp_cpu_to_be_32\n- * @ref tfp_be_to_cpu_32\n- * @ref tfp_cpu_to_be_64\n- * @ref tfp_be_to_cpu_64\n */\n \n-#define tfp_cpu_to_le_16(val) rte_cpu_to_le_16(val)\n-#define tfp_le_to_cpu_16(val) rte_le_to_cpu_16(val)\n-#define tfp_cpu_to_le_32(val) rte_cpu_to_le_32(val)\n-#define tfp_le_to_cpu_32(val) rte_le_to_cpu_32(val)\n-#define tfp_cpu_to_le_64(val) rte_cpu_to_le_64(val)\n-#define tfp_le_to_cpu_64(val) rte_le_to_cpu_64(val)\n-#define tfp_cpu_to_be_16(val) rte_cpu_to_be_16(val)\n-#define tfp_be_to_cpu_16(val) rte_be_to_cpu_16(val)\n-#define tfp_cpu_to_be_32(val) rte_cpu_to_be_32(val)\n-#define tfp_be_to_cpu_32(val) rte_be_to_cpu_32(val)\n-#define tfp_cpu_to_be_64(val) rte_cpu_to_be_64(val)\n-#define tfp_be_to_cpu_64(val) rte_be_to_cpu_64(val)\n-#define tfp_bswap_16(val) rte_bswap16(val)\n-#define tfp_bswap_32(val) rte_bswap32(val)\n-#define tfp_bswap_64(val) rte_bswap64(val)\n-\n /**\n * Provides communication capability from the TrueFlow API layer to\n * the TrueFlow firmware. The portability layer internally provides\n@@ -162,9 +152,24 @@ int tfp_send_msg_direct(struct tf *tfp,\n * -1 - Global error like not supported\n * -EINVAL - Parameter Error\n */\n-int tfp_send_msg_tunneled(struct tf *tfp,\n+int tfp_send_msg_tunneled(struct tf *tfp,\n \t\t\t struct tfp_send_msg_parms *parms);\n \n+/**\n+ * Sends OEM command message to Chimp\n+ *\n+ * [in] session, pointer to session handle\n+ * [in] max_flows, max number of flows requested\n+ *\n+ * Returns:\n+ * 0 - Success\n+ * -1 - Global error like not supported\n+ * -EINVAL - Parameter Error\n+ */\n+int\n+tfp_msg_hwrm_oem_cmd(struct tf *tfp,\n+\t\t uint32_t max_flows);\n+\n /**\n * Allocates zero'ed memory from the heap.\n *\n@@ -179,10 +184,58 @@ int tfp_send_msg_tunneled(struct tf *tfp,\n * -EINVAL - Parameter error\n */\n int tfp_calloc(struct tfp_calloc_parms *parms);\n-\n-void tfp_free(void *addr);\n void tfp_memcpy(void *dest, void *src, size_t n);\n+void tfp_free(void *addr);\n+\n void tfp_spinlock_init(struct tfp_spinlock_parms *slock);\n void tfp_spinlock_lock(struct tfp_spinlock_parms *slock);\n void tfp_spinlock_unlock(struct tfp_spinlock_parms *slock);\n+\n+/**\n+ * Lookup of the FID in the platform specific structure.\n+ *\n+ * [in] session\n+ * Pointer to session handle\n+ *\n+ * [out] fw_fid\n+ * Pointer to the fw_fid\n+ *\n+ * Returns:\n+ * 0 - Success\n+ * -EINVAL - Parameter error\n+ */\n+int tfp_get_fid(struct tf *tfp, uint16_t *fw_fid);\n+\n+\n+/*\n+ * @ref tfp_cpu_to_le_16\n+ * @ref tfp_le_to_cpu_16\n+ * @ref tfp_cpu_to_le_32\n+ * @ref tfp_le_to_cpu_32\n+ * @ref tfp_cpu_to_le_64\n+ * @ref tfp_le_to_cpu_64\n+ * @ref tfp_cpu_to_be_16\n+ * @ref tfp_be_to_cpu_16\n+ * @ref tfp_cpu_to_be_32\n+ * @ref tfp_be_to_cpu_32\n+ * @ref tfp_cpu_to_be_64\n+ * @ref tfp_be_to_cpu_64\n+ */\n+\n+#define tfp_cpu_to_le_16(val) rte_cpu_to_le_16(val)\n+#define tfp_le_to_cpu_16(val) rte_le_to_cpu_16(val)\n+#define tfp_cpu_to_le_32(val) rte_cpu_to_le_32(val)\n+#define tfp_le_to_cpu_32(val) rte_le_to_cpu_32(val)\n+#define tfp_cpu_to_le_64(val) rte_cpu_to_le_64(val)\n+#define tfp_le_to_cpu_64(val) rte_le_to_cpu_64(val)\n+#define tfp_cpu_to_be_16(val) rte_cpu_to_be_16(val)\n+#define tfp_be_to_cpu_16(val) rte_be_to_cpu_16(val)\n+#define tfp_cpu_to_be_32(val) rte_cpu_to_be_32(val)\n+#define tfp_be_to_cpu_32(val) rte_be_to_cpu_32(val)\n+#define tfp_cpu_to_be_64(val) rte_cpu_to_be_64(val)\n+#define tfp_be_to_cpu_64(val) rte_be_to_cpu_64(val)\n+#define tfp_bswap_16(val) rte_bswap16(val)\n+#define tfp_bswap_32(val) rte_bswap32(val)\n+#define tfp_bswap_64(val) rte_bswap64(val)\n+\n #endif /* _TFP_H_ */\n", "prefixes": [ "v5", "09/51" ] }