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GET /api/patches/7305/?format=api
{ "id": 7305, "url": "https://patches.dpdk.org/api/patches/7305/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443606022-13581-10-git-send-email-harry.van.haaren@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443606022-13581-10-git-send-email-harry.van.haaren@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443606022-13581-10-git-send-email-harry.van.haaren@intel.com", "date": "2015-09-30T09:40:20", "name": "[dpdk-dev,v2,09/11] i40e: add xstats() implementation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "18b2fc7765b0b8e35284344ce79f0014df787dba", "submitter": { "id": 317, "url": "https://patches.dpdk.org/api/people/317/?format=api", "name": "Van Haaren, Harry", "email": "harry.van.haaren@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443606022-13581-10-git-send-email-harry.van.haaren@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7305/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7305/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 56BFC8E87;\n\tWed, 30 Sep 2015 11:41:10 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id DCCF48E5A\n\tfor <dev@dpdk.org>; Wed, 30 Sep 2015 11:41:01 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 30 Sep 2015 02:41:01 -0700", "from sie-lab-212-222.ir.intel.com (HELO\n\tsilpixa00366884.ir.intel.com) ([10.237.212.222])\n\tby FMSMGA003.fm.intel.com with ESMTP; 30 Sep 2015 02:41:00 -0700" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,611,1437462000\"; d=\"scan'208\";a=\"571198055\"", "From": "Harry van Haaren <harry.van.haaren@intel.com>", "To": "dev@dpdk.org", "Date": "Wed, 30 Sep 2015 10:40:20 +0100", "Message-Id": "<1443606022-13581-10-git-send-email-harry.van.haaren@intel.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1443606022-13581-1-git-send-email-harry.van.haaren@intel.com>", "References": "<1443606022-13581-1-git-send-email-harry.van.haaren@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 09/11] i40e: add xstats() implementation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add xstats functions to i40e PMD, allowing extended statistics\nto be retrieved from the NIC and exposed to the DPDK.\n\nSigned-off-by: Harry van Haaren <harry.van.haaren@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 268 +++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 261 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 2dd9fdc..f2952b9 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -127,7 +127,10 @@ static int i40e_dev_set_link_up(struct rte_eth_dev *dev);\n static int i40e_dev_set_link_down(struct rte_eth_dev *dev);\n static void i40e_dev_stats_get(struct rte_eth_dev *dev,\n \t\t\t struct rte_eth_stats *stats);\n+static int i40e_dev_xstats_get(struct rte_eth_dev *dev,\n+\t\t\t struct rte_eth_xstats *xstats, unsigned n);\n static void i40e_dev_stats_reset(struct rte_eth_dev *dev);\n+static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);\n static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,\n \t\t\t\t\t uint16_t queue_id,\n \t\t\t\t\t uint8_t stat_idx,\n@@ -232,6 +235,8 @@ static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t uint32_t flags);\n static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \t\t\t\t\t struct timespec *timestamp);\n+static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);\n+\n \n static const struct rte_pci_id pci_id_i40e_map[] = {\n #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n@@ -252,7 +257,9 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.dev_set_link_down = i40e_dev_set_link_down,\n \t.link_update = i40e_dev_link_update,\n \t.stats_get = i40e_dev_stats_get,\n+\t.xstats_get = i40e_dev_xstats_get,\n \t.stats_reset = i40e_dev_stats_reset,\n+\t.xstats_reset = i40e_dev_xstats_reset,\n \t.queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,\n \t.dev_infos_get = i40e_dev_info_get,\n \t.vlan_filter_set = i40e_vlan_filter_set,\n@@ -291,6 +298,190 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,\n };\n \n+/* store statistics names and its offset in stats structure */\n+struct rte_i40e_xstats_name_off {\n+\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n+\tunsigned offset;\n+};\n+\n+static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {\n+\t{\"rx_bytes\", offsetof(struct i40e_eth_stats, rx_bytes)},\n+\t{\"rx_unicast_packets\", offsetof(struct i40e_eth_stats, rx_unicast)},\n+\t{\"rx_multicast_packets\", offsetof(struct i40e_eth_stats, rx_multicast)},\n+\t{\"rx_broadcast_packets\", offsetof(struct i40e_eth_stats, rx_broadcast)},\n+\t{\"rx_dropped\", offsetof(struct i40e_eth_stats, rx_discards)},\n+\t{\"rx_unknown_protocol_packets\", offsetof(struct i40e_eth_stats,\n+\t\trx_unknown_protocol)},\n+\t{\"tx_bytes\", offsetof(struct i40e_eth_stats, tx_bytes)},\n+\t{\"tx_unicast_packets\", offsetof(struct i40e_eth_stats, tx_unicast)},\n+\t{\"tx_multicast_packets\", offsetof(struct i40e_eth_stats, tx_multicast)},\n+\t{\"tx_broadcast_packets\", offsetof(struct i40e_eth_stats, tx_broadcast)},\n+\t{\"tx_dropped\", offsetof(struct i40e_eth_stats, tx_discards)},\n+\t{\"tx_errors\", offsetof(struct i40e_eth_stats, tx_errors)},\n+};\n+\n+static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {\n+\t{\"tx_link_down_dropped\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_dropped_link_down)},\n+\t{\"rx_crc_errors\", offsetof(struct i40e_hw_port_stats, crc_errors)},\n+\t{\"rx_illegal_bytes\", offsetof(struct i40e_hw_port_stats,\n+\t\tillegal_bytes)},\n+\t{\"rx_error_bytes\", offsetof(struct i40e_hw_port_stats, error_bytes)},\n+\t{\"mac_local_errors\", offsetof(struct i40e_hw_port_stats,\n+\t\tmac_local_faults)},\n+\t{\"mac_remote_errors\", offsetof(struct i40e_hw_port_stats,\n+\t\tmac_remote_faults)},\n+\t{\"rx_length_errors\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_length_errors)},\n+\t{\"tx_xon_packets\", offsetof(struct i40e_hw_port_stats, link_xon_tx)},\n+\t{\"rx_xon_packets\", offsetof(struct i40e_hw_port_stats, link_xon_rx)},\n+\t{\"tx_xoff_packets\", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},\n+\t{\"rx_xoff_packets\", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},\n+\t{\"rx_size_64_packets\", offsetof(struct i40e_hw_port_stats, rx_size_64)},\n+\t{\"rx_size_65_to_127_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_127)},\n+\t{\"rx_size_128_to_255_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_255)},\n+\t{\"rx_size_256_to_511_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_511)},\n+\t{\"rx_size_512_to_1023_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_1023)},\n+\t{\"rx_size_1024_to_1522_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_1522)},\n+\t{\"rx_size_1523_to_max_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_size_big)},\n+\t{\"rx_undersized_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_undersize)},\n+\t{\"rx_oversize_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_oversize)},\n+\t{\"rx_mac_short_dropped\", offsetof(struct i40e_hw_port_stats,\n+\t\tmac_short_packet_dropped)},\n+\t{\"rx_fragmented_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_fragments)},\n+\t{\"rx_jabber_packets\", offsetof(struct i40e_hw_port_stats, rx_jabber)},\n+\t{\"tx_size_64_packets\", offsetof(struct i40e_hw_port_stats, tx_size_64)},\n+\t{\"tx_size_65_to_127_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_127)},\n+\t{\"tx_size_128_to_255_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_255)},\n+\t{\"tx_size_256_to_511_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_511)},\n+\t{\"tx_size_512_to_1023_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_1023)},\n+\t{\"tx_size_1024_to_1522_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_1522)},\n+\t{\"tx_size_1523_to_max_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_size_big)},\n+\t{\"rx_flow_director_atr_match_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, fd_atr_match)},\n+\t{\"rx_flow_director_sb_match_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, fd_sb_match)},\n+\t{\"tx_low_power_idle_status\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_lpi_status)},\n+\t{\"rx_low_power_idle_status\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_lpi_status)},\n+\t{\"tx_low_power_idle_count\", offsetof(struct i40e_hw_port_stats,\n+\t\ttx_lpi_count)},\n+\t{\"rx_low_power_idle_count\", offsetof(struct i40e_hw_port_stats,\n+\t\trx_lpi_count)},\n+\n+\t/* priority_xon_rx[8] */\n+\t{\"tx_q0_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[0])},\n+\t{\"tx_q1_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[1])},\n+\t{\"tx_q2_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[2])},\n+\t{\"tx_q3_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[3])},\n+\t{\"tx_q4_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[4])},\n+\t{\"tx_q5_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[5])},\n+\t{\"tx_q6_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[6])},\n+\t{\"tx_q7_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_tx[7])},\n+\n+\t/* priority_xon_rx[8] */\n+\t{\"rx_q0_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[0])},\n+\t{\"rx_q1_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[1])},\n+\t{\"rx_q2_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[2])},\n+\t{\"rx_q3_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[3])},\n+\t{\"rx_q4_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[4])},\n+\t{\"rx_q5_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[5])},\n+\t{\"rx_q6_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[6])},\n+\t{\"rx_q7_xon_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xon_rx[7])},\n+\n+\t/* priority_xoff_tx[8] */\n+\t{\"tx_q0_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[0])},\n+\t{\"tx_q1_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[1])},\n+\t{\"tx_q2_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[2])},\n+\t{\"tx_q3_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[3])},\n+\t{\"tx_q4_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[4])},\n+\t{\"tx_q5_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[5])},\n+\t{\"tx_q6_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[6])},\n+\t{\"tx_q7_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_tx[7])},\n+\n+\t/* priority_xoff_rx[8] */\n+\t{\"rx_q0_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[0])},\n+\t{\"rx_q1_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[1])},\n+\t{\"rx_q2_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[2])},\n+\t{\"rx_q3_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[3])},\n+\t{\"rx_q4_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[4])},\n+\t{\"rx_q5_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[5])},\n+\t{\"rx_q6_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[6])},\n+\t{\"rx_q7_xoff_priority_packets\", offsetof(struct i40e_hw_port_stats,\n+\t\tpriority_xoff_rx[7])},\n+\n+\t/* priority_xon_2_xoff[8] */\n+\t{\"xx_q0_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[0])},\n+\t{\"xx_q1_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[1])},\n+\t{\"xx_q2_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[2])},\n+\t{\"xx_q3_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[3])},\n+\t{\"xx_q4_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[4])},\n+\t{\"xx_q5_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[5])},\n+\t{\"xx_q6_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[6])},\n+\t{\"xx_q7_xon_to_xoff_priority_packets\",\n+\t\toffsetof(struct i40e_hw_port_stats, priority_xon_2_xoff[7])},\n+};\n+\n+#define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \\\n+\t\tsizeof(rte_i40e_stats_strings[0]))\n+#define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \\\n+\t\tsizeof(rte_i40e_hw_port_strings[0]))\n+#define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS)\n+\n static struct eth_driver rte_i40e_pmd = {\n \t.pci_drv = {\n \t\t.name = \"rte_i40e_pmd\",\n@@ -1322,16 +1513,12 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi)\n \t\t vsi->vsi_id);\n }\n \n-/* Get all statistics of a port */\n static void\n-i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)\n {\n-\tuint32_t i;\n-\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n-\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tunsigned int i;\n \tstruct i40e_hw_port_stats *ns = &pf->stats; /* new stats */\n \tstruct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */\n-\n \t/* Get statistics of struct i40e_eth_stats */\n \ti40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),\n \t\t\t I40E_GLPRT_GORCL(hw->port),\n@@ -1508,8 +1695,21 @@ i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \n \tpf->offset_loaded = true;\n \n-\tif (pf->main_vsi)\n+\tif(pf->main_vsi)\n \t\ti40e_update_vsi_stats(pf->main_vsi);\n+}\n+\n+/* Get all statistics of a port */\n+static void\n+i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_hw_port_stats *ns = &pf->stats; /* new stats */\n+\tunsigned i;\n+\n+\t/* call read registers - updates values, now write them to struct */\n+\ti40e_read_stats_registers(pf, hw);\n \n \tstats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +\n \t\t\t\t\t\tns->eth.rx_broadcast;\n@@ -1599,6 +1799,60 @@ i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \tPMD_DRV_LOG(DEBUG, \"***************** PF stats end ********************\");\n }\n \n+static void\n+i40e_dev_xstats_reset(struct rte_eth_dev *dev)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct i40e_hw_port_stats *hw_stats = &pf->stats;\n+\n+\t/* The hw registers are cleared on read */\n+\tpf->offset_loaded = false;\n+\ti40e_read_stats_registers(pf, hw);\n+\n+\t/* reset software counters */\n+\tmemset(hw_stats, 0, sizeof(*hw_stats));\n+}\n+\n+static int\n+i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,\n+\t\t unsigned n)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tunsigned i, count = 0;\n+\tstruct i40e_hw_port_stats *hw_stats = &pf->stats;\n+\n+\tif(n < I40E_NB_XSTATS)\n+\t\treturn I40E_NB_XSTATS;\n+\n+\ti40e_read_stats_registers(pf, hw);\n+\n+\t/* Reset */\n+\tif(xstats == NULL)\n+\t\treturn 0;\n+\n+\t/* copy from i40e_eth_stats struct */\n+\tfor(i = 0; i < I40E_NB_ETH_XSTATS; i++) {\n+\t\tsnprintf(xstats[count].name, sizeof(xstats[count].name),\n+\t\t\t \"%s\", rte_i40e_stats_strings[i].name);\n+\t\txstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +\n+\t\t\trte_i40e_stats_strings[i].offset);\n+\t\tcount++;\n+\t}\n+\n+\t/* copy from i40e_hw_port struct */\n+\tfor(i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {\n+\t\tsnprintf(xstats[count].name, sizeof(xstats[count].name),\n+\t\t\t \"%s\", rte_i40e_hw_port_strings[i].name);\n+\t\txstats[count].value = *(uint64_t *)(((char *)hw_stats) +\n+\t\t\t\trte_i40e_hw_port_strings[i].offset);\n+\t\tcount++;\n+\t}\n+\n+\treturn I40E_NB_XSTATS;\n+}\n+\n /* Reset the statistics */\n static void\n i40e_dev_stats_reset(struct rte_eth_dev *dev)\n", "prefixes": [ "dpdk-dev", "v2", "09/11" ] }