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GET /api/patches/72010/?format=api
{ "id": 72010, "url": "https://patches.dpdk.org/api/patches/72010/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1592901667-12161-3-git-send-email-shirik@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1592901667-12161-3-git-send-email-shirik@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1592901667-12161-3-git-send-email-shirik@mellanox.com", "date": "2020-06-23T08:41:06", "name": "[2/3] net/mlx5: add default miss action to flow engine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fa95e69c24ad1a090a7c9cab624fe0142ac6c39c", "submitter": { "id": 1575, "url": "https://patches.dpdk.org/api/people/1575/?format=api", "name": "Shiri Kuzin", "email": "shirik@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1592901667-12161-3-git-send-email-shirik@mellanox.com/mbox/", "series": [ { "id": 10562, "url": "https://patches.dpdk.org/api/series/10562/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10562", "date": "2020-06-23T08:41:04", "name": "mlx5: LACP handling for bonded devices", "version": 1, "mbox": "https://patches.dpdk.org/series/10562/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/72010/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/72010/checks/", "tags": {}, "related": [], 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b=USTtAthRKX5LOXtE2mHcBMlPq/1PDXNsh0NUL9s0RjpIyweFn1TpQH/LKezmZKOVLChXRBKd6wO9Irrk5fbtDE4DJTIxZCfuyqAda2uvy6GH8xi64FO3Ij0AoO4uCe/7G/U9aU3ionxZXTwwAZBId3M1seaM/ZyMSHYTy/nV/VE=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=mellanox.com;", "From": "Shiri Kuzin <shirik@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com,\n\tviacheslavo@mellanox.com", "Date": "Tue, 23 Jun 2020 11:41:06 +0300", "Message-Id": "<1592901667-12161-3-git-send-email-shirik@mellanox.com>", "X-Mailer": [ "git-send-email 1.8.3.1", "git-send-email 1.8.3.1" ], "In-Reply-To": "<1592901667-12161-1-git-send-email-shirik@mellanox.com>", "References": "<1592901667-12161-1-git-send-email-shirik@mellanox.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "AM0PR04CA0088.eurprd04.prod.outlook.com\n (2603:10a6:208:be::29) To AM0PR0502MB3874.eurprd05.prod.outlook.com\n (2603:10a6:208:1a::29)", "MIME-Version": "1.0", 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6wNBPCzuIpCy9DWGfAr8L5dourvrY/WgKL/wFKrRkfPlOvGH/GspDo9ly1qABaAOQWBxnubkuGAGEwOSiV3xf+jirgoU65UZSaHhckkDBbfq6lbmmdBJLcYGkbybDE3MOPLBEEGgQ5jDbFTHIpMinU0YseqHYDyvqc9PTdJQH249IXIGgNNkVwOn3CsxxFT1HIA60WMVvh+nQmKZHqg2uaT3z5+XQNgKrppByuLVqLXyJAE4ikE6VDQbcakF3kQOtAfThCIlsmw/7GB3IkNLmFM19rkdjGgh1Y93KsqjMTS1Kvr+dCNQZbpYVLWuuRIEc3jD3TxpeOc/WRjvBI3g0/cng7uaSs2hcqTsq2AhnHx98wXmGEqTZq3CedjmOgC1sOoQ5zBwv0dLRkdd3BqIEaYOoyGPwuUkBDdcBsadc37sa416kdEJC9gbNDCs57RXS/Cbe1qghssaOlJa2b4+YkeJgN5PQFAsmhAjjr2VqZo=", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 64ca3863-e64f-4532-ea96-08d8175138d8", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Jun 2020 08:41:28.8323 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 12/M4Rudh7oTLBzRb0RSePd30Mio0TsVDEvzY4heMxX2NLLIsH2a5g70chTynjxJod07AwLuMKv4ydGLi3MNBQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM0PR0502MB4036", "Subject": "[dpdk-dev] [PATCH 2/3] net/mlx5: add default miss action to flow\n\tengine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The new action is an internal mlx5 action that will call\nthe rdma-core function MLX5DV_FLOW_ACTION_DEFAULT_MISS.\n\nThe default miss action will be used when a bond is\nconfigured to allow traffic related to the bond to\nbe managed in the kernel.\n\nSigned-off-by: Shiri Kuzin <shirik@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 9 +++\n drivers/net/mlx5/mlx5_flow.c | 92 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 11 +++-\n drivers/net/mlx5/mlx5_flow_dv.c | 127 +++++++++++++++++++++++++++++++++++++---\n 4 files changed, 231 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8a09ebc..93bde5a 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -451,6 +451,12 @@ struct mlx5_flow_counter_mng {\n \tLIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;\n };\n \n+/* Default miss action resource structure. */\n+struct mlx5_flow_default_miss_resource {\n+\tvoid *action; /* Pointer to the rdma-core action. */\n+\trte_atomic32_t refcnt; /* Default miss action reference counter. */\n+};\n+\n #define MLX5_AGE_EVENT_NEW\t\t1\n #define MLX5_AGE_TRIGGER\t\t2\n #define MLX5_AGE_SET(age_info, BIT) \\\n@@ -559,6 +565,8 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t port_id_action_list; /* List of port ID actions. */\n \tuint32_t push_vlan_action_list; /* List of push VLAN actions. */\n \tstruct mlx5_flow_counter_mng cmng; /* Counters management structure. */\n+\tstruct mlx5_flow_default_miss_resource default_miss;\n+\t/* Default miss action resource structure. */\n \tstruct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];\n \t/* Memory Pool for mlx5 flow resources. */\n \tstruct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */\n@@ -872,6 +880,7 @@ int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,\n int mlx5_ctrl_flow(struct rte_eth_dev *dev,\n \t\t struct rte_flow_item_eth *eth_spec,\n \t\t struct rte_flow_item_eth *eth_mask);\n+int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);\n struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);\n int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);\n void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 3a48b89..4700ec1 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1238,6 +1238,43 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n }\n \n /*\n+ * Validate the default miss action.\n+ *\n+ * @param[in] action_flags\n+ * Bit-fields that holds the actions detected until now.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_validate_action_default_miss(uint64_t action_flags,\n+\t\t\t\tconst struct rte_flow_attr *attr,\n+\t\t\t\tstruct rte_flow_error *error)\n+{\n+\tif (action_flags & MLX5_FLOW_FATE_ACTIONS)\n+\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, NULL,\n+\t\t\t\t\t \"can't have 2 fate actions in\"\n+\t\t\t\t\t \" same flow\");\n+\tif (attr->egress)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL,\n+\t\t\t\t\t \"default miss action not supported \"\n+\t\t\t\t\t \"for egress\");\n+\tif (attr->group)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,\n+\t\t\t\t\t \"only group 0 is supported\");\n+\tif (attr->transfer)\n+\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,\n+\t\t\t\t\t NULL, \"transfer is not supported\");\n+\treturn 0;\n+}\n+\n+/*\n * Validate the count action.\n *\n * @param[in] dev\n@@ -4984,6 +5021,61 @@ struct rte_flow *\n }\n \n /**\n+ * Create default miss flow rule matching lacp traffic\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param eth_spec\n+ * An Ethernet flow spec to apply.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+mlx5_flow_lacp_miss(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\t/*\n+\t * The LACP matching is done by only using ether type since using\n+\t * a multicast dst mac causes kernel to give low priority to this flow.\n+\t */\n+\tstatic const struct rte_flow_item_eth lacp_spec = {\n+\t\t.type = RTE_BE16(0x8809),\n+\t};\n+\tstatic const struct rte_flow_item_eth lacp_mask = {\n+\t\t.type = 0xffff,\n+\t};\n+\tconst struct rte_flow_attr attr = {\n+\t\t.ingress = 1,\n+\t};\n+\tstruct rte_flow_item items[] = {\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ITEM_TYPE_ETH,\n+\t\t\t.spec = &lacp_spec,\n+\t\t\t.mask = &lacp_mask,\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n+\t\t},\n+\t};\n+\tstruct rte_flow_action actions[] = {\n+\t\t{\n+\t\t\t.type = MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,\n+\t\t},\n+\t\t{\n+\t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n+\t\t},\n+\t};\n+\tstruct rte_flow_error error;\n+\tuint32_t flow_idx = flow_list_create(dev, &priv->ctrl_flows,\n+\t\t\t\t&attr, items, actions, false, &error);\n+\n+\tif (!flow_idx)\n+\t\treturn -rte_errno;\n+\treturn 0;\n+}\n+\n+/**\n * Destroy a flow.\n *\n * @see rte_flow_destroy()\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 2c96677..50ec741 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -43,6 +43,7 @@ enum mlx5_rte_flow_action_type {\n \tMLX5_RTE_FLOW_ACTION_TYPE_TAG,\n \tMLX5_RTE_FLOW_ACTION_TYPE_MARK,\n \tMLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,\n+\tMLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,\n };\n \n /* Matches on selected register. */\n@@ -200,10 +201,12 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)\n #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)\n #define MLX5_FLOW_ACTION_AGE (1ull << 34)\n+#define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)\n \n #define MLX5_FLOW_FATE_ACTIONS \\\n \t(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \\\n-\t MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)\n+\t MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \\\n+\t MLX5_FLOW_ACTION_DEFAULT_MISS)\n \n #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \\\n \t(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \\\n@@ -364,6 +367,7 @@ enum mlx5_flow_fate_type {\n \tMLX5_FLOW_FATE_JUMP,\n \tMLX5_FLOW_FATE_PORT_ID,\n \tMLX5_FLOW_FATE_DROP,\n+\tMLX5_FLOW_FATE_DEFAULT_MISS,\n \tMLX5_FLOW_FATE_MAX,\n };\n \n@@ -545,6 +549,8 @@ struct mlx5_flow_handle {\n \t\t/**< Index to port ID action resource. */\n \t\tuint32_t rix_fate;\n \t\t/**< Generic value indicates the fate action. */\n+\t\tuint32_t rix_default_fate;\n+\t\t/**< Indicates default miss fate action. */\n \t};\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \tstruct mlx5_flow_handle_dv dvh;\n@@ -946,6 +952,9 @@ int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,\n \t\t\t\t const struct rte_flow_attr *attr,\n \t\t\t\t uint64_t item_flags,\n \t\t\t\t struct rte_flow_error *error);\n+int mlx5_flow_validate_action_default_miss(uint64_t action_flags,\n+\t\t\t\tconst struct rte_flow_attr *attr,\n+\t\t\t\tstruct rte_flow_error *error);\n int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,\n \t\t\t\t const struct rte_flow_attr *attributes,\n \t\t\t\t struct rte_flow_error *error);\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex f174009..d1eb65b 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -79,6 +79,9 @@\n flow_dv_tbl_resource_release(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_flow_tbl_resource *tbl);\n \n+static int\n+flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);\n+\n /**\n * Initialize flow attributes structure according to flow items' types.\n *\n@@ -2676,6 +2679,42 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n+ * Find existing default miss resource or create and register a new one.\n+ *\n+ * @param[in, out] dev\n+ * Pointer to rte_eth_dev structure.\n+ * @param[out] error\n+ * pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success otherwise -errno and errno is set.\n+ */\n+static int\n+flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,\n+\t\tstruct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_flow_default_miss_resource *cache_resource =\n+\t\t\t&sh->default_miss;\n+\tint cnt = rte_atomic32_read(&cache_resource->refcnt);\n+\n+\tif (!cnt) {\n+\t\tMLX5_ASSERT(cache_resource->action);\n+\t\tcache_resource->action =\n+\t\tmlx5_glue->dr_create_flow_action_default_miss();\n+\t\tif (!cache_resource->action)\n+\t\t\treturn rte_flow_error_set(error, ENOMEM,\n+\t\t\t\t\tRTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\"cannot create default miss action\");\n+\t\tDRV_LOG(DEBUG, \"new default miss resource %p: refcnt %d++\",\n+\t\t\t\t(void *)cache_resource->action, cnt);\n+\t}\n+\trte_atomic32_inc(&cache_resource->refcnt);\n+\treturn 0;\n+}\n+\n+/**\n * Find existing table port ID resource or create and register a new one.\n *\n * @param[in, out] dev\n@@ -5249,6 +5288,15 @@ struct field_modify_info modify_tcp[] = {\n \t\t\taction_flags |= MLX5_FLOW_ACTION_RSS;\n \t\t\t++actions_n;\n \t\t\tbreak;\n+\t\tcase MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:\n+\t\t\tret =\n+\t\t\tmlx5_flow_validate_action_default_miss(action_flags,\n+\t\t\t\t\tattr, error);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t\taction_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;\n+\t\t\t++actions_n;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n \t\t\tret = flow_dv_validate_action_count(dev, error);\n \t\t\tif (ret < 0)\n@@ -8212,6 +8260,11 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t\treturn -rte_errno;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_SET_TAG;\n \t\t\tbreak;\n+\t\tcase MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:\n+\t\t\taction_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;\n+\t\t\tdev_flow->handle->fate_action =\n+\t\t\t\t\tMLX5_FLOW_FATE_DEFAULT_MISS;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_METER:\n \t\t\tmtr = actions->conf;\n \t\t\tif (!flow->meter) {\n@@ -8304,7 +8357,11 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tflow_dv_translate_item_eth(match_mask, match_value,\n \t\t\t\t\t\t items, tunnel,\n \t\t\t\t\t\t dev_flow->dv.group);\n-\t\t\tmatcher.priority = MLX5_PRIORITY_MAP_L2;\n+\t\t\tmatcher.priority = action_flags &\n+\t\t\t\t\tMLX5_FLOW_ACTION_DEFAULT_MISS &&\n+\t\t\t\t\t!dev_flow->external ?\n+\t\t\t\t\tMLX5_PRIORITY_MAP_L3 :\n+\t\t\t\t\tMLX5_PRIORITY_MAP_L2;\n \t\t\tlast_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :\n \t\t\t\t\t MLX5_FLOW_LAYER_OUTER_L2;\n \t\t\tbreak;\n@@ -8604,7 +8661,19 @@ struct field_modify_info modify_tcp[] = {\n \t\t\t}\n \t\t\tdh->rix_hrxq = hrxq_idx;\n \t\t\tdv->actions[n++] = hrxq->action;\n+\t\t} else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {\n+\t\t\tif (flow_dv_default_miss_resource_register\n+\t\t\t\t\t(dev, error)) {\n+\t\t\t\trte_flow_error_set\n+\t\t\t\t\t(error, rte_errno,\n+\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t \"cannot create default miss resource\");\n+\t\t\t\tgoto error_default_miss;\n+\t\t\t}\n+\t\t\tdh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;\n+\t\t\tdv->actions[n++] = priv->sh->default_miss.action;\n \t\t}\n+\n \t\tdh->ib_flow =\n \t\t\tmlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,\n \t\t\t\t\t\t (void *)&dv->value, n,\n@@ -8629,6 +8698,9 @@ struct field_modify_info modify_tcp[] = {\n \t}\n \treturn 0;\n error:\n+\tif (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)\n+\t\tflow_dv_default_miss_resource_release(dev);\n+error_default_miss:\n \terr = rte_errno; /* Save rte_errno before cleanup. */\n \tSILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,\n \t\t handle_idx, dh, next) {\n@@ -8766,6 +8838,36 @@ struct field_modify_info modify_tcp[] = {\n }\n \n /**\n+ * Release a default miss resource.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @return\n+ * 1 while a reference on it exists, 0 when freed.\n+ */\n+static int\n+flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_flow_default_miss_resource *cache_resource =\n+\t\t\t&sh->default_miss;\n+\n+\tMLX5_ASSERT(cache_resource->action);\n+\tDRV_LOG(DEBUG, \"default miss resource %p: refcnt %d--\",\n+\t\t\t(void *)cache_resource->action,\n+\t\t\trte_atomic32_read(&cache_resource->refcnt));\n+\tif (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {\n+\t\tclaim_zero(mlx5_glue->destroy_flow_action\n+\t\t\t\t(cache_resource->action));\n+\t\tDRV_LOG(DEBUG, \"default miss resource %p: removed\",\n+\t\t\t\t(void *)cache_resource->action);\n+\t\treturn 0;\n+\t}\n+\treturn 1;\n+}\n+\n+/**\n * Release a modify-header resource.\n *\n * @param handle\n@@ -8892,16 +8994,26 @@ struct field_modify_info modify_tcp[] = {\n {\n \tif (!handle->rix_fate)\n \t\treturn;\n-\tif (handle->fate_action == MLX5_FLOW_FATE_DROP)\n+\tswitch (handle->fate_action) {\n+\tcase MLX5_FLOW_FATE_DROP:\n \t\tmlx5_hrxq_drop_release(dev);\n-\telse if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)\n+\t\tbreak;\n+\tcase MLX5_FLOW_FATE_QUEUE:\n \t\tmlx5_hrxq_release(dev, handle->rix_hrxq);\n-\telse if (handle->fate_action == MLX5_FLOW_FATE_JUMP)\n+\t\tbreak;\n+\tcase MLX5_FLOW_FATE_JUMP:\n \t\tflow_dv_jump_tbl_resource_release(dev, handle);\n-\telse if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)\n+\t\tbreak;\n+\tcase MLX5_FLOW_FATE_PORT_ID:\n \t\tflow_dv_port_id_action_resource_release(dev, handle);\n-\telse\n+\t\tbreak;\n+\tcase MLX5_FLOW_FATE_DEFAULT_MISS:\n+\t\tflow_dv_default_miss_resource_release(dev);\n+\t\tbreak;\n+\tdefault:\n \t\tDRV_LOG(DEBUG, \"Incorrect fate action:%d\", handle->fate_action);\n+\t\tbreak;\n+\t}\n \thandle->rix_fate = 0;\n }\n \n@@ -8934,7 +9046,8 @@ struct field_modify_info modify_tcp[] = {\n \t\t\tdh->ib_flow = NULL;\n \t\t}\n \t\tif (dh->fate_action == MLX5_FLOW_FATE_DROP ||\n-\t\t dh->fate_action == MLX5_FLOW_FATE_QUEUE)\n+\t\t dh->fate_action == MLX5_FLOW_FATE_QUEUE ||\n+\t\t dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)\n \t\t\tflow_dv_fate_resource_release(dev, dh);\n \t\tif (dh->vf_vlan.tag && dh->vf_vlan.created)\n \t\t\tmlx5_vlan_vmwa_release(dev, &dh->vf_vlan);\n", "prefixes": [ "2/3" ] }