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GET /api/patches/7161/?format=api
{ "id": 7161, "url": "https://patches.dpdk.org/api/patches/7161/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1443132870-11032-1-git-send-email-rkerur@gmail.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1443132870-11032-1-git-send-email-rkerur@gmail.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1443132870-11032-1-git-send-email-rkerur@gmail.com", "date": "2015-09-24T22:14:30", "name": "[dpdk-dev,v1] Add support for I217 and I218 Intel 1G chipsets.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "13759aa2c52aaad337821c70e1e60c6ff796516c", "submitter": { "id": 134, "url": "https://patches.dpdk.org/api/people/134/?format=api", "name": "Ravi Kerur", "email": "rkerur@gmail.com" }, "delegate": { "id": 10, "url": "https://patches.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1443132870-11032-1-git-send-email-rkerur@gmail.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/7161/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/7161/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 5819A8E73;\n\tFri, 25 Sep 2015 00:14:30 +0200 (CEST)", "from mail-pa0-f51.google.com (mail-pa0-f51.google.com\n\t[209.85.220.51]) by dpdk.org (Postfix) with ESMTP id 1C06D58EF\n\tfor <dev@dpdk.org>; Fri, 25 Sep 2015 00:14:29 +0200 (CEST)", "by pacgz1 with SMTP id gz1so2277241pac.3\n\tfor <dev@dpdk.org>; Thu, 24 Sep 2015 15:14:28 -0700 (PDT)", "from user-PC.hsd1.ca.comcast.net\n\t(c-24-4-155-27.hsd1.ca.comcast.net. [24.4.155.27])\n\tby smtp.gmail.com with ESMTPSA id\n\tfk8sm276798pab.33.2015.09.24.15.14.27\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 24 Sep 2015 15:14:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Ft3P+fcQMunN6ZE9ctxXPBRqIln62+4E7ko8DkDi0CY=;\n\tb=OeDMpa7hhaHuylkpj1EsA7G9Qqv1LUyNyoQAhPvXKmhZ/vbVXmX3lV1g6KOAPfL2uo\n\ttW3kyqbmo4IA6pg58dqwJHWJkt7vvBXx7mfPTTquHqIL5Rz0Wt+Iuj9sCFyM/fn/Vg5+\n\thm6/A88Xb+PdM1qrIw/rSnYq4BSMhity5AdbVFbOoceSkRwXMvy5/DPmWPipijAd/W1T\n\tKe35xYR8yulxTx+4kTO5q9+DEOUbnsljolRzH1rXBu5u9lJhFqV6DG1Px9LcGBFY0LCV\n\tCOog4uAJfcGSPJ75efaKiImPsdT2RO/skiDHjYEc5c5x+xrSlNZy6mJCzVPWCTZ51+r5\n\tpHnw==", "X-Received": "by 10.68.68.205 with SMTP id y13mr2433725pbt.99.1443132868523;\n\tThu, 24 Sep 2015 15:14:28 -0700 (PDT)", "From": "Ravi Kerur <rkerur@gmail.com>", "To": "dev@dpdk.org", "Date": "Thu, 24 Sep 2015 15:14:30 -0700", "Message-Id": "<1443132870-11032-1-git-send-email-rkerur@gmail.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1443132825-10973-1-git-send-email-rkerur@gmail.com>", "References": "<1443132825-10973-1-git-send-email-rkerur@gmail.com>", "Subject": "[dpdk-dev] [PATCH v1] Add support for I217 and I218 Intel 1G\n\tchipsets.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds I217 and I218 Intel chipsets.\n\nCompiled for:\n > i686-native-linuxapp-gcc\n > x86_64-native-linuxapp-clang\n > x86_64-native-linuxapp-gcc\n > x86_x32-native-linuxapp-gcc\n\nTested on:\n > x86_64 Ubuntu 14.04 with Intel I218-V and I217-LM chipsets.\n\nSigned-off-by: Ravi Kerur <rkerur@gmail.com>\n---\n drivers/net/e1000/base/e1000_api.c | 1 +\n drivers/net/e1000/base/e1000_hw.h | 1 +\n drivers/net/e1000/base/e1000_ich8lan.c | 30 +++++++-----------------\n drivers/net/e1000/base/e1000_osdep.h | 24 +++++++++++++++----\n drivers/net/e1000/em_ethdev.c | 31 ++++++++++++++++++++++++-\n lib/librte_eal/common/include/rte_pci_dev_ids.h | 6 +++++\n 6 files changed, 65 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/net/e1000/base/e1000_api.c b/drivers/net/e1000/base/e1000_api.c\nindex a064565..018a9a3 100644\n--- a/drivers/net/e1000/base/e1000_api.c\n+++ b/drivers/net/e1000/base/e1000_api.c\n@@ -292,6 +292,7 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)\n \tcase E1000_DEV_ID_PCH_LPT_I217_V:\n \tcase E1000_DEV_ID_PCH_LPTLP_I218_LM:\n \tcase E1000_DEV_ID_PCH_LPTLP_I218_V:\n+\tcase E1000_DEV_ID_PCH_LPTLP_I218_V2:\n \t\tmac->type = e1000_pch_lpt;\n \t\tbreak;\n \tcase E1000_DEV_ID_82575EB_COPPER:\ndiff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h\nindex 4dd92a3..c4b6212 100644\n--- a/drivers/net/e1000/base/e1000_hw.h\n+++ b/drivers/net/e1000/base/e1000_hw.h\n@@ -132,6 +132,7 @@ struct e1000_hw;\n #define E1000_DEV_ID_PCH_LPT_I217_V\t\t0x153B\n #define E1000_DEV_ID_PCH_LPTLP_I218_LM\t\t0x155A\n #define E1000_DEV_ID_PCH_LPTLP_I218_V\t\t0x1559\n+#define E1000_DEV_ID_PCH_LPTLP_I218_V2\t\t0x15A1\n #define E1000_DEV_ID_82576\t\t\t0x10C9\n #define E1000_DEV_ID_82576_FIBER\t\t0x10E6\n #define E1000_DEV_ID_82576_SERDES\t\t0x10E7\ndiff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c\nindex 3b1627b..c7fa1ad 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.c\n+++ b/drivers/net/e1000/base/e1000_ich8lan.c\n@@ -1386,29 +1386,15 @@ STATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n \tif (!mac->get_link_status)\n \t\treturn E1000_SUCCESS;\n \n-\tif ((hw->mac.type < e1000_pch_lpt) ||\n-\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||\n-\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {\n-\t\t/* First we want to see if the MII Status Register reports\n-\t\t * link. If so, then we want to get the current speed/duplex\n-\t\t * of the PHY.\n-\t\t */\n-\t\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n-\t\tif (ret_val)\n-\t\t\treturn ret_val;\n-\t} else {\n-\t\t/* Check the MAC's STATUS register to determine link state\n-\t\t * since the PHY could be inaccessible while in ULP mode.\n-\t\t */\n-\t\tlink = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);\n-\t\tif (link)\n-\t\t\tret_val = e1000_disable_ulp_lpt_lp(hw, false);\n-\t\telse\n-\t\t\tret_val = e1000_enable_ulp_lpt_lp(hw, false);\n+\t/* First we want to see if the MII Status Register reports\n+\t * link. If so, then we want to get the current speed/duplex\n+\t * of the PHY.\n+\t */\n+\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 100000, &link);\n+\tif (ret_val)\n+\t\treturn ret_val;\n \n-\t\tif (ret_val)\n-\t\t\treturn ret_val;\n-\t}\n+\tDEBUGOUT1(\"After phy_has_link_generic link state is %d\\n\", link);\n \n \tif (hw->mac.type == e1000_pchlan) {\n \t\tret_val = e1000_k1_gig_workaround_hv(hw, link);\ndiff --git a/drivers/net/e1000/base/e1000_osdep.h b/drivers/net/e1000/base/e1000_osdep.h\nindex d04ec73..3255d37 100644\n--- a/drivers/net/e1000/base/e1000_osdep.h\n+++ b/drivers/net/e1000/base/e1000_osdep.h\n@@ -96,13 +96,22 @@ typedef int\t\tbool;\n \n #define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n \n+#define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg)))\n+\n #define E1000_PCI_REG_WRITE(reg, value) do { \\\n \tE1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \\\n } while (0)\n \n+#define E1000_PCI_REG_WRITE16(reg, value) do { \\\n+\tE1000_PCI_REG16((reg)) = (value); \\\n+} while (0)\n+\n #define E1000_PCI_REG_ADDR(hw, reg) \\\n \t((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))\n \n+#define E1000_PCI_REG_FLASH_ADDR(hw, reg) \\\n+\t((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))\n+\n #define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \\\n \tE1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))\n \n@@ -111,6 +120,11 @@ static inline uint32_t e1000_read_addr(volatile void* addr)\n \treturn rte_le_to_cpu_32(E1000_PCI_REG(addr));\n }\n \n+static inline uint16_t e1000_read_addr16(volatile void* addr)\n+{\n+\treturn rte_le_to_cpu_16(E1000_PCI_REG16(addr));\n+}\n+\n /* Necessary defines */\n #define E1000_MRQC_ENABLE_MASK 0x00000007\n #define E1000_MRQC_RSS_FIELD_IPV6_EX\t\t0x00080000\n@@ -156,20 +170,20 @@ static inline uint32_t e1000_read_addr(volatile void* addr)\n \tE1000_WRITE_REG(hw, reg, value)\n \n /*\n- * Not implemented.\n+ * Tested on I217/I218 chipset.\n */\n \n #define E1000_READ_FLASH_REG(hw, reg) \\\n-\t(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0)\n+\te1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))\n \n #define E1000_READ_FLASH_REG16(hw, reg) \\\n-\t(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0)\n+\te1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))\n \n #define E1000_WRITE_FLASH_REG(hw, reg, value) \\\n-\tE1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value)\n+\tE1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))\n \n #define E1000_WRITE_FLASH_REG16(hw, reg, value) \\\n-\tE1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value)\n+\tE1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))\n \n #define STATIC static\n \ndiff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c\nindex 912f5dd..1f7015e 100644\n--- a/drivers/net/e1000/em_ethdev.c\n+++ b/drivers/net/e1000/em_ethdev.c\n@@ -220,6 +220,28 @@ rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * eth_em_dev_is_ich8 - Check for ICH8 device\n+ * @hw: pointer to the HW structure\n+ *\n+ * return TRUE for ICH8, otherwise FALSE\n+ **/\n+static bool\n+eth_em_dev_is_ich8(struct e1000_hw *hw)\n+{\n+\tDEBUGFUNC(\"eth_em_dev_is_ich8\");\n+\tswitch (hw->device_id) {\n+\tcase E1000_DEV_ID_PCH_LPT_I217_LM:\n+\tcase E1000_DEV_ID_PCH_LPT_I217_V:\n+\tcase E1000_DEV_ID_PCH_LPTLP_I218_LM:\n+\tcase E1000_DEV_ID_PCH_LPTLP_I218_V:\n+\tcase E1000_DEV_ID_PCH_LPTLP_I218_V2:\n+\t\treturn 1;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n static int\n eth_em_dev_init(struct rte_eth_dev *eth_dev)\n {\n@@ -251,6 +273,8 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev)\n \tadapter->stopped = 0;\n \n \t/* For ICH8 support we'll need to map the flash memory BAR */\n+\tif (eth_em_dev_is_ich8(hw))\n+\t\thw->flash_address = (void *)pci_dev->mem_resource[1].addr;\n \n \tif (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||\n \t\t\tem_hw_init(hw) != 0) {\n@@ -476,6 +500,7 @@ em_set_pba(struct e1000_hw *hw)\n \t\t\tbreak;\n \t\tcase e1000_pchlan:\n \t\tcase e1000_pch2lan:\n+\t\tcase e1000_pch_lpt:\n \t\t\tpba = E1000_PBA_26K;\n \t\t\tbreak;\n \t\tdefault:\n@@ -724,7 +749,8 @@ em_hardware_init(struct e1000_hw *hw)\n \t\thw->fc.requested_mode = e1000_fc_none;\n \n \t/* Workaround: no TX flow ctrl for PCH */\n-\tif (hw->mac.type == e1000_pchlan)\n+\tif (hw->mac.type == e1000_pchlan ||\n+\t\thw->mac.type == e1000_pch_lpt)\n \t\thw->fc.requested_mode = e1000_fc_rx_pause;\n \n \t/* Override - settings for PCH2LAN, ya its magic :) */\n@@ -733,6 +759,8 @@ em_hardware_init(struct e1000_hw *hw)\n \t\thw->fc.low_water = 0x5048;\n \t\thw->fc.pause_time = 0x0650;\n \t\thw->fc.refresh_time = 0x0400;\n+\t} else if (hw->mac.type == e1000_pch_lpt) {\n+\t\thw->fc.requested_mode = e1000_fc_full;\n \t}\n \n \tdiag = e1000_init_hw(hw);\n@@ -891,6 +919,7 @@ em_get_max_pktlen(const struct e1000_hw *hw)\n \tcase e1000_ich9lan:\n \tcase e1000_ich10lan:\n \tcase e1000_pch2lan:\n+\tcase e1000_pch_lpt:\n \tcase e1000_82574:\n \tcase e1000_80003es2lan: /* 9K Jumbo Frame size */\n \tcase e1000_82583:\ndiff --git a/lib/librte_eal/common/include/rte_pci_dev_ids.h b/lib/librte_eal/common/include/rte_pci_dev_ids.h\nindex cf2cf70..e0d69e8 100644\n--- a/lib/librte_eal/common/include/rte_pci_dev_ids.h\n+++ b/lib/librte_eal/common/include/rte_pci_dev_ids.h\n@@ -272,6 +272,7 @@\n #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B\n #define E1000_DEV_ID_PCH_LPTLP_I218_LM\t 0x155A\n #define E1000_DEV_ID_PCH_LPTLP_I218_V\t 0x1559\n+#define E1000_DEV_ID_PCH_LPTLP_I218_V2\t 0x15A1\n \n /*\n * Tested (supported) on VM emulated HW.\n@@ -305,6 +306,11 @@ RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L)\n RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L)\n RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA)\n RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V)\n+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_LM)\n+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_V)\n+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM)\n+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V)\n+RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V2)\n \n /******************** Physical IGB devices from e1000_hw.h ********************/\n \n", "prefixes": [ "dpdk-dev", "v1" ] }