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GET /api/patches/71244/?format=api
{ "id": 71244, "url": "https://patches.dpdk.org/api/patches/71244/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200611084330.18301-6-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200611084330.18301-6-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200611084330.18301-6-qi.z.zhang@intel.com", "date": "2020-06-11T08:43:25", "name": "[05/10] net/ice/base: rename misleading variable", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7ca48688f97ea011e667b4ee7b538734b40acff2", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200611084330.18301-6-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 10404, "url": "https://patches.dpdk.org/api/series/10404/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=10404", "date": "2020-06-11T08:43:20", "name": "net/ice: base code update for 20.08 batch 2", "version": 1, "mbox": "https://patches.dpdk.org/series/10404/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/71244/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/71244/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 73F58A00C5;\n\tThu, 11 Jun 2020 10:40:22 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0913B1BE9B;\n\tThu, 11 Jun 2020 10:39:45 +0200 (CEST)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 31D851BE8E\n for <dev@dpdk.org>; Thu, 11 Jun 2020 10:39:43 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Jun 2020 01:39:43 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by orsmga004.jf.intel.com with ESMTP; 11 Jun 2020 01:39:41 -0700" ], "IronPort-SDR": [ "\n 0WWWaHB4uat/sIAkyrtLs0iBukpkeiozYSpa4gXz9QT7uvIimHf3yvbNQfs7JU11DfttBMh5Gb\n j3DpDF6E/guA==", "\n 4vSYXS3PkgY0RMPWNsZnTtYt85yPkxknZlfOYp0YJzsdkBkCNR9BdyiRBFtYiyNaRCx4DizxTM\n lGU1CXiS0M2g==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,499,1583222400\"; d=\"scan'208\";a=\"419039172\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Nick Nunley <nicholas.d.nunley@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Thu, 11 Jun 2020 16:43:25 +0800", "Message-Id": "<20200611084330.18301-6-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200611084330.18301-1-qi.z.zhang@intel.com>", "References": "<20200611084330.18301-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 05/10] net/ice/base: rename misleading variable", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The grst_delay variable in ice_check_reset contains the maximum time\n(in 100 msec units) that the driver will wait for a reset event to\ntransition to the Device Active state. The value is the sum of three\nseparate components:\n1) The maximum time it may take for the firmware to process its\noutstanding command before handling the reset request.\n2) The value in RSTCTL.GRSTDEL (the delay firmware inserts between first\nseeing the driver reset request and the actual hardware assertion).\n3) The maximum expected reset processing time in hardware.\n\nReferring to this total time as \"grst_delay\" is misleading and\npotentially confusing to someone checking the code and cross-referencing\nthe hardware specification.\n\nFix this by renaming the variable to \"grst_timeout\", which is more\ndescriptive of its actual use.\n\nSigned-off-by: Nick Nunley <nicholas.d.nunley@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 85b6e1a37..1683daf28 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -882,23 +882,23 @@ void ice_deinit_hw(struct ice_hw *hw)\n */\n enum ice_status ice_check_reset(struct ice_hw *hw)\n {\n-\tu32 cnt, reg = 0, grst_delay, uld_mask;\n+\tu32 cnt, reg = 0, grst_timeout, uld_mask;\n \n \t/* Poll for Device Active state in case a recent CORER, GLOBR,\n \t * or EMPR has occurred. The grst delay value is in 100ms units.\n \t * Add 1sec for outstanding AQ commands that can take a long time.\n \t */\n-\tgrst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>\n-\t\t GLGEN_RSTCTL_GRSTDEL_S) + 10;\n+\tgrst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>\n+\t\t\tGLGEN_RSTCTL_GRSTDEL_S) + 10;\n \n-\tfor (cnt = 0; cnt < grst_delay; cnt++) {\n+\tfor (cnt = 0; cnt < grst_timeout; cnt++) {\n \t\tice_msec_delay(100, true);\n \t\treg = rd32(hw, GLGEN_RSTAT);\n \t\tif (!(reg & GLGEN_RSTAT_DEVSTATE_M))\n \t\t\tbreak;\n \t}\n \n-\tif (cnt == grst_delay) {\n+\tif (cnt == grst_timeout) {\n \t\tice_debug(hw, ICE_DBG_INIT,\n \t\t\t \"Global reset polling failed to complete.\\n\");\n \t\treturn ICE_ERR_RESET_FAILED;\n", "prefixes": [ "05/10" ] }