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{
    "id": 7115,
    "url": "https://patches.dpdk.org/api/patches/7115/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1442906770-18805-2-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1442906770-18805-2-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1442906770-18805-2-git-send-email-helin.zhang@intel.com",
    "date": "2015-09-22T07:26:09",
    "name": "[dpdk-dev,v2,1/2] i40e: add RSS granularity configuration",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e73033624243d3f4f24e749be18d3602fd54ba26",
    "submitter": {
        "id": 14,
        "url": "https://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1442906770-18805-2-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/7115/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/7115/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 6C77E8DAE;\n\tTue, 22 Sep 2015 09:26:26 +0200 (CEST)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 471478DAC\n\tfor <dev@dpdk.org>; Tue, 22 Sep 2015 09:26:24 +0200 (CEST)",
            "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga103.jf.intel.com with ESMTP; 22 Sep 2015 00:26:23 -0700",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 22 Sep 2015 00:26:21 -0700",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t8M7QIv5008109;\n\tTue, 22 Sep 2015 15:26:18 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t8M7QE9Y018846; Tue, 22 Sep 2015 15:26:16 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t8M7QESM018842; \n\tTue, 22 Sep 2015 15:26:14 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.17,571,1437462000\"; d=\"scan'208\";a=\"566063814\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Tue, 22 Sep 2015 15:26:09 +0800",
        "Message-Id": "<1442906770-18805-2-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1442906770-18805-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1442903547-18198-1-git-send-email-helin.zhang@intel.com>\n\t<1442906770-18805-1-git-send-email-helin.zhang@intel.com>",
        "Cc": "yulong.pei@intel.com",
        "Subject": "[dpdk-dev] [PATCH v2 1/2] i40e: add RSS granularity configuration",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The default fields of a received packet are loaded from firmware,\nwhich cannot be modified even users want to use different fields\nfor RSS or filtering. Here adds a workaround to open more\nflexibilities of selecting packet fields for hash calculation or\nflow director to users.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nSigned-off-by: Andrey Chilikin <andrey.chilikin@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c  | 591 ++++++++++++++++++++++++++++++++++++++++\n drivers/net/i40e/i40e_ethdev.h  |   6 +\n drivers/net/i40e/i40e_fdir.c    |  31 +++\n lib/librte_ether/rte_eth_ctrl.h | 106 ++++++-\n 4 files changed, 730 insertions(+), 4 deletions(-)\n\nv2 changes:\nSolved the compilation issues.",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 2dd9fdc..e711992 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -113,6 +113,131 @@\n #define I40E_PRTTSYN_TSYNENA  0x80000000\n #define I40E_PRTTSYN_TSYNTYPE 0x0e000000\n \n+#define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))\n+#define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))\n+#define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))\n+#define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))\n+\n+#define I40E_INSET_UNKNOWN        0x00000000000000000ULL\n+\n+/* FD/Hash filters input set fields */\n+#define I40E_INSET_DMAC            0x0000000000000001ULL\n+#define I40E_INSET_SMAC            0x0000000000000002ULL\n+#define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL\n+#define I40E_INSET_VLAN_INNER      0x0000000000000008ULL\n+#define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL\n+\n+#define I40E_INSET_IPV4_SRC        0x0000000000000100ULL\n+#define I40E_INSET_IPV4_DST        0x0000000000000200ULL\n+#define I40E_INSET_IPV6_SRC        0x0000000000000400ULL\n+#define I40E_INSET_IPV6_DST        0x0000000000000800ULL\n+#define I40E_INSET_SRC_PORT        0x0000000000001000ULL\n+#define I40E_INSET_DST_PORT        0x0000000000002000ULL\n+#define I40E_INSET_SCTP_VT         0x0000000000004000ULL\n+\n+/* next 8 fields can be used with masking only; two 16-bit masks per PCTYPE */\n+#define I40E_INSET_IPV4_TOS        0x0000000000010000ULL\n+#define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL\n+#define I40E_INSET_IPV4_TTL        0x0000000000040000ULL\n+#define I40E_INSET_IPV6_TC         0x0000000000080000ULL\n+#define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL\n+#define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL\n+#define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL\n+#define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL\n+\n+/* tunnel outer IP, valid only if flexible payload is not defined */\n+#define I40E_INSET_TUNNEL_IPV4_DST 0x0000000001000000ULL\n+#define I40E_INSET_TUNNEL_IPV6_DST 0x0000000002000000ULL\n+#define I40E_INSET_TUNNEL_DMAC     0x0000000004000000ULL\n+#define I40E_INSET_TUNNEL_SRC_PORT 0x0000000008000000ULL\n+#define I40E_INSET_TUNNEL_DST_PORT 0x0000000010000000ULL\n+#define I40E_INSET_TUNNEL_ID       0x0000000020000000ULL\n+#define I40E_INSET_GRE_NEXT_PROTO  I40E_INSET_DST_PORT\n+\n+/* last Ethertype for L2 PCTYPE                       */\n+#define I40E_INSET_LAST_ETHER_TYPE 0x0000000100000000ULL\n+\n+/* 8 words of Flex Payload                            */\n+#define I40E_INSET_FLEX_PAYLOAD_W1 0x0000001000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W2 0x0000002000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W3 0x0000004000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W4 0x0000008000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W5 0x0000010000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W6 0x0000020000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W7 0x0000040000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD_W8 0x0000080000000000ULL\n+#define I40E_INSET_FLEX_PAYLOAD \\\n+\t(I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \\\n+\tI40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \\\n+\tI40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \\\n+\tI40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)\n+\n+#define I40E_INSET_ALL             0xFFFFFFFFFFFFFFFFULL\n+\n+/**\n+ * Below are values for writing un-exposed registers suggested\n+ * by silicon experts\n+ */\n+/* Destination MAC address */\n+#define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL\n+/* Source MAC address */\n+#define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL\n+/* VLAN tag in the outer L2 header */\n+#define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL\n+/* VLAN tag in the inner L2 header */\n+#define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL\n+/* Source IPv4 address */\n+#define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL\n+/* Destination IPv4 address */\n+#define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL\n+/* Source IPv6 address */\n+#define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL\n+/* Destination IPv6 address */\n+#define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL\n+/* Source L4 port */\n+#define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL\n+/* Destination L4 port */\n+#define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL\n+/* SCTP verification tag */\n+#define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL\n+/* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/\n+#define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL\n+/* Source port of tunneling UDP */\n+#define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL\n+/* Destination port of tunneling UDP */\n+#define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL\n+/* Tunneling UDP keys */\n+#define I40E_REG_INSET_TUNNEL_L4_UDP_KEY         0x00000000000F8000ULL\n+/* GRE version and protocol type */\n+#define I40E_REG_INSET_TUNNEL_GRE_VER_PROTO_TYPE 0x0000000000300000ULL\n+/* GRE key */\n+#define I40E_REG_INSET_TUNNEL_GRE_KEY            0x00000000000C0000ULL\n+/* Last ether type */\n+#define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL\n+/* Tunneling outer destination IPv4 address */\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL\n+/* Tunneling outer destination IPv6 address */\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL\n+/* 1st word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL\n+/* 2nd word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL\n+/* 3rd word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL\n+/* 4th word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL\n+/* 5th word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL\n+/* 6th word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL\n+/* 7th word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL\n+/* 8th word of flex payload */\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL\n+#define I40E_REG_INSET_ALL                       0xFFFFFFFFFFFFFFFFULL\n+\n+#define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL\n+\n static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);\n static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);\n static int i40e_dev_configure(struct rte_eth_dev *dev);\n@@ -5451,6 +5576,466 @@ out:\n \treturn 0;\n }\n \n+/**\n+ * Validate if the input set is allowed for a specific PCTYPE\n+ */\n+static int\n+i40e_validate_input_set(enum i40e_filter_pctype pctype, uint64_t inset)\n+{\n+\tstatic const uint64_t valid_inset_table[] = {\n+\t\t[I40E_FILTER_PCTYPE_FRAG_IPV4] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |\n+\t\t\tI40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |\n+\t\t\tI40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |\n+\t\t\tI40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |\n+\t\t\tI40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |\n+\t\t\tI40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |\n+\t\t\tI40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |\n+\t\t\tI40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |\n+\t\t\tI40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |\n+\t\t\tI40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |\n+\t\t\tI40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |\n+\t\t\tI40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |\n+\t\t\tI40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |\n+\t\t\tI40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_FRAG_IPV6] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |\n+\t\t\tI40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |\n+\t\t\tI40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |\n+\t\t\tI40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |\n+\t\t\tI40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |\n+\t\t\tI40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |\n+\t\t\tI40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |\n+\t\t\tI40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |\n+\t\t\tI40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |\n+\t\t\tI40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |\n+\t\t\tI40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |\n+\t\t\tI40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |\n+\t\t\tI40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |\n+\t\t\tI40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |\n+\t\t\tI40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |\n+\t\t\tI40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |\n+\t\t\tI40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |\n+\t\t\tI40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |\n+\t\t\tI40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |\n+\t\t\tI40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,\n+\t\t[I40E_FILTER_PCTYPE_L2_PAYLOAD] =\n+\t\t\tI40E_INSET_DMAC | I40E_INSET_SMAC |\n+\t\t\tI40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |\n+\t\t\tI40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |\n+\t\t\tI40E_INSET_FLEX_PAYLOAD,\n+\t};\n+\n+\tif (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)\n+\t\treturn -EINVAL;\n+\n+\tif ((inset != I40E_INSET_ALL) && (inset &\n+\t\t(~valid_inset_table[pctype])))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+/* default input set fields combination per pctype */\n+static uint64_t\n+i40e_get_default_input_set(uint16_t pctype)\n+{\n+\tstatic const uint64_t default_inset_table[] = {\n+\t\t[I40E_FILTER_PCTYPE_FRAG_IPV4] =\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |\n+\t\t\tI40E_INSET_SCTP_VT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =\n+\t\t\tI40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,\n+\t\t[I40E_FILTER_PCTYPE_FRAG_IPV6] =\n+\t\t\tI40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =\n+\t\t\tI40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =\n+\t\t\tI40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =\n+\t\t\tI40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |\n+\t\t\tI40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |\n+\t\t\tI40E_INSET_SCTP_VT,\n+\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =\n+\t\t\tI40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,\n+\t\t[I40E_FILTER_PCTYPE_L2_PAYLOAD] =\n+\t\t\tI40E_INSET_LAST_ETHER_TYPE,\n+\t};\n+\n+\tif (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)\n+\t\treturn 0;\n+\n+\treturn default_inset_table[pctype];\n+}\n+\n+/**\n+ * Parse the input set from index to logical bit masks\n+ */\n+static uint64_t\n+i40e_parse_input_set(enum i40e_filter_pctype pctype,\n+\t\t     enum rte_eth_input_set_field *field,\n+\t\t     uint16_t size)\n+{\n+\tuint64_t inset = 0;\n+\tuint16_t i, j;\n+\n+\tstatic const struct {\n+\t\tenum rte_eth_input_set_field field;\n+\t\tuint64_t inset;\n+\t} inset_convert_table[] = {\n+\t\t{RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},\n+\t\t{RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},\n+\t\t{RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},\n+\t\t{RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},\n+\t\t{RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},\n+\t\t{RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},\n+\t\t{RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},\n+\t\t{RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},\n+\t\t{RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},\n+\t\t{RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},\n+\t\t{RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},\n+\t\t{RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},\n+\t\t{RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,\n+\t\t\tI40E_INSET_IPV6_NEXT_HDR},\n+\t\t{RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},\n+\t\t{RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,\n+\t\t\tI40E_INSET_SCTP_VT},\n+\t\t{RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,\n+\t\t\tI40E_INSET_TUNNEL_DMAC},\n+\t\t{RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,\n+\t\t\tI40E_INSET_VLAN_TUNNEL},\n+\t\t{RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY, I40E_INSET_TUNNEL_ID},\n+\t\t{RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},\n+\t\t{RTE_ETH_INPUT_SET_ALL, I40E_INSET_ALL},\n+\t};\n+\n+\tif (!field || size > RTE_ETH_INSET_SIZE_MAX)\n+\t\treturn 0;\n+\n+\t/* Only one item allowed for default or all */\n+\tif (size == 1) {\n+\t\tif (field[0] == RTE_ETH_INPUT_SET_DEFAULT)\n+\t\t\treturn i40e_get_default_input_set(pctype);\n+\t\telse if (field[0] == RTE_ETH_INPUT_SET_ALL)\n+\t\t\treturn I40E_INSET_ALL;\n+\t}\n+\n+\tfor (i = 0; i < size; i++) {\n+\t\tfor (j = 0; j < RTE_DIM(inset_convert_table); j++) {\n+\t\t\tif (field[i] == inset_convert_table[j].field) {\n+\t\t\t\tinset |= inset_convert_table[j].inset;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* It contains unsupported input set, return 0 immediately */\n+\t\tif (j == RTE_DIM(inset_convert_table))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn inset;\n+}\n+\n+/**\n+ * Translate the input set from bit masks to register aware bit masks\n+ */\n+static uint64_t\n+i40e_translate_input_set_reg(uint64_t inset)\n+{\n+\tuint64_t val = 0;\n+\tuint16_t i;\n+\n+\tstatic const struct {\n+\t\tuint64_t inset;\n+\t\tuint64_t inset_reg;\n+\t} inset_map[] = {\n+\t\t{I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},\n+\t\t{I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},\n+\t\t{I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},\n+\t\t{I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},\n+\t\t{I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},\n+\t\t{I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},\n+\t\t{I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},\n+\t\t{I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},\n+\t\t{I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},\n+\t\t{I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},\n+\t\t{I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},\n+\t\t{I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},\n+\t\t{I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_GRE_KEY},\n+\t\t{I40E_INSET_TUNNEL_DMAC,\n+\t\t\tI40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},\n+\t\t{I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},\n+\t\t{I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},\n+\t\t{I40E_INSET_TUNNEL_SRC_PORT,\n+\t\t\tI40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},\n+\t\t{I40E_INSET_TUNNEL_DST_PORT,\n+\t\t\tI40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},\n+\t\t{I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},\n+\t};\n+\n+\tif (inset == I40E_INSET_ALL)\n+\t\treturn I40E_REG_INSET_ALL;\n+\n+\tfor (i = 0; i < RTE_DIM(inset_map); i++) {\n+\t\tif (inset & inset_map[i].inset)\n+\t\t\tval |= inset_map[i].inset_reg;\n+\t}\n+\n+\treturn val;\n+}\n+\n+static int\n+i40e_generate_inset_mask_reg(uint64_t inset, uint64_t *mask)\n+{\n+\tuint8_t idx = 0;\n+\n+\tif (!mask)\n+\t\treturn -EINVAL;\n+\n+\t*mask = I40E_REG_INSET_MASK_DEFAULT;\n+\tif (inset & I40E_INSET_IPV4_TOS) {\n+\t\t*mask |= (0x0009FF00 << (idx * 32));\n+\t\tidx++;\n+\t}\n+\tif (inset & I40E_INSET_IPV4_PROTO) {\n+\t\t*mask |= (0x000DFF00 << (idx * 32));\n+\t\tidx++;\n+\t}\n+\n+\treturn idx;\n+}\n+\n+static void\n+i40e_check_modify_reg(struct i40e_hw *hw, uint32_t addr,\n+\t\t\t    uint32_t val, uint8_t enable)\n+{\n+\tuint32_t reg, reg_o = I40E_READ_REG(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\\n\", addr, reg_o);\n+\tif (enable)\n+\t\treg = reg_o | val;\n+\telse\n+\t\treg = reg_o & ~val;\n+\tif (reg != reg_o)\n+\t\tI40E_WRITE_REG(hw, addr, reg);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\\n\", addr,\n+\t\t    (uint32_t)I40E_READ_REG(hw, addr));\n+}\n+\n+static void\n+i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\\n\", addr, reg);\n+\tif (reg != val)\n+\t\tI40E_WRITE_REG(hw, addr, val);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\\n\", addr,\n+\t\t    (uint32_t)I40E_READ_REG(hw, addr));\n+}\n+\n+static int\n+i40e_check_write_mask_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)\n+{\n+\tuint32_t reg = I40E_READ_REG(hw, addr);\n+\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] original: 0x%08x\\n\", addr, reg);\n+\tif (reg != 0)\n+\t\treturn -EINVAL;\n+\tI40E_WRITE_REG(hw, addr, val);\n+\tPMD_DRV_LOG(DEBUG, \"[0x%08x] after: 0x%08x\\n\", addr,\n+\t\t    (uint32_t)I40E_READ_REG(hw, addr));\n+\n+\treturn 0;\n+}\n+\n+int\n+i40e_filter_inset_select(struct i40e_hw *hw,\n+\t\t\t  struct rte_eth_input_set_conf *conf,\n+\t\t\t  enum rte_filter_type filter)\n+{\n+\tenum i40e_filter_pctype pctype;\n+\tuint64_t inset_reg, mask_reg;\n+\tuint64_t input_set;\n+\tuint32_t reg;\n+\tint num, i;\n+\n+\tif (!hw || !conf) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\tpctype = i40e_flowtype_to_pctype(conf->flow_type);\n+\tif (pctype == 0 ||\n+\t\tpctype > I40E_FILTER_PCTYPE_L2_PAYLOAD || (filter !=\n+\t\tRTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR)) {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tinput_set = i40e_parse_input_set(pctype, conf->field,\n+\t\t\t\t\t conf->inset_size);\n+\tif (!input_set)\n+\t\treturn -EINVAL;\n+\n+\tif (i40e_validate_input_set(pctype, input_set) != 0)\n+\t\treturn -EINVAL;\n+\n+\tif (input_set == I40E_INSET_ALL && conf->enable) {\n+\t\t/* Return with failure if trying to enable all */\n+\t\treturn -EINVAL;\n+\t} else if (input_set == I40E_INSET_ALL && !conf->enable) {\n+\t\t/* Clear all registers if trying to disable all */\n+\t\tif (filter == RTE_ETH_FILTER_HASH) {\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_GLQF_HASH_MSK(0, pctype),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_GLQF_HASH_MSK(1, pctype),\n+\t\t\t\t\t     0x0);\n+\t\t} else if (filter == RTE_ETH_FILTER_FDIR) {\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_PRTQF_FD_INSET(pctype, 0),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw,\n+\t\t\t\t\t     I40E_PRTQF_FD_INSET(pctype, 1),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_MSK(pctype, 0),\n+\t\t\t\t\t     0x0);\n+\t\t\ti40e_check_write_reg(hw, I40E_PRTQF_FD_MSK(pctype, 1),\n+\t\t\t\t\t     0x0);\n+\t\t}\n+\t\tI40E_WRITE_FLUSH(hw);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tinset_reg = i40e_translate_input_set_reg(input_set);\n+\tif (!inset_reg)\n+\t\treturn -EINVAL;\n+\n+\tnum = i40e_generate_inset_mask_reg(input_set, &mask_reg);\n+\tif (num < 0 || num > 2)\n+\t\treturn -EINVAL;\n+\n+\tif (filter == RTE_ETH_FILTER_HASH) {\n+\t\ti40e_check_modify_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),\n+\t\t\t\t      (uint32_t)(inset_reg & 0xFFFFFFFF),\n+\t\t\t\t      conf->enable);\n+\t\ti40e_check_modify_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),\n+\t\t\t\t      (uint32_t)((inset_reg >> 32) &\n+\t\t\t\t      0xFFFFFFFF), conf->enable);\n+\n+\t\tfor (i = 0; i < num; i++) {\n+\t\t\treg = (uint32_t)(mask_reg >> (i * 32));\n+\t\t\tif (i40e_check_write_mask_reg(hw,\n+\t\t\t\t\t\t      I40E_GLQF_HASH_MSK(0,\n+\t\t\t\t\t\t      pctype), reg) == 0)\n+\t\t\t\tcontinue;\n+\t\t\tif (i40e_check_write_mask_reg(hw,\n+\t\t\t\t\t\t      I40E_GLQF_HASH_MSK(1,\n+\t\t\t\t\t\t      pctype), reg) < 0)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else if (filter == RTE_ETH_FILTER_FDIR) {\n+\t\ti40e_check_modify_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),\n+\t\t\t\t      (uint32_t)(inset_reg & 0xFFFFFFFF),\n+\t\t\t\t      conf->enable);\n+\t\ti40e_check_modify_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),\n+\t\t\t\t      (uint32_t)((inset_reg >> 32) &\n+\t\t\t\t      0xFFFFFFFF), conf->enable);\n+\t\tfor (i = 0; i < num; i++) {\n+\t\t\treg = (uint32_t)(mask_reg >> (i * 32));\n+\t\t\tif (i40e_check_write_mask_reg(hw,\n+\t\t\t\tI40E_PRTQF_FD_MSK(pctype, 0), reg) == 0)\n+\t\t\t\tcontinue;\n+\t\t\tif (i40e_check_write_mask_reg(hw,\n+\t\t\t\tI40E_PRTQF_FD_MSK(pctype, 1), reg) < 0)\n+\t\t\t\treturn -EINVAL;\n+\t\t}\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\tI40E_WRITE_FLUSH(hw);\n+\n+\treturn 0;\n+}\n+\n static int\n i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n {\n@@ -5498,6 +6083,12 @@ i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n \t\tret = i40e_set_hash_filter_global_config(hw,\n \t\t\t\t&(info->info.global_conf));\n \t\tbreak;\n+\tcase RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:\n+\t\tret = i40e_filter_inset_select(hw,\n+\t\t\t\t\t       &(info->info.input_set_conf),\n+\t\t\t\t\t       RTE_ETH_FILTER_HASH);\n+\t\tbreak;\n+\n \tdefault:\n \t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n \t\t\t\t\t\t\tinfo->info_type);\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex 6185657..a997a08 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -501,6 +501,12 @@ uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);\n int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,\n \t\t\t  enum rte_filter_op filter_op,\n \t\t\t  void *arg);\n+int i40e_select_filter_input_set(struct i40e_hw *hw,\n+\t\t\t\t struct rte_eth_input_set_conf *conf,\n+\t\t\t\t enum rte_filter_type filter);\n+int i40e_filter_inset_select(struct i40e_hw *hw,\n+\t\t\t     struct rte_eth_input_set_conf *conf,\n+\t\t\t     enum rte_filter_type filter);\n \n /* I40E_DEV_PRIVATE_TO */\n #define I40E_DEV_PRIVATE_TO_PF(adapter) \\\ndiff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c\nindex c9ce98f..ba18c9d 100644\n--- a/drivers/net/i40e/i40e_fdir.c\n+++ b/drivers/net/i40e/i40e_fdir.c\n@@ -1342,6 +1342,33 @@ i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)\n \t\t\t    I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n }\n \n+static int\n+i40e_fdir_filter_set(struct rte_eth_dev *dev,\n+\t\t     struct rte_eth_hash_filter_info *info)\n+{\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tint ret = 0;\n+\n+\tif (!info) {\n+\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tswitch (info->info_type) {\n+\tcase RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:\n+\t\tret = i40e_filter_inset_select(hw,\n+\t\t\t&(info->info.input_set_conf), RTE_ETH_FILTER_FDIR);\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_DRV_LOG(ERR, \"FD filter info type (%d) not supported\",\n+\t\t\t    info->info_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n /*\n  * i40e_fdir_ctrl_func - deal with all operations on flow director.\n  * @pf: board private structure\n@@ -1382,6 +1409,10 @@ i40e_fdir_ctrl_func(struct rte_eth_dev *dev,\n \tcase RTE_ETH_FILTER_INFO:\n \t\ti40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);\n \t\tbreak;\n+\tcase RTE_ETH_FILTER_SET:\n+\t\tret = i40e_fdir_filter_set(dev,\n+\t\t\t(struct rte_eth_hash_filter_info *)arg);\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_STATS:\n \t\ti40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);\n \t\tbreak;\ndiff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h\nindex 26b7b33..2a1eb36 100644\n--- a/lib/librte_ether/rte_eth_ctrl.h\n+++ b/lib/librte_ether/rte_eth_ctrl.h\n@@ -1,7 +1,7 @@\n /*-\n  *   BSD LICENSE\n  *\n- *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n  *   All rights reserved.\n  *\n  *   Redistribution and use in source and binary forms, with or without\n@@ -295,7 +295,73 @@ struct rte_eth_tunnel_filter_conf {\n \tuint16_t queue_id;      /** < queue number. */\n };\n \n-#define RTE_ETH_FDIR_MAX_FLEXLEN         16 /** < Max length of flexbytes. */\n+#define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */\n+#define RTE_ETH_INSET_SIZE_MAX   128 /** < Max length of input set. */\n+\n+/**\n+ * Input set fields for Flow Director and Hash filters\n+ */\n+enum rte_eth_input_set_field {\n+\tRTE_ETH_INPUT_SET_UNKNOWN = 0,\n+\n+\t/* L2 */\n+\tRTE_ETH_INPUT_SET_L2_SRC_MAC = 1,\n+\tRTE_ETH_INPUT_SET_L2_DST_MAC,\n+\tRTE_ETH_INPUT_SET_L2_OUTER_VLAN,\n+\tRTE_ETH_INPUT_SET_L2_INNER_VLAN,\n+\tRTE_ETH_INPUT_SET_L2_ETHERTYPE,\n+\n+\t/* L3 */\n+\tRTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,\n+\tRTE_ETH_INPUT_SET_L3_DST_IP4,\n+\tRTE_ETH_INPUT_SET_L3_SRC_IP6,\n+\tRTE_ETH_INPUT_SET_L3_DST_IP6,\n+\tRTE_ETH_INPUT_SET_L3_IP4_TOS,\n+\tRTE_ETH_INPUT_SET_L3_IP4_PROTO,\n+\tRTE_ETH_INPUT_SET_L3_IP6_TC,\n+\tRTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,\n+\n+\t/* L4 */\n+\tRTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,\n+\tRTE_ETH_INPUT_SET_L4_UDP_DST_PORT,\n+\tRTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,\n+\tRTE_ETH_INPUT_SET_L4_TCP_DST_PORT,\n+\tRTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,\n+\tRTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,\n+\tRTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,\n+\n+\t/* Tunnel */\n+\tRTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,\n+\tRTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,\n+\tRTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,\n+\tRTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,\n+\tRTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,\n+\n+\t/* Flexible Payload */\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,\n+\tRTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,\n+\n+\tRTE_ETH_INPUT_SET_DEFAULT = 65533,\n+\tRTE_ETH_INPUT_SET_ALL = 65534,\n+\tRTE_ETH_INPUT_SET_MAX = 65535,\n+};\n+\n+/**\n+ * A structure used to define the input set configuration for\n+ * flow director and hash filters\n+ */\n+struct rte_eth_input_set_conf {\n+\tuint16_t flow_type;\n+\tuint16_t inset_size;\n+\tenum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];\n+\tuint8_t enable;\n+};\n \n /**\n  * A structure used to define the input for L2 flow\n@@ -504,7 +570,7 @@ struct rte_eth_fdir_flex_mask {\n \n /**\n  * A structure used to define all flexible payload related setting\n- * include flexpay load and flex mask\n+ * include flex payload and flex mask\n  */\n struct rte_eth_fdir_flex_conf {\n \tuint16_t nb_payloads;  /**< The number of following payload cfg */\n@@ -582,12 +648,40 @@ struct rte_eth_fdir_stats {\n };\n \n /**\n+ * Flow Director filter information types.\n+ */\n+enum rte_eth_fdir_filter_info_type {\n+\tRTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,\n+\t/** Flow Director filter input set configuration */\n+\tRTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,\n+\tRTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,\n+};\n+\n+/**\n+ * A structure used to set or get hash filter information, to support filter\n+ * type of 'RTE_ETH_FILTER_FDIR' RTE_ETH_FILTER_SET operation.\n+ */\n+/**\n+ * A structure used to support Flow Director RTE_ETH_FILTER_SET operations\n+  */\n+struct rte_eth_fdir_filter_info {\n+\tenum rte_eth_fdir_filter_info_type info_type; /**< Information type */\n+\t/** Details of fdir filter information */\n+\tunion {\n+\t\t/** Flow Director input set configuration per port */\n+\t\tstruct rte_eth_input_set_conf input_set_conf;\n+\t} info;\n+};\n+\n+/**\n  * Hash filter information types.\n  * - RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT is for getting/setting the\n  *   information/configuration of 'symmetric hash enable' per port.\n  * - RTE_ETH_HASH_FILTER_GLOBAL_CONFIG is for getting/setting the global\n  *   configurations of hash filters. Those global configurations are valid\n  *   for all ports of the same NIC.\n+ * - RTE_ETH_HASH_FILTER_INPUT_SET_SELECT is for setting the global\n+ *   hash input set fields\n  */\n enum rte_eth_hash_filter_info_type {\n \tRTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,\n@@ -595,6 +689,8 @@ enum rte_eth_hash_filter_info_type {\n \tRTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,\n \t/** Configure globally for hash filter */\n \tRTE_ETH_HASH_FILTER_GLOBAL_CONFIG,\n+\t/** Global Hash filter input set configuration */\n+\tRTE_ETH_HASH_FILTER_INPUT_SET_SELECT,\n \tRTE_ETH_HASH_FILTER_INFO_TYPE_MAX,\n };\n \n@@ -614,7 +710,7 @@ enum rte_eth_hash_function {\n  * A structure used to set or get global hash function configurations which\n  * include symmetric hash enable per flow type and hash function type.\n  * Each bit in sym_hash_enable_mask[] indicates if the symmetric hash of the\n- * coresponding flow type is enabled or not.\n+ * corresponding flow type is enabled or not.\n  * Each bit in valid_bit_mask[] indicates if the corresponding bit in\n  * sym_hash_enable_mask[] is valid or not. For the configurations gotten, it\n  * also means if the flow type is supported by hardware or not.\n@@ -639,6 +735,8 @@ struct rte_eth_hash_filter_info {\n \t\tuint8_t enable;\n \t\t/** Global configurations of hash filter */\n \t\tstruct rte_eth_hash_global_conf global_conf;\n+\t\t/** Global configurations of hash filter input set */\n+\t\tstruct rte_eth_input_set_conf input_set_conf;\n \t} info;\n };\n \n",
    "prefixes": [
        "dpdk-dev",
        "v2",
        "1/2"
    ]
}