Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/6920/?format=api
{ "id": 6920, "url": "https://patches.dpdk.org/api/patches/6920/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1441523526-26202-19-git-send-email-jingjing.wu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1441523526-26202-19-git-send-email-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1441523526-26202-19-git-send-email-jingjing.wu@intel.com", "date": "2015-09-06T07:11:32", "name": "[dpdk-dev,18/52] i40e/base: Add parsing for CEE DCBX TLVs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5dd2405c763ab8c3f8d509f4ef37940247f78d58", "submitter": { "id": 47, "url": "https://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1441523526-26202-19-git-send-email-jingjing.wu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/6920/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/6920/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id B2F0A8E7A;\n\tSun, 6 Sep 2015 09:12:56 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id BEC7F8E6C\n\tfor <dev@dpdk.org>; Sun, 6 Sep 2015 09:12:54 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 06 Sep 2015 00:12:53 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga003.jf.intel.com with ESMTP; 06 Sep 2015 00:12:53 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t867Coxl018586;\n\tSun, 6 Sep 2015 15:12:50 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t867CmGA026363; Sun, 6 Sep 2015 15:12:50 +0800", "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t867CmZH026359; \n\tSun, 6 Sep 2015 15:12:48 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,478,1437462000\"; d=\"scan'208\";a=\"639504765\"", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Sun, 6 Sep 2015 15:11:32 +0800", "Message-Id": "<1441523526-26202-19-git-send-email-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1441523526-26202-1-git-send-email-jingjing.wu@intel.com>", "References": "<1441523526-26202-1-git-send-email-jingjing.wu@intel.com>", "Subject": "[dpdk-dev] [PATCH 18/52] i40e/base: Add parsing for CEE DCBX TLVs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds parsing for CEE DCBX TLVs from the LLDP MIB.\n\nWhile the driver gets the DCB CEE operational configuration from Firmware\nusing the \"Get CEE DCBX Oper Config\" AQ command there is a need to get\nthe CEE DesiredCfg Tx by firmware and DCB configuration Rx from peer; for\ndebug and other application purposes.\n\nAlso gets rid of unused locals variables.\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n drivers/net/i40e/base/i40e_dcb.c | 191 +++++++++++++++++++++++++++++++++++++-\n drivers/net/i40e/base/i40e_dcb.h | 39 ++++++++\n drivers/net/i40e/base/i40e_type.h | 2 +\n 3 files changed, 228 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/i40e/base/i40e_dcb.c b/drivers/net/i40e/base/i40e_dcb.c\nindex 033e52d..9c8e044 100644\n--- a/drivers/net/i40e/base/i40e_dcb.c\n+++ b/drivers/net/i40e/base/i40e_dcb.c\n@@ -299,6 +299,188 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,\n }\n \n /**\n+ * i40e_parse_cee_pgcfg_tlv\n+ * @tlv: CEE DCBX PG CFG TLV\n+ * @dcbcfg: Local store to update ETS CFG data\n+ *\n+ * Parses CEE DCBX PG CFG TLV\n+ **/\n+static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tstruct i40e_dcb_ets_config *etscfg;\n+\tu8 *buf = tlv->tlvinfo;\n+\tu16 offset = 0;\n+\tu8 priority;\n+\tint i;\n+\n+\tetscfg = &dcbcfg->etscfg;\n+\n+\tif (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)\n+\t\tetscfg->willing = 1;\n+\n+\tetscfg->cbs = 0;\n+\t/* Priority Group Table (4 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 |\n+\t * -----------------------------------------\n+\t * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|\n+\t * -----------------------------------------\n+\t * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|\n+\t * -----------------------------------------\n+\t */\n+\tfor (i = 0; i < 4; i++) {\n+\t\tpriority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>\n+\t\t\t\t I40E_CEE_PGID_PRIO_1_SHIFT);\n+\t\tetscfg->prioritytable[i * 2] = priority;\n+\t\tpriority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>\n+\t\t\t\t I40E_CEE_PGID_PRIO_0_SHIFT);\n+\t\tetscfg->prioritytable[i * 2 + 1] = priority;\n+\t\toffset++;\n+\t}\n+\n+\t/* PG Percentage Table (8 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n+\t * ---------------------------------\n+\t * |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|\n+\t * ---------------------------------\n+\t */\n+\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n+\t\tetscfg->tcbwtable[i] = buf[offset++];\n+\n+\t/* Number of TCs supported (1 octet) */\n+\tetscfg->maxtcs = buf[offset];\n+}\n+\n+/**\n+ * i40e_parse_cee_pfccfg_tlv\n+ * @tlv: CEE DCBX PFC CFG TLV\n+ * @dcbcfg: Local store to update PFC CFG data\n+ *\n+ * Parses CEE DCBX PFC CFG TLV\n+ **/\n+static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu8 *buf = tlv->tlvinfo;\n+\n+\tif (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)\n+\t\tdcbcfg->pfc.willing = 1;\n+\n+\t/* ------------------------\n+\t * | PFC Enable | PFC TCs |\n+\t * ------------------------\n+\t * | 1 octet | 1 octet |\n+\t */\n+\tdcbcfg->pfc.pfcenable = buf[0];\n+\tdcbcfg->pfc.pfccap = buf[1];\n+}\n+\n+/**\n+ * i40e_parse_cee_app_tlv\n+ * @tlv: CEE DCBX APP TLV\n+ * @dcbcfg: Local store to update APP PRIO data\n+ *\n+ * Parses CEE DCBX APP PRIO TLV\n+ **/\n+static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu16 length, typelength, offset = 0;\n+\tstruct i40e_cee_app_prio *app;\n+\tu8 i, up, selector;\n+\n+\ttypelength = I40E_NTOHS(tlv->hdr.typelen);\n+\tlength = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n+\t\t I40E_LLDP_TLV_LEN_SHIFT);\n+\n+\tdcbcfg->numapps = length/sizeof(*app);\n+\tif (!dcbcfg->numapps)\n+\t\treturn;\n+\n+\tfor (i = 0; i < dcbcfg->numapps; i++) {\n+\t\tapp = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);\n+\t\tfor (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {\n+\t\t\tif (app->prio_map & BIT(up))\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tdcbcfg->app[i].priority = up;\n+\t\t/* Get Selector from lower 2 bits, and convert to IEEE */\n+\t\tselector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK);\n+\t\tif (selector == I40E_CEE_APP_SEL_ETHTYPE)\n+\t\t\tdcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;\n+\t\telse if (selector == I40E_CEE_APP_SEL_TCPIP)\n+\t\t\tdcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;\n+\t\telse\n+\t\t\t/* Keep selector as it is for unknown types */\n+\t\t\tdcbcfg->app[i].selector = selector;\n+\t\tdcbcfg->app[i].protocolid = I40E_NTOHS(app->protocol);\n+\t\t/* Move to next app */\n+\t\toffset += sizeof(*app);\n+\t}\n+}\n+\n+/**\n+ * i40e_parse_cee_tlv\n+ * @tlv: CEE DCBX TLV\n+ * @dcbcfg: Local store to update DCBX config data\n+ *\n+ * Get the TLV subtype and send it to parsing function\n+ * based on the subtype value\n+ **/\n+static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,\n+\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu16 len, tlvlen, sublen, typelength;\n+\tstruct i40e_cee_feat_tlv *sub_tlv;\n+\tu8 subtype, feat_tlv_count = 0;\n+\tu32 ouisubtype;\n+\n+\touisubtype = I40E_NTOHL(tlv->ouisubtype);\n+\tsubtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>\n+\t\t I40E_LLDP_TLV_SUBTYPE_SHIFT);\n+\t/* Return if not CEE DCBX */\n+\tif (subtype != I40E_CEE_DCBX_TYPE)\n+\t\treturn;\n+\n+\ttypelength = I40E_NTOHS(tlv->typelength);\n+\ttlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n+\t\t\tI40E_LLDP_TLV_LEN_SHIFT);\n+\tlen = sizeof(tlv->typelength) + sizeof(ouisubtype) +\n+\t sizeof(struct i40e_cee_ctrl_tlv);\n+\t/* Return if no CEE DCBX Feature TLVs */\n+\tif (tlvlen <= len)\n+\t\treturn;\n+\n+\tsub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);\n+\twhile (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {\n+\t\ttypelength = I40E_NTOHS(sub_tlv->hdr.typelen);\n+\t\tsublen = (u16)((typelength &\n+\t\t\t\tI40E_LLDP_TLV_LEN_MASK) >>\n+\t\t\t\tI40E_LLDP_TLV_LEN_SHIFT);\n+\t\tsubtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>\n+\t\t\t\tI40E_LLDP_TLV_TYPE_SHIFT);\n+\t\tswitch (subtype) {\n+\t\tcase I40E_CEE_SUBTYPE_PG_CFG:\n+\t\t\ti40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tcase I40E_CEE_SUBTYPE_PFC_CFG:\n+\t\t\ti40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tcase I40E_CEE_SUBTYPE_APP_PRI:\n+\t\t\ti40e_parse_cee_app_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn; /* Invalid Sub-type return */\n+\t\t}\n+\t\tfeat_tlv_count++;\n+\t\t/* Move to next sub TLV */\n+\t\tsub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +\n+\t\t\t\t\t\tsizeof(sub_tlv->hdr.typelen) +\n+\t\t\t\t\t\tsublen);\n+\t}\n+}\n+\n+/**\n * i40e_parse_org_tlv\n * @tlv: Organization specific TLV\n * @dcbcfg: Local store to update ETS REC data\n@@ -319,6 +501,9 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,\n \tcase I40E_IEEE_8021QAZ_OUI:\n \t\ti40e_parse_ieee_tlv(tlv, dcbcfg);\n \t\tbreak;\n+\tcase I40E_CEE_DCBX_OUI:\n+\t\ti40e_parse_cee_tlv(tlv, dcbcfg);\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -426,7 +611,7 @@ static void i40e_cee_to_dcb_v1_config(\n {\n \tu16 status, tlv_status = LE16_TO_CPU(cee_cfg->tlv_status);\n \tu16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);\n-\tu8 i, tc, err, sync, oper;\n+\tu8 i, tc, err;\n \n \t/* CEE PG data to ETS config */\n \tdcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;\n@@ -466,9 +651,7 @@ static void i40e_cee_to_dcb_v1_config(\n \tstatus = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>\n \t\t I40E_AQC_CEE_APP_STATUS_SHIFT;\n \terr = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;\n-\tsync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;\n-\toper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;\n-\t/* Add APPs if Error is False and Oper/Sync is True */\n+\t/* Add APPs if Error is False */\n \tif (!err) {\n \t\t/* CEE operating configuration supports FCoE/iSCSI/FIP only */\n \t\tdcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;\ndiff --git a/drivers/net/i40e/base/i40e_dcb.h b/drivers/net/i40e/base/i40e_dcb.h\nindex 841cfc3..3aa228b 100644\n--- a/drivers/net/i40e/base/i40e_dcb.h\n+++ b/drivers/net/i40e/base/i40e_dcb.h\n@@ -54,6 +54,15 @@ POSSIBILITY OF SUCH DAMAGE.\n #define I40E_IEEE_SUBTYPE_PFC_CFG\t11\n #define I40E_IEEE_SUBTYPE_APP_PRI\t12\n \n+#define I40E_CEE_DCBX_OUI\t\t0x001b21\n+#define I40E_CEE_DCBX_TYPE\t\t2\n+\n+#define I40E_CEE_SUBTYPE_CTRL\t\t1\n+#define I40E_CEE_SUBTYPE_PG_CFG\t\t2\n+#define I40E_CEE_SUBTYPE_PFC_CFG\t3\n+#define I40E_CEE_SUBTYPE_APP_PRI\t4\n+\n+#define I40E_CEE_MAX_FEAT_TYPE\t\t3\n #define I40E_LLDP_ADMINSTATUS_DISABLED\t\t0\n #define I40E_LLDP_ADMINSTATUS_ENABLED_RX\t1\n #define I40E_LLDP_ADMINSTATUS_ENABLED_TX\t2\n@@ -136,6 +145,36 @@ struct i40e_lldp_org_tlv {\n \t__be32 ouisubtype;\n \tu8 tlvinfo[1];\n };\n+\n+struct i40e_cee_tlv_hdr {\n+\t__be16 typelen;\n+\tu8 operver;\n+\tu8 maxver;\n+};\n+\n+struct i40e_cee_ctrl_tlv {\n+\tstruct i40e_cee_tlv_hdr hdr;\n+\t__be32 seqno;\n+\t__be32 ackno;\n+};\n+\n+struct i40e_cee_feat_tlv {\n+\tstruct i40e_cee_tlv_hdr hdr;\n+\tu8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */\n+#define I40E_CEE_FEAT_TLV_ENABLE_MASK\t0x80\n+#define I40E_CEE_FEAT_TLV_WILLING_MASK\t0x40\n+#define I40E_CEE_FEAT_TLV_ERR_MASK\t0x20\n+\tu8 subtype;\n+\tu8 tlvinfo[1];\n+};\n+\n+struct i40e_cee_app_prio {\n+\t__be16 protocol;\n+\tu8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */\n+#define I40E_CEE_APP_SELECTOR_MASK\t0x03\n+\t__be16 lower_oui;\n+\tu8 prio_map;\n+};\n #pragma pack()\n \n /*\ndiff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h\nindex ccd7992..eb87d54 100644\n--- a/drivers/net/i40e/base/i40e_type.h\n+++ b/drivers/net/i40e/base/i40e_type.h\n@@ -483,6 +483,8 @@ struct i40e_fc_info {\n #define I40E_APP_PROTOID_FIP\t\t0x8914\n #define I40E_APP_SEL_ETHTYPE\t\t0x1\n #define I40E_APP_SEL_TCPIP\t\t0x2\n+#define I40E_CEE_APP_SEL_ETHTYPE\t0x0\n+#define I40E_CEE_APP_SEL_TCPIP\t\t0x1\n \n /* CEE or IEEE 802.1Qaz ETS Configuration data */\n struct i40e_dcb_ets_config {\n", "prefixes": [ "dpdk-dev", "18/52" ] }