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{
    "id": 68493,
    "url": "https://patches.dpdk.org/api/patches/68493/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1586938751-32808-8-git-send-email-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1586938751-32808-8-git-send-email-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1586938751-32808-8-git-send-email-venkatkumar.duvvuru@broadcom.com",
    "date": "2020-04-15T08:18:44",
    "name": "[v4,07/34] net/bnxt: add initial tf core resource mgmt support",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "accc39a546e217532537158c686219f07044eb0e",
    "submitter": {
        "id": 1635,
        "url": "https://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1586938751-32808-8-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 9386,
            "url": "https://patches.dpdk.org/api/series/9386/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9386",
            "date": "2020-04-15T08:18:37",
            "name": "add support for host based flow table management",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/9386/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/68493/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/68493/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Shahaji Bhosle <sbhosle@broadcom.com>",
        "Date": "Wed, 15 Apr 2020 13:48:44 +0530",
        "Message-Id": "\n <1586938751-32808-8-git-send-email-venkatkumar.duvvuru@broadcom.com>",
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        "In-Reply-To": "\n <1586938751-32808-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "References": "\n <1586852011-37536-1-git-send-email-venkatkumar.duvvuru@broadcom.com>\n <1586938751-32808-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
        "Subject": "[dpdk-dev] [PATCH v4 07/34] net/bnxt: add initial tf core resource\n\tmgmt support",
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    },
    "content": "From: Shahaji Bhosle <sbhosle@broadcom.com>\n\n- Add TruFlow public API definitions for resources\n  as well as RM infrastructure\n\nSigned-off-by: Shahaji Bhosle <sbhosle@broadcom.com>\nReviewed-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/Makefile             |    1 +\n drivers/net/bnxt/tf_core/tf_core.c    |   40 +\n drivers/net/bnxt/tf_core/tf_core.h    |  125 +++\n drivers/net/bnxt/tf_core/tf_rm.c      | 1731 +++++++++++++++++++++++++++++++++\n drivers/net/bnxt/tf_core/tf_rm.h      |  175 ++++\n drivers/net/bnxt/tf_core/tf_session.h |  206 +++-\n 6 files changed, 2277 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/bnxt/tf_core/tf_rm.c",
    "diff": "diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile\nindex c39c098..02f8c3f 100644\n--- a/drivers/net/bnxt/Makefile\n+++ b/drivers/net/bnxt/Makefile\n@@ -51,6 +51,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_core.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/bitalloc.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_msg.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/rand.c\n+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tf_rm.c\n SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += tf_core/tfp.c\n \n #\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c\nindex d82f746..7d76efa 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.c\n+++ b/drivers/net/bnxt/tf_core/tf_core.c\n@@ -20,6 +20,29 @@ static inline uint32_t SWAP_WORDS32(uint32_t val32)\n \t\t((val32 & 0xffff0000) >> 16));\n }\n \n+static void tf_seeds_init(struct tf_session *session)\n+{\n+\tint i;\n+\tuint32_t r;\n+\n+\t/* Initialize the lfsr */\n+\trand_init();\n+\n+\t/* RX and TX use the same seed values */\n+\tsession->lkup_lkup3_init_cfg[TF_DIR_RX] =\n+\t\tsession->lkup_lkup3_init_cfg[TF_DIR_TX] =\n+\t\t\t\t\t\tSWAP_WORDS32(rand32());\n+\n+\tfor (i = 0; i < TF_LKUP_SEED_MEM_SIZE / 2; i++) {\n+\t\tr = SWAP_WORDS32(rand32());\n+\t\tsession->lkup_em_seed_mem[TF_DIR_RX][i * 2] = r;\n+\t\tsession->lkup_em_seed_mem[TF_DIR_TX][i * 2] = r;\n+\t\tr = SWAP_WORDS32(rand32());\n+\t\tsession->lkup_em_seed_mem[TF_DIR_RX][i * 2 + 1] = (r & 0x1);\n+\t\tsession->lkup_em_seed_mem[TF_DIR_TX][i * 2 + 1] = (r & 0x1);\n+\t}\n+}\n+\n int\n tf_open_session(struct tf                    *tfp,\n \t\tstruct tf_open_session_parms *parms)\n@@ -109,6 +132,7 @@ tf_open_session(struct tf                    *tfp,\n \n \t/* Initialize Session */\n \tsession->device_type = parms->device_type;\n+\ttf_rm_init(tfp);\n \n \t/* Construct the Session ID */\n \tsession->session_id.internal.domain = domain;\n@@ -125,6 +149,16 @@ tf_open_session(struct tf                    *tfp,\n \t\tgoto cleanup_close;\n \t}\n \n+\t/* Adjust the Session with what firmware allowed us to get */\n+\trc = tf_rm_allocate_validate(tfp);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tgoto cleanup_close;\n+\t}\n+\n+\t/* Setup hash seeds */\n+\ttf_seeds_init(session);\n+\n \tsession->ref_count++;\n \n \t/* Return session ID */\n@@ -195,6 +229,12 @@ tf_close_session(struct tf *tfp)\n \n \ttfs = (struct tf_session *)(tfp->session->core_data);\n \n+\t/* Cleanup if we're last user of the session */\n+\tif (tfs->ref_count == 1) {\n+\t\t/* Cleanup any outstanding resources */\n+\t\trc_close = tf_rm_close(tfp);\n+\t}\n+\n \tif (tfs->session_id.id != TF_SESSION_ID_INVALID) {\n \t\trc = tf_msg_session_close(tfp);\n \t\tif (rc) {\ndiff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h\nindex 69433ac..3455d8f 100644\n--- a/drivers/net/bnxt/tf_core/tf_core.h\n+++ b/drivers/net/bnxt/tf_core/tf_core.h\n@@ -344,4 +344,129 @@ int tf_attach_session(struct tf *tfp,\n  */\n int tf_close_session(struct tf *tfp);\n \n+/**\n+ * @page  ident Identity Management\n+ *\n+ * @ref tf_alloc_identifier\n+ *\n+ * @ref tf_free_identifier\n+ */\n+enum tf_identifier_type {\n+\t/** The L2 Context is returned from the L2 Ctxt TCAM lookup\n+\t *  and can be used in WC TCAM or EM keys to virtualize further\n+\t *  lookups.\n+\t */\n+\tTF_IDENT_TYPE_L2_CTXT,\n+\t/** The WC profile func is returned from the L2 Ctxt TCAM lookup\n+\t *  to enable virtualization of the profile TCAM.\n+\t */\n+\tTF_IDENT_TYPE_PROF_FUNC,\n+\t/** The WC profile ID is included in the WC lookup key\n+\t *  to enable virtualization of the WC TCAM hardware.\n+\t */\n+\tTF_IDENT_TYPE_WC_PROF,\n+\t/** The EM profile ID is included in the EM lookup key\n+\t *  to enable virtualization of the EM hardware. (not required for Brd4\n+\t *  as it has table scope)\n+\t */\n+\tTF_IDENT_TYPE_EM_PROF,\n+\t/** The L2 func is included in the ILT result and from recycling to\n+\t *  enable virtualization of further lookups.\n+\t */\n+\tTF_IDENT_TYPE_L2_FUNC\n+};\n+\n+/**\n+ * TCAM table type\n+ */\n+enum tf_tcam_tbl_type {\n+\tTF_TCAM_TBL_TYPE_L2_CTXT_TCAM,\n+\tTF_TCAM_TBL_TYPE_PROF_TCAM,\n+\tTF_TCAM_TBL_TYPE_WC_TCAM,\n+\tTF_TCAM_TBL_TYPE_SP_TCAM,\n+\tTF_TCAM_TBL_TYPE_CT_RULE_TCAM,\n+\tTF_TCAM_TBL_TYPE_VEB_TCAM,\n+\tTF_TCAM_TBL_TYPE_MAX\n+\n+};\n+\n+/**\n+ * Enumeration of TruFlow table types. A table type is used to identify a\n+ * resource object.\n+ *\n+ * NOTE: The table type TF_TBL_TYPE_EXT is unique in that it is\n+ * the only table type that is connected with a table scope.\n+ */\n+enum tf_tbl_type {\n+\t/** Wh+/Brd2 Action Record */\n+\tTF_TBL_TYPE_FULL_ACT_RECORD,\n+\t/** Multicast Groups */\n+\tTF_TBL_TYPE_MCAST_GROUPS,\n+\t/** Action Encap 8 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_8B,\n+\t/** Action Encap 16 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_16B,\n+\t/** Action Encap 64 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_32B,\n+\t/** Action Encap 64 Bytes */\n+\tTF_TBL_TYPE_ACT_ENCAP_64B,\n+\t/** Action Source Properties SMAC */\n+\tTF_TBL_TYPE_ACT_SP_SMAC,\n+\t/** Action Source Properties SMAC IPv4 */\n+\tTF_TBL_TYPE_ACT_SP_SMAC_IPV4,\n+\t/** Action Source Properties SMAC IPv6 */\n+\tTF_TBL_TYPE_ACT_SP_SMAC_IPV6,\n+\t/** Action Statistics 64 Bits */\n+\tTF_TBL_TYPE_ACT_STATS_64,\n+\t/** Action Modify L4 Src Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_SPORT,\n+\t/** Action Modify L4 Dest Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_DPORT,\n+\t/** Action Modify IPv4 Source */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV4_SRC,\n+\t/** Action _Modify L4 Dest Port */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV4_DEST,\n+\t/** Action Modify IPv6 Source */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV6_SRC,\n+\t/** Action Modify IPv6 Destination */\n+\tTF_TBL_TYPE_ACT_MODIFY_IPV6_DEST,\n+\n+\t/* HW */\n+\n+\t/** Meter Profiles */\n+\tTF_TBL_TYPE_METER_PROF,\n+\t/** Meter Instance */\n+\tTF_TBL_TYPE_METER_INST,\n+\t/** Mirror Config */\n+\tTF_TBL_TYPE_MIRROR_CONFIG,\n+\t/** UPAR */\n+\tTF_TBL_TYPE_UPAR,\n+\t/** Brd4 Epoch 0 table */\n+\tTF_TBL_TYPE_EPOCH0,\n+\t/** Brd4 Epoch 1 table  */\n+\tTF_TBL_TYPE_EPOCH1,\n+\t/** Brd4 Metadata  */\n+\tTF_TBL_TYPE_METADATA,\n+\t/** Brd4 CT State  */\n+\tTF_TBL_TYPE_CT_STATE,\n+\t/** Brd4 Range Profile  */\n+\tTF_TBL_TYPE_RANGE_PROF,\n+\t/** Brd4 Range Entry  */\n+\tTF_TBL_TYPE_RANGE_ENTRY,\n+\t/** Brd4 LAG Entry  */\n+\tTF_TBL_TYPE_LAG,\n+\t/** Brd4 only VNIC/SVIF Table */\n+\tTF_TBL_TYPE_VNIC_SVIF,\n+\n+\t/* External */\n+\n+\t/** External table type - initially 1 poolsize entries.\n+\t * All External table types are associated with a table\n+\t * scope. Internal types are not.\n+\t */\n+\tTF_TBL_TYPE_EXT,\n+\t/** Future - external pool of size0 entries */\n+\tTF_TBL_TYPE_EXT_0,\n+\tTF_TBL_TYPE_MAX\n+};\n #endif /* _TF_CORE_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c\nnew file mode 100644\nindex 0000000..56767e7\n--- /dev/null\n+++ b/drivers/net/bnxt/tf_core/tf_rm.c\n@@ -0,0 +1,1731 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019-2020 Broadcom\n+ * All rights reserved.\n+ */\n+\n+#include <string.h>\n+\n+#include <rte_common.h>\n+\n+#include \"tf_rm.h\"\n+#include \"tf_core.h\"\n+#include \"tf_session.h\"\n+#include \"tf_resources.h\"\n+#include \"tf_msg.h\"\n+#include \"bnxt.h\"\n+\n+/**\n+ * Internal macro to perform HW resource allocation check between what\n+ * firmware reports vs what was statically requested.\n+ *\n+ * Parameters:\n+ *   struct tf_rm_hw_query    *hquery      - Pointer to the hw query result\n+ *   enum tf_dir               dir         - Direction to process\n+ *   enum tf_resource_type_hw  hcapi_type  - HCAPI type, the index element\n+ *                                           in the hw query structure\n+ *   define                    def_value   - Define value to check against\n+ *   uint32_t                 *eflag       - Result of the check\n+ */\n+#define TF_RM_CHECK_HW_ALLOC(hquery, dir, hcapi_type, def_value, eflag) do {  \\\n+\tif ((dir) == TF_DIR_RX) {\t\t\t\t\t      \\\n+\t\tif ((hquery)->hw_query[(hcapi_type)].max != def_value ## _RX) \\\n+\t\t\t*(eflag) |= 1 << (hcapi_type);\t\t\t      \\\n+\t} else {\t\t\t\t\t\t\t      \\\n+\t\tif ((hquery)->hw_query[(hcapi_type)].max != def_value ## _TX) \\\n+\t\t\t*(eflag) |= 1 << (hcapi_type);\t\t\t      \\\n+\t}\t\t\t\t\t\t\t\t      \\\n+} while (0)\n+\n+/**\n+ * Internal macro to perform HW resource allocation check between what\n+ * firmware reports vs what was statically requested.\n+ *\n+ * Parameters:\n+ *   struct tf_rm_sram_query   *squery      - Pointer to the sram query result\n+ *   enum tf_dir                dir         - Direction to process\n+ *   enum tf_resource_type_sram hcapi_type  - HCAPI type, the index element\n+ *                                            in the hw query structure\n+ *   define                     def_value   - Define value to check against\n+ *   uint32_t                  *eflag       - Result of the check\n+ */\n+#define TF_RM_CHECK_SRAM_ALLOC(squery, dir, hcapi_type, def_value, eflag) do { \\\n+\tif ((dir) == TF_DIR_RX) {\t\t\t\t\t       \\\n+\t\tif ((squery)->sram_query[(hcapi_type)].max != def_value ## _RX)\\\n+\t\t\t*(eflag) |= 1 << (hcapi_type);\t\t\t       \\\n+\t} else {\t\t\t\t\t\t\t       \\\n+\t\tif ((squery)->sram_query[(hcapi_type)].max != def_value ## _TX)\\\n+\t\t\t*(eflag) |= 1 << (hcapi_type);\t\t\t       \\\n+\t}\t\t\t\t\t\t\t\t       \\\n+} while (0)\n+\n+/**\n+ * Internal macro to convert a reserved resource define name to be\n+ * direction specific.\n+ *\n+ * Parameters:\n+ *   enum tf_dir    dir         - Direction to process\n+ *   string         type        - Type name to append RX or TX to\n+ *   string         dtype       - Direction specific type\n+ *\n+ *\n+ */\n+#define TF_RESC_RSVD(dir, type, dtype) do {\t\\\n+\t\tif ((dir) == TF_DIR_RX)\t\t\\\n+\t\t\t(dtype) = type ## _RX;\t\\\n+\t\telse\t\t\t\t\\\n+\t\t\t(dtype) = type ## _TX;\t\\\n+\t} while (0)\n+\n+const char\n+*tf_dir_2_str(enum tf_dir dir)\n+{\n+\tswitch (dir) {\n+\tcase TF_DIR_RX:\n+\t\treturn \"RX\";\n+\tcase TF_DIR_TX:\n+\t\treturn \"TX\";\n+\tdefault:\n+\t\treturn \"Invalid direction\";\n+\t}\n+}\n+\n+const char\n+*tf_ident_2_str(enum tf_identifier_type id_type)\n+{\n+\tswitch (id_type) {\n+\tcase TF_IDENT_TYPE_L2_CTXT:\n+\t\treturn \"l2_ctxt_remap\";\n+\tcase TF_IDENT_TYPE_PROF_FUNC:\n+\t\treturn \"prof_func\";\n+\tcase TF_IDENT_TYPE_WC_PROF:\n+\t\treturn \"wc_prof\";\n+\tcase TF_IDENT_TYPE_EM_PROF:\n+\t\treturn \"em_prof\";\n+\tcase TF_IDENT_TYPE_L2_FUNC:\n+\t\treturn \"l2_func\";\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn \"Invalid identifier\";\n+}\n+\n+const char\n+*tf_hcapi_sram_2_str(enum tf_resource_type_sram sram_type)\n+{\n+\tswitch (sram_type) {\n+\tcase TF_RESC_TYPE_SRAM_FULL_ACTION:\n+\t\treturn \"Full action\";\n+\tcase TF_RESC_TYPE_SRAM_MCG:\n+\t\treturn \"MCG\";\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_8B:\n+\t\treturn \"Encap 8B\";\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_16B:\n+\t\treturn \"Encap 16B\";\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_64B:\n+\t\treturn \"Encap 64B\";\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC:\n+\t\treturn \"Source properties SMAC\";\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC_IPV4:\n+\t\treturn \"Source properties SMAC IPv4\";\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC_IPV6:\n+\t\treturn \"Source properties IPv6\";\n+\tcase TF_RESC_TYPE_SRAM_COUNTER_64B:\n+\t\treturn \"Counter 64B\";\n+\tcase TF_RESC_TYPE_SRAM_NAT_SPORT:\n+\t\treturn \"NAT source port\";\n+\tcase TF_RESC_TYPE_SRAM_NAT_DPORT:\n+\t\treturn \"NAT destination port\";\n+\tcase TF_RESC_TYPE_SRAM_NAT_S_IPV4:\n+\t\treturn \"NAT source IPv4\";\n+\tcase TF_RESC_TYPE_SRAM_NAT_D_IPV4:\n+\t\treturn \"NAT destination IPv4\";\n+\tdefault:\n+\t\treturn \"Invalid identifier\";\n+\t}\n+}\n+\n+/**\n+ * Helper function to perform a SRAM HCAPI resource type lookup\n+ * against the reserved value of the same static type.\n+ *\n+ * Returns:\n+ *   -EOPNOTSUPP - Reserved resource type not supported\n+ *   Value       - Integer value of the reserved value for the requested type\n+ */\n+static int\n+tf_rm_rsvd_sram_value(enum tf_dir dir, enum tf_resource_type_sram index)\n+{\n+\tuint32_t value = -EOPNOTSUPP;\n+\n+\tswitch (index) {\n+\tcase TF_RESC_TYPE_SRAM_FULL_ACTION:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_FULL_ACTION, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_MCG:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_MCG, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_8B:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_ENCAP_8B, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_16B:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_ENCAP_16B, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_ENCAP_64B:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_ENCAP_64B, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_SP_SMAC, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC_IPV4:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_SP_SMAC_IPV4, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_SP_SMAC_IPV6:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_SP_SMAC_IPV6, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_COUNTER_64B:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_COUNTER_64B, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_NAT_SPORT:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_NAT_SPORT, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_NAT_DPORT:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_NAT_DPORT, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_NAT_S_IPV4:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_NAT_S_IPV4, value);\n+\t\tbreak;\n+\tcase TF_RESC_TYPE_SRAM_NAT_D_IPV4:\n+\t\tTF_RESC_RSVD(dir, TF_RSVD_SRAM_NAT_D_IPV4, value);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn value;\n+}\n+\n+/**\n+ * Helper function to print all the SRAM resource qcaps errors\n+ * reported in the error_flag.\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [in] error_flag\n+ *   Pointer to the sram error flags created at time of the query check\n+ */\n+static void\n+tf_rm_print_sram_qcaps_error(enum tf_dir dir,\n+\t\t\t     struct tf_rm_sram_query *sram_query,\n+\t\t\t     uint32_t *error_flag)\n+{\n+\tint i;\n+\n+\tPMD_DRV_LOG(ERR, \"QCAPS errors SRAM\\n\");\n+\tPMD_DRV_LOG(ERR, \"  Direction: %s\\n\", tf_dir_2_str(dir));\n+\tPMD_DRV_LOG(ERR, \"  Elements:\\n\");\n+\n+\tfor (i = 0; i < TF_RESC_TYPE_SRAM_MAX; i++) {\n+\t\tif (*error_flag & 1 << i)\n+\t\t\tPMD_DRV_LOG(ERR, \"    %s, %d elem available, req:%d\\n\",\n+\t\t\t\t    tf_hcapi_sram_2_str(i),\n+\t\t\t\t    sram_query->sram_query[i].max,\n+\t\t\t\t    tf_rm_rsvd_sram_value(dir, i));\n+\t}\n+}\n+\n+/**\n+ * Performs a HW resource check between what firmware capability\n+ * reports and what the core expects is available.\n+ *\n+ * Firmware performs the resource carving at AFM init time and the\n+ * resource capability is reported in the TruFlow qcaps msg.\n+ *\n+ * [in] query\n+ *   Pointer to HW Query data structure. Query holds what the firmware\n+ *   offers of the HW resources.\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [in/out] error_flag\n+ *   Pointer to a bit array indicating the error of a single HCAPI\n+ *   resource type. When a bit is set to 1, the HCAPI resource type\n+ *   failed static allocation.\n+ *\n+ * Returns:\n+ *  0       - Success\n+ *  -ENOMEM - Failure on one of the allocated resources. Check the\n+ *            error_flag for what types are flagged errored.\n+ */\n+static int\n+tf_rm_check_hw_qcaps_static(struct tf_rm_hw_query *query,\n+\t\t\t    enum tf_dir dir,\n+\t\t\t    uint32_t *error_flag)\n+{\n+\t*error_flag = 0;\n+\tTF_RM_CHECK_HW_ALLOC(query,\n+\t\t\t     dir,\n+\t\t\t     TF_RESC_TYPE_HW_RANGE_ENTRY,\n+\t\t\t     TF_RSVD_RANGE_ENTRY,\n+\t\t\t     error_flag);\n+\n+\tif (*error_flag != 0)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Performs a SRAM resource check between what firmware capability\n+ * reports and what the core expects is available.\n+ *\n+ * Firmware performs the resource carving at AFM init time and the\n+ * resource capability is reported in the TruFlow qcaps msg.\n+ *\n+ * [in] query\n+ *   Pointer to SRAM Query data structure. Query holds what the\n+ *   firmware offers of the SRAM resources.\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [in/out] error_flag\n+ *   Pointer to a bit array indicating the error of a single HCAPI\n+ *   resource type. When a bit is set to 1, the HCAPI resource type\n+ *   failed static allocation.\n+ *\n+ * Returns:\n+ *  0       - Success\n+ *  -ENOMEM - Failure on one of the allocated resources. Check the\n+ *            error_flag for what types are flagged errored.\n+ */\n+static int\n+tf_rm_check_sram_qcaps_static(struct tf_rm_sram_query *query,\n+\t\t\t      enum tf_dir dir,\n+\t\t\t      uint32_t *error_flag)\n+{\n+\t*error_flag = 0;\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_FULL_ACTION,\n+\t\t\t       TF_RSVD_SRAM_FULL_ACTION,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_MCG,\n+\t\t\t       TF_RSVD_SRAM_MCG,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_ENCAP_8B,\n+\t\t\t       TF_RSVD_SRAM_ENCAP_8B,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_ENCAP_16B,\n+\t\t\t       TF_RSVD_SRAM_ENCAP_16B,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_ENCAP_64B,\n+\t\t\t       TF_RSVD_SRAM_ENCAP_64B,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_SP_SMAC,\n+\t\t\t       TF_RSVD_SRAM_SP_SMAC,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_SP_SMAC_IPV4,\n+\t\t\t       TF_RSVD_SRAM_SP_SMAC_IPV4,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_SP_SMAC_IPV6,\n+\t\t\t       TF_RSVD_SRAM_SP_SMAC_IPV6,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_COUNTER_64B,\n+\t\t\t       TF_RSVD_SRAM_COUNTER_64B,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_NAT_SPORT,\n+\t\t\t       TF_RSVD_SRAM_NAT_SPORT,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_NAT_DPORT,\n+\t\t\t       TF_RSVD_SRAM_NAT_DPORT,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_NAT_S_IPV4,\n+\t\t\t       TF_RSVD_SRAM_NAT_S_IPV4,\n+\t\t\t       error_flag);\n+\n+\tTF_RM_CHECK_SRAM_ALLOC(query,\n+\t\t\t       dir,\n+\t\t\t       TF_RESC_TYPE_SRAM_NAT_D_IPV4,\n+\t\t\t       TF_RSVD_SRAM_NAT_D_IPV4,\n+\t\t\t       error_flag);\n+\n+\tif (*error_flag != 0)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * Internal function to mark pool entries used.\n+ */\n+static void\n+tf_rm_reserve_range(uint32_t count,\n+\t\t    uint32_t rsv_begin,\n+\t\t    uint32_t rsv_end,\n+\t\t    uint32_t max,\n+\t\t    struct bitalloc *pool)\n+{\n+\tuint32_t i;\n+\n+\t/* If no resources has been requested we mark everything\n+\t * 'used'\n+\t */\n+\tif (count == 0)\t{\n+\t\tfor (i = 0; i < max; i++)\n+\t\t\tba_alloc_index(pool, i);\n+\t} else {\n+\t\t/* Support 2 main modes\n+\t\t * Reserved range starts from bottom up (with\n+\t\t * pre-reserved value or not)\n+\t\t * - begin = 0 to end xx\n+\t\t * - begin = 1 to end xx\n+\t\t *\n+\t\t * Reserved range starts from top down\n+\t\t * - begin = yy to end max\n+\t\t */\n+\n+\t\t/* Bottom up check, start from 0 */\n+\t\tif (rsv_begin == 0) {\n+\t\t\tfor (i = rsv_end + 1; i < max; i++)\n+\t\t\t\tba_alloc_index(pool, i);\n+\t\t}\n+\n+\t\t/* Bottom up check, start from 1 or higher OR\n+\t\t * Top Down\n+\t\t */\n+\t\tif (rsv_begin >= 1) {\n+\t\t\t/* Allocate from 0 until start */\n+\t\t\tfor (i = 0; i < rsv_begin; i++)\n+\t\t\t\tba_alloc_index(pool, i);\n+\n+\t\t\t/* Skip and then do the remaining */\n+\t\t\tif (rsv_end < max - 1) {\n+\t\t\t\tfor (i = rsv_end; i < max; i++)\n+\t\t\t\t\tba_alloc_index(pool, i);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * Internal function to mark all the l2 ctxt allocated that Truflow\n+ * does not own.\n+ */\n+static void\n+tf_rm_rsvd_l2_ctxt(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_HW_L2_CTXT_TCAM;\n+\tuint32_t end = 0;\n+\n+\t/* l2 ctxt rx direction */\n+\tif (tfs->resc.rx.hw_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.hw_entry[index].start +\n+\t\t\ttfs->resc.rx.hw_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.hw_entry[index].stride,\n+\t\t\t    tfs->resc.rx.hw_entry[index].start,\n+\t\t\t    end,\n+\t\t\t    TF_NUM_L2_CTXT_TCAM,\n+\t\t\t    tfs->TF_L2_CTXT_TCAM_POOL_NAME_RX);\n+\n+\t/* l2 ctxt tx direction */\n+\tif (tfs->resc.tx.hw_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.hw_entry[index].start +\n+\t\t\ttfs->resc.tx.hw_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.hw_entry[index].stride,\n+\t\t\t    tfs->resc.tx.hw_entry[index].start,\n+\t\t\t    end,\n+\t\t\t    TF_NUM_L2_CTXT_TCAM,\n+\t\t\t    tfs->TF_L2_CTXT_TCAM_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the l2 func resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_l2_func(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_HW_L2_FUNC;\n+\tuint32_t end = 0;\n+\n+\t/* l2 func rx direction */\n+\tif (tfs->resc.rx.hw_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.hw_entry[index].start +\n+\t\t\ttfs->resc.rx.hw_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.hw_entry[index].stride,\n+\t\t\t    tfs->resc.rx.hw_entry[index].start,\n+\t\t\t    end,\n+\t\t\t    TF_NUM_L2_FUNC,\n+\t\t\t    tfs->TF_L2_FUNC_POOL_NAME_RX);\n+\n+\t/* l2 func tx direction */\n+\tif (tfs->resc.tx.hw_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.hw_entry[index].start +\n+\t\t\ttfs->resc.tx.hw_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.hw_entry[index].stride,\n+\t\t\t    tfs->resc.tx.hw_entry[index].start,\n+\t\t\t    end,\n+\t\t\t    TF_NUM_L2_FUNC,\n+\t\t\t    tfs->TF_L2_FUNC_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the full action resources allocated\n+ * that Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_full_action(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_FULL_ACTION;\n+\tuint16_t end = 0;\n+\n+\t/* full action rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_FULL_ACTION_RX,\n+\t\t\t    tfs->TF_SRAM_FULL_ACTION_POOL_NAME_RX);\n+\n+\t/* full action tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_FULL_ACTION_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_FULL_ACTION_TX,\n+\t\t\t    tfs->TF_SRAM_FULL_ACTION_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the multicast group resources\n+ * allocated that Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_mcg(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_MCG;\n+\tuint16_t end = 0;\n+\n+\t/* multicast group rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_MCG_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_MCG_RX,\n+\t\t\t    tfs->TF_SRAM_MCG_POOL_NAME_RX);\n+\n+\t/* Multicast Group on TX is not supported */\n+}\n+\n+/**\n+ * Internal function to mark all the encap resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_encap(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_ENCAP_8B;\n+\tuint16_t end = 0;\n+\n+\t/* encap 8b rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_8B_RX,\n+\t\t\t    tfs->TF_SRAM_ENCAP_8B_POOL_NAME_RX);\n+\n+\t/* encap 8b tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_8B_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_8B_TX,\n+\t\t\t    tfs->TF_SRAM_ENCAP_8B_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_ENCAP_16B;\n+\n+\t/* encap 16b rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_16B_RX,\n+\t\t\t    tfs->TF_SRAM_ENCAP_16B_POOL_NAME_RX);\n+\n+\t/* encap 16b tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_16B_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_16B_TX,\n+\t\t\t    tfs->TF_SRAM_ENCAP_16B_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_ENCAP_64B;\n+\n+\t/* Encap 64B not supported on RX */\n+\n+\t/* Encap 64b tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_64B_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_ENCAP_64B_TX,\n+\t\t\t    tfs->TF_SRAM_ENCAP_64B_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the sp resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_sp(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_SP_SMAC;\n+\tuint16_t end = 0;\n+\n+\t/* sp smac rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_RX,\n+\t\t\t    tfs->TF_SRAM_SP_SMAC_POOL_NAME_RX);\n+\n+\t/* sp smac tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_TX,\n+\t\t\t    tfs->TF_SRAM_SP_SMAC_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_SP_SMAC_IPV4;\n+\n+\t/* SP SMAC IPv4 not supported on RX */\n+\n+\t/* sp smac ipv4 tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_IPV4_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_IPV4_TX,\n+\t\t\t    tfs->TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_SP_SMAC_IPV6;\n+\n+\t/* SP SMAC IPv6 not supported on RX */\n+\n+\t/* sp smac ipv6 tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_IPV6_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_SP_SMAC_IPV6_TX,\n+\t\t\t    tfs->TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the stat resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_stats(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_COUNTER_64B;\n+\tuint16_t end = 0;\n+\n+\t/* counter 64b rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_COUNTER_64B_RX,\n+\t\t\t    tfs->TF_SRAM_STATS_64B_POOL_NAME_RX);\n+\n+\t/* counter 64b tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_COUNTER_64B_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_COUNTER_64B_TX,\n+\t\t\t    tfs->TF_SRAM_STATS_64B_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function to mark all the nat resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_rsvd_sram_nat(struct tf_session *tfs)\n+{\n+\tuint32_t index = TF_RESC_TYPE_SRAM_NAT_SPORT;\n+\tuint16_t end = 0;\n+\n+\t/* nat source port rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_SPORT_RX,\n+\t\t\t    tfs->TF_SRAM_NAT_SPORT_POOL_NAME_RX);\n+\n+\t/* nat source port tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_SPORT_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_SPORT_TX,\n+\t\t\t    tfs->TF_SRAM_NAT_SPORT_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_NAT_DPORT;\n+\n+\t/* nat destination port rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_DPORT_RX,\n+\t\t\t    tfs->TF_SRAM_NAT_DPORT_POOL_NAME_RX);\n+\n+\t/* nat destination port tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_DPORT_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_DPORT_TX,\n+\t\t\t    tfs->TF_SRAM_NAT_DPORT_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_NAT_S_IPV4;\n+\n+\t/* nat source port ipv4 rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_S_IPV4_RX,\n+\t\t\t    tfs->TF_SRAM_NAT_S_IPV4_POOL_NAME_RX);\n+\n+\t/* nat source ipv4 port tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_S_IPV4_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_S_IPV4_TX,\n+\t\t\t    tfs->TF_SRAM_NAT_S_IPV4_POOL_NAME_TX);\n+\n+\tindex = TF_RESC_TYPE_SRAM_NAT_D_IPV4;\n+\n+\t/* nat destination port ipv4 rx direction */\n+\tif (tfs->resc.rx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.rx.sram_entry[index].start +\n+\t\t\ttfs->resc.rx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.rx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_RX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_D_IPV4_RX,\n+\t\t\t    tfs->TF_SRAM_NAT_D_IPV4_POOL_NAME_RX);\n+\n+\t/* nat destination ipv4 port tx direction */\n+\tif (tfs->resc.tx.sram_entry[index].stride > 0)\n+\t\tend = tfs->resc.tx.sram_entry[index].start +\n+\t\t\ttfs->resc.tx.sram_entry[index].stride - 1;\n+\n+\ttf_rm_reserve_range(tfs->resc.tx.sram_entry[index].stride,\n+\t\t\t    TF_RSVD_SRAM_NAT_D_IPV4_BEGIN_IDX_TX,\n+\t\t\t    end,\n+\t\t\t    TF_RSVD_SRAM_NAT_D_IPV4_TX,\n+\t\t\t    tfs->TF_SRAM_NAT_D_IPV4_POOL_NAME_TX);\n+}\n+\n+/**\n+ * Internal function used to validate the HW allocated resources\n+ * against the requested values.\n+ */\n+static int\n+tf_rm_hw_alloc_validate(enum tf_dir dir,\n+\t\t\tstruct tf_rm_hw_alloc *hw_alloc,\n+\t\t\tstruct tf_rm_entry *hw_entry)\n+{\n+\tint error = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < TF_RESC_TYPE_HW_MAX; i++) {\n+\t\tif (hw_entry[i].stride != hw_alloc->hw_num[i]) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"%s, Alloc failed id:%d expect:%d got:%d\\n\",\n+\t\t\t\ttf_dir_2_str(dir),\n+\t\t\t\ti,\n+\t\t\t\thw_alloc->hw_num[i],\n+\t\t\t\thw_entry[i].stride);\n+\t\t\terror = -1;\n+\t\t}\n+\t}\n+\n+\treturn error;\n+}\n+\n+/**\n+ * Internal function used to validate the SRAM allocated resources\n+ * against the requested values.\n+ */\n+static int\n+tf_rm_sram_alloc_validate(enum tf_dir dir __rte_unused,\n+\t\t\t  struct tf_rm_sram_alloc *sram_alloc,\n+\t\t\t  struct tf_rm_entry *sram_entry)\n+{\n+\tint error = 0;\n+\tint i;\n+\n+\tfor (i = 0; i < TF_RESC_TYPE_SRAM_MAX; i++) {\n+\t\tif (sram_entry[i].stride != sram_alloc->sram_num[i]) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"%s, Alloc failed idx:%d expect:%d got:%d\\n\",\n+\t\t\t\ttf_dir_2_str(dir),\n+\t\t\t\ti,\n+\t\t\t\tsram_alloc->sram_num[i],\n+\t\t\t\tsram_entry[i].stride);\n+\t\t\terror = -1;\n+\t\t}\n+\t}\n+\n+\treturn error;\n+}\n+\n+/**\n+ * Internal function used to mark all the HW resources allocated that\n+ * Truflow does not own.\n+ */\n+static void\n+tf_rm_reserve_hw(struct tf *tfp)\n+{\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* TBD\n+\t * There is no direct AFM resource allocation as it is carved\n+\t * statically at AFM boot time. Thus the bit allocators work\n+\t * on the full HW resource amount and we just mark everything\n+\t * used except the resources that Truflow took ownership off.\n+\t */\n+\ttf_rm_rsvd_l2_ctxt(tfs);\n+\ttf_rm_rsvd_l2_func(tfs);\n+}\n+\n+/**\n+ * Internal function used to mark all the SRAM resources allocated\n+ * that Truflow does not own.\n+ */\n+static void\n+tf_rm_reserve_sram(struct tf *tfp)\n+{\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\n+\t/* TBD\n+\t * There is no direct AFM resource allocation as it is carved\n+\t * statically at AFM boot time. Thus the bit allocators work\n+\t * on the full HW resource amount and we just mark everything\n+\t * used except the resources that Truflow took ownership off.\n+\t */\n+\ttf_rm_rsvd_sram_full_action(tfs);\n+\ttf_rm_rsvd_sram_mcg(tfs);\n+\ttf_rm_rsvd_sram_encap(tfs);\n+\ttf_rm_rsvd_sram_sp(tfs);\n+\ttf_rm_rsvd_sram_stats(tfs);\n+\ttf_rm_rsvd_sram_nat(tfs);\n+}\n+\n+/**\n+ * Internal function used to allocate and validate all HW resources.\n+ */\n+static int\n+tf_rm_allocate_validate_hw(struct tf *tfp,\n+\t\t\t   enum tf_dir dir)\n+{\n+\tint rc;\n+\tint i;\n+\tstruct tf_rm_hw_query hw_query;\n+\tstruct tf_rm_hw_alloc hw_alloc;\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\tstruct tf_rm_entry *hw_entries;\n+\tuint32_t error_flag;\n+\n+\tif (dir == TF_DIR_RX)\n+\t\thw_entries = tfs->resc.rx.hw_entry;\n+\telse\n+\t\thw_entries = tfs->resc.tx.hw_entry;\n+\n+\t/* Query for Session HW Resources */\n+\trc = tf_msg_session_hw_resc_qcaps(tfp, dir, &hw_query);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, HW qcaps message send failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\trc = tf_rm_check_hw_qcaps_static(&hw_query, dir, &error_flag);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"%s, HW QCAPS validation failed, error_flag:0x%x\\n\",\n+\t\t\ttf_dir_2_str(dir),\n+\t\t\terror_flag);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Post process HW capability */\n+\tfor (i = 0; i < TF_RESC_TYPE_HW_MAX; i++)\n+\t\thw_alloc.hw_num[i] = hw_query.hw_query[i].max;\n+\n+\t/* Allocate Session HW Resources */\n+\trc = tf_msg_session_hw_resc_alloc(tfp, dir, &hw_alloc, hw_entries);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, HW alloc message send failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Perform HW allocation validation as its possible the\n+\t * resource availability changed between qcaps and alloc\n+\t */\n+\trc = tf_rm_hw_alloc_validate(dir, &hw_alloc, hw_entries);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, HW Resource validation failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\treturn 0;\n+\n+ cleanup:\n+\treturn -1;\n+}\n+\n+/**\n+ * Internal function used to allocate and validate all SRAM resources.\n+ *\n+ * [in] tfp\n+ *   Pointer to TF handle\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * Returns:\n+ *   0  - Success\n+ *   -1 - Internal error\n+ */\n+static int\n+tf_rm_allocate_validate_sram(struct tf *tfp,\n+\t\t\t     enum tf_dir dir)\n+{\n+\tint rc;\n+\tint i;\n+\tstruct tf_rm_sram_query sram_query;\n+\tstruct tf_rm_sram_alloc sram_alloc;\n+\tstruct tf_session *tfs = (struct tf_session *)(tfp->session->core_data);\n+\tstruct tf_rm_entry *sram_entries;\n+\tuint32_t error_flag;\n+\n+\tif (dir == TF_DIR_RX)\n+\t\tsram_entries = tfs->resc.rx.sram_entry;\n+\telse\n+\t\tsram_entries = tfs->resc.tx.sram_entry;\n+\n+\t/* Query for Session SRAM Resources */\n+\trc = tf_msg_session_sram_resc_qcaps(tfp, dir, &sram_query);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, SRAM qcaps message send failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\trc = tf_rm_check_sram_qcaps_static(&sram_query, dir, &error_flag);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\"%s, SRAM QCAPS validation failed, error_flag:%x\\n\",\n+\t\t\ttf_dir_2_str(dir),\n+\t\t\terror_flag);\n+\t\ttf_rm_print_sram_qcaps_error(dir, &sram_query, &error_flag);\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Post process SRAM capability */\n+\tfor (i = 0; i < TF_RESC_TYPE_SRAM_MAX; i++)\n+\t\tsram_alloc.sram_num[i] = sram_query.sram_query[i].max;\n+\n+\t/* Allocate Session SRAM Resources */\n+\trc = tf_msg_session_sram_resc_alloc(tfp,\n+\t\t\t\t\t    dir,\n+\t\t\t\t\t    &sram_alloc,\n+\t\t\t\t\t    sram_entries);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, SRAM alloc message send failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\t/* Perform SRAM allocation validation as its possible the\n+\t * resource availability changed between qcaps and alloc\n+\t */\n+\trc = tf_rm_sram_alloc_validate(dir, &sram_alloc, sram_entries);\n+\tif (rc) {\n+\t\t/* Log error */\n+\t\tPMD_DRV_LOG(ERR,\n+\t\t\t    \"%s, SRAM Resource allocation validation failed\\n\",\n+\t\t\t    tf_dir_2_str(dir));\n+\t\tgoto cleanup;\n+\t}\n+\n+\treturn 0;\n+\n+ cleanup:\n+\treturn -1;\n+}\n+\n+/**\n+ * Helper function used to prune a SRAM resource array to only hold\n+ * elements that needs to be flushed.\n+ *\n+ * [in] tfs\n+ *   Session handle\n+ *\n+ * [in] dir\n+ *   Receive or transmit direction\n+ *\n+ * [in] hw_entries\n+ *   Master SRAM Resource data base\n+ *\n+ * [in/out] flush_entries\n+ *   Pruned SRAM Resource database of entries to be flushed. This\n+ *   array should be passed in as a complete copy of the master SRAM\n+ *   Resource database. The outgoing result will be a pruned version\n+ *   based on the result of the requested checking\n+ *\n+ * Returns:\n+ *    0 - Success, no flush required\n+ *    1 - Success, flush required\n+ *   -1 - Internal error\n+ */\n+static int\n+tf_rm_sram_to_flush(struct tf_session *tfs,\n+\t\t    enum tf_dir dir,\n+\t\t    struct tf_rm_entry *sram_entries,\n+\t\t    struct tf_rm_entry *flush_entries)\n+{\n+\tint rc;\n+\tint flush_rc = 0;\n+\tint free_cnt;\n+\tstruct bitalloc *pool;\n+\n+\t/* Check all the sram resource pools and check for left over\n+\t * elements. Any found will result in the complete pool of a\n+\t * type to get invalidated.\n+\t */\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_FULL_ACTION_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_FULL_ACTION].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_FULL_ACTION].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_FULL_ACTION].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\t/* Only pools for RX direction */\n+\tif (dir == TF_DIR_RX) {\n+\t\tTF_RM_GET_POOLS_RX(tfs, &pool,\n+\t\t\t\t   TF_SRAM_MCG_POOL_NAME);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\tfree_cnt = ba_free_count(pool);\n+\t\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_MCG].stride) {\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_MCG].start = 0;\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_MCG].stride = 0;\n+\t\t} else {\n+\t\t\tflush_rc = 1;\n+\t\t}\n+\t} else {\n+\t\t/* Always prune TX direction */\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_MCG].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_MCG].stride = 0;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_ENCAP_8B_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_ENCAP_8B].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_8B].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_8B].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_ENCAP_16B_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_ENCAP_16B].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_16B].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_16B].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\t/* Only pools for TX direction */\n+\tif (dir == TF_DIR_TX) {\n+\t\tTF_RM_GET_POOLS_TX(tfs, &pool,\n+\t\t\t\t   TF_SRAM_ENCAP_64B_POOL_NAME);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\tfree_cnt = ba_free_count(pool);\n+\t\tif (free_cnt ==\n+\t\t    sram_entries[TF_RESC_TYPE_SRAM_ENCAP_64B].stride) {\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_64B].start = 0;\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_64B].stride = 0;\n+\t\t} else {\n+\t\t\tflush_rc = 1;\n+\t\t}\n+\t} else {\n+\t\t/* Always prune RX direction */\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_64B].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_ENCAP_64B].stride = 0;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_SP_SMAC_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_SP_SMAC].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\t/* Only pools for TX direction */\n+\tif (dir == TF_DIR_TX) {\n+\t\tTF_RM_GET_POOLS_TX(tfs, &pool,\n+\t\t\t\t   TF_SRAM_SP_SMAC_IPV4_POOL_NAME);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\tfree_cnt = ba_free_count(pool);\n+\t\tif (free_cnt ==\n+\t\t    sram_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV4].stride) {\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV4].start = 0;\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV4].stride =\n+\t\t\t\t0;\n+\t\t} else {\n+\t\t\tflush_rc = 1;\n+\t\t}\n+\t} else {\n+\t\t/* Always prune RX direction */\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV4].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV4].stride = 0;\n+\t}\n+\n+\t/* Only pools for TX direction */\n+\tif (dir == TF_DIR_TX) {\n+\t\tTF_RM_GET_POOLS_TX(tfs, &pool,\n+\t\t\t\t   TF_SRAM_SP_SMAC_IPV6_POOL_NAME);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\tfree_cnt = ba_free_count(pool);\n+\t\tif (free_cnt ==\n+\t\t    sram_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV6].stride) {\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV6].start = 0;\n+\t\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV6].stride =\n+\t\t\t\t0;\n+\t\t} else {\n+\t\t\tflush_rc = 1;\n+\t\t}\n+\t} else {\n+\t\t/* Always prune RX direction */\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV6].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_SP_SMAC_IPV6].stride = 0;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_STATS_64B_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_COUNTER_64B].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_COUNTER_64B].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_COUNTER_64B].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_NAT_SPORT_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_NAT_SPORT].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_SPORT].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_SPORT].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_NAT_DPORT_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_NAT_DPORT].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_DPORT].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_DPORT].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_NAT_S_IPV4_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_NAT_S_IPV4].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_S_IPV4].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_S_IPV4].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\tTF_RM_GET_POOLS(tfs, dir, &pool,\n+\t\t\tTF_SRAM_NAT_D_IPV4_POOL_NAME,\n+\t\t\trc);\n+\tif (rc)\n+\t\treturn rc;\n+\tfree_cnt = ba_free_count(pool);\n+\tif (free_cnt == sram_entries[TF_RESC_TYPE_SRAM_NAT_D_IPV4].stride) {\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_D_IPV4].start = 0;\n+\t\tflush_entries[TF_RESC_TYPE_SRAM_NAT_D_IPV4].stride = 0;\n+\t} else {\n+\t\tflush_rc = 1;\n+\t}\n+\n+\treturn flush_rc;\n+}\n+\n+/**\n+ * Helper function used to generate an error log for the SRAM types\n+ * that needs to be flushed. The types should have been cleaned up\n+ * ahead of invoking tf_close_session.\n+ *\n+ * [in] sram_entries\n+ *   SRAM Resource database holding elements to be flushed\n+ */\n+static void\n+tf_rm_log_sram_flush(enum tf_dir dir,\n+\t\t     struct tf_rm_entry *sram_entries)\n+{\n+\tint i;\n+\n+\t/* Walk the sram flush array and log the types that wasn't\n+\t * cleaned up.\n+\t */\n+\tfor (i = 0; i < TF_RESC_TYPE_SRAM_MAX; i++) {\n+\t\tif (sram_entries[i].stride != 0)\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t    \"%s: %s was not cleaned up\\n\",\n+\t\t\t\t    tf_dir_2_str(dir),\n+\t\t\t\t    tf_hcapi_sram_2_str(i));\n+\t}\n+}\n+\n+void\n+tf_rm_init(struct tf *tfp __rte_unused)\n+{\n+\tstruct tf_session *tfs =\n+\t\t(struct tf_session *)(tfp->session->core_data);\n+\n+\t/* This version is host specific and should be checked against\n+\t * when attaching as there is no guarantee that a secondary\n+\t * would run from same image version.\n+\t */\n+\ttfs->ver.major = TF_SESSION_VER_MAJOR;\n+\ttfs->ver.minor = TF_SESSION_VER_MINOR;\n+\ttfs->ver.update = TF_SESSION_VER_UPDATE;\n+\n+\ttfs->session_id.id = 0;\n+\ttfs->ref_count = 0;\n+\n+\t/* Initialization of Table Scopes */\n+\t/* ll_init(&tfs->tbl_scope_ll); */\n+\n+\t/* Initialization of HW and SRAM resource DB */\n+\tmemset(&tfs->resc, 0, sizeof(struct tf_rm_db));\n+\n+\t/* Initialization of HW Resource Pools */\n+\tba_init(tfs->TF_L2_CTXT_TCAM_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);\n+\tba_init(tfs->TF_L2_CTXT_TCAM_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);\n+\n+\t/* Initialization of SRAM Resource Pools\n+\t * These pools are set to the TFLIB defined MAX sizes not\n+\t * AFM's HW max as to limit the memory consumption\n+\t */\n+\tba_init(tfs->TF_SRAM_FULL_ACTION_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_FULL_ACTION_RX);\n+\tba_init(tfs->TF_SRAM_FULL_ACTION_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_FULL_ACTION_TX);\n+\t/* Only Multicast Group on RX is supported */\n+\tba_init(tfs->TF_SRAM_MCG_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_MCG_RX);\n+\tba_init(tfs->TF_SRAM_ENCAP_8B_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_ENCAP_8B_RX);\n+\tba_init(tfs->TF_SRAM_ENCAP_8B_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_ENCAP_8B_TX);\n+\tba_init(tfs->TF_SRAM_ENCAP_16B_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_ENCAP_16B_RX);\n+\tba_init(tfs->TF_SRAM_ENCAP_16B_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_ENCAP_16B_TX);\n+\t/* Only Encap 64B on TX is supported */\n+\tba_init(tfs->TF_SRAM_ENCAP_64B_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_ENCAP_64B_TX);\n+\tba_init(tfs->TF_SRAM_SP_SMAC_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_SP_SMAC_RX);\n+\tba_init(tfs->TF_SRAM_SP_SMAC_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_SP_SMAC_TX);\n+\t/* Only SP SMAC IPv4 on TX is supported */\n+\tba_init(tfs->TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_SP_SMAC_IPV4_TX);\n+\t/* Only SP SMAC IPv6 on TX is supported */\n+\tba_init(tfs->TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_SP_SMAC_IPV6_TX);\n+\tba_init(tfs->TF_SRAM_STATS_64B_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_COUNTER_64B_RX);\n+\tba_init(tfs->TF_SRAM_STATS_64B_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_COUNTER_64B_TX);\n+\tba_init(tfs->TF_SRAM_NAT_SPORT_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_NAT_SPORT_RX);\n+\tba_init(tfs->TF_SRAM_NAT_SPORT_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_NAT_SPORT_TX);\n+\tba_init(tfs->TF_SRAM_NAT_DPORT_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_NAT_DPORT_RX);\n+\tba_init(tfs->TF_SRAM_NAT_DPORT_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_NAT_DPORT_TX);\n+\tba_init(tfs->TF_SRAM_NAT_S_IPV4_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_NAT_S_IPV4_RX);\n+\tba_init(tfs->TF_SRAM_NAT_S_IPV4_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_NAT_S_IPV4_TX);\n+\tba_init(tfs->TF_SRAM_NAT_D_IPV4_POOL_NAME_RX,\n+\t\tTF_RSVD_SRAM_NAT_D_IPV4_RX);\n+\tba_init(tfs->TF_SRAM_NAT_D_IPV4_POOL_NAME_TX,\n+\t\tTF_RSVD_SRAM_NAT_D_IPV4_TX);\n+\n+\t/* Initialization of pools local to TF Core */\n+\tba_init(tfs->TF_L2_CTXT_REMAP_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);\n+\tba_init(tfs->TF_L2_CTXT_REMAP_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);\n+}\n+\n+int\n+tf_rm_allocate_validate(struct tf *tfp)\n+{\n+\tint rc;\n+\tint i;\n+\n+\tfor (i = 0; i < TF_DIR_MAX; i++) {\n+\t\trc = tf_rm_allocate_validate_hw(tfp, i);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t\trc = tf_rm_allocate_validate_sram(tfp, i);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\t/* With both HW and SRAM allocated and validated we can\n+\t * 'scrub' the reservation on the pools.\n+\t */\n+\ttf_rm_reserve_hw(tfp);\n+\ttf_rm_reserve_sram(tfp);\n+\n+\treturn rc;\n+}\n+\n+int\n+tf_rm_close(struct tf *tfp)\n+{\n+\tint rc;\n+\tint rc_close = 0;\n+\tint i;\n+\tstruct tf_rm_entry *hw_entries;\n+\tstruct tf_rm_entry *sram_entries;\n+\tstruct tf_rm_entry *sram_flush_entries;\n+\tstruct tf_session *tfs __rte_unused =\n+\t\t(struct tf_session *)(tfp->session->core_data);\n+\n+\tstruct tf_rm_db flush_resc = tfs->resc;\n+\n+\t/* On close it is assumed that the session has already cleaned\n+\t * up all its resources, individually, while destroying its\n+\t * flows. No checking is performed thus the behavior is as\n+\t * follows.\n+\t *\n+\t * Session RM will signal FW to release session resources. FW\n+\t * will perform invalidation of all the allocated entries\n+\t * (assures any outstanding resources has been cleared, then\n+\t * free the FW RM instance.\n+\t *\n+\t * Session will then be freed by tf_close_session() thus there\n+\t * is no need to clean each resource pool as the whole session\n+\t * is going away.\n+\t */\n+\n+\tfor (i = 0; i < TF_DIR_MAX; i++) {\n+\t\tif (i == TF_DIR_RX) {\n+\t\t\thw_entries = tfs->resc.rx.hw_entry;\n+\t\t\tsram_entries = tfs->resc.rx.sram_entry;\n+\t\t\tsram_flush_entries = flush_resc.rx.sram_entry;\n+\t\t} else {\n+\t\t\thw_entries = tfs->resc.tx.hw_entry;\n+\t\t\tsram_entries = tfs->resc.tx.sram_entry;\n+\t\t\tsram_flush_entries = flush_resc.tx.sram_entry;\n+\t\t}\n+\n+\t\t/* Check for any not previously freed SRAM resources\n+\t\t * and flush if required.\n+\t\t */\n+\t\trc = tf_rm_sram_to_flush(tfs,\n+\t\t\t\t\t i,\n+\t\t\t\t\t sram_entries,\n+\t\t\t\t\t sram_flush_entries);\n+\t\tif (rc) {\n+\t\t\trc_close = -ENOTEMPTY;\n+\t\t\t/* Log error */\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t    \"%s, lingering SRAM resources\\n\",\n+\t\t\t\t    tf_dir_2_str(i));\n+\n+\t\t\t/* Log the entries to be flushed */\n+\t\t\ttf_rm_log_sram_flush(i, sram_flush_entries);\n+\n+\t\t\trc = tf_msg_session_sram_resc_flush(tfp,\n+\t\t\t\t\t\t\t    i,\n+\t\t\t\t\t\t\t    sram_flush_entries);\n+\t\t\tif (rc) {\n+\t\t\t\trc_close = rc;\n+\t\t\t\t/* Log error */\n+\t\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\t    \"%s, HW flush failed\\n\",\n+\t\t\t\t\t    tf_dir_2_str(i));\n+\t\t\t}\n+\t\t}\n+\n+\t\trc = tf_msg_session_hw_resc_free(tfp, i, hw_entries);\n+\t\tif (rc) {\n+\t\t\trc_close = rc;\n+\t\t\t/* Log error */\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t    \"%s, HW free failed\\n\",\n+\t\t\t\t    tf_dir_2_str(i));\n+\t\t}\n+\n+\t\trc = tf_msg_session_sram_resc_free(tfp, i, sram_entries);\n+\t\tif (rc) {\n+\t\t\trc_close = rc;\n+\t\t\t/* Log error */\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t    \"%s, SRAM free failed\\n\",\n+\t\t\t\t    tf_dir_2_str(i));\n+\t\t}\n+\t}\n+\n+\treturn rc_close;\n+}\n+\n+int\n+tf_rm_convert_tbl_type(enum tf_tbl_type type,\n+\t\t       uint32_t *hcapi_type)\n+{\n+\tint rc = 0;\n+\n+\tswitch (type) {\n+\tcase TF_TBL_TYPE_FULL_ACT_RECORD:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_FULL_ACTION;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_MCAST_GROUPS:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_MCG;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_ENCAP_8B:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_ENCAP_8B;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_ENCAP_16B:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_ENCAP_16B;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_ENCAP_64B:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_ENCAP_64B;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_SP_SMAC;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV4:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_SP_SMAC_IPV4;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV6:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_SP_SMAC_IPV6;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_STATS_64:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_COUNTER_64B;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_MODIFY_SPORT:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_NAT_SPORT;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_MODIFY_DPORT:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_NAT_DPORT;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV4_SRC:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_NAT_S_IPV4;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV4_DEST:\n+\t\t*hcapi_type = TF_RESC_TYPE_SRAM_NAT_D_IPV4;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_METER_PROF:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_METER_PROF;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_METER_INST:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_METER_INST;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_MIRROR_CONFIG:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_MIRROR;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_UPAR:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_UPAR;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_EPOCH0:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_EPOCH0;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_EPOCH1:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_EPOCH1;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_METADATA:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_METADATA;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_CT_STATE:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_CT_STATE;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_RANGE_PROF:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_RANGE_PROF;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_RANGE_ENTRY:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_RANGE_ENTRY;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_LAG:\n+\t\t*hcapi_type = TF_RESC_TYPE_HW_LAG_ENTRY;\n+\t\tbreak;\n+\t/* Not yet supported */\n+\tcase TF_TBL_TYPE_ACT_ENCAP_32B:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV6_DEST:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV6_SRC:\n+\tcase TF_TBL_TYPE_VNIC_SVIF:\n+\tcase TF_TBL_TYPE_EXT:   /* No pools for this type */\n+\tcase TF_TBL_TYPE_EXT_0: /* No pools for this type */\n+\tdefault:\n+\t\t*hcapi_type = -1;\n+\t\trc = -EOPNOTSUPP;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+tf_rm_convert_index(struct tf_session *tfs,\n+\t\t    enum tf_dir dir,\n+\t\t    enum tf_tbl_type type,\n+\t\t    enum tf_rm_convert_type c_type,\n+\t\t    uint32_t index,\n+\t\t    uint32_t *convert_index)\n+{\n+\tint rc;\n+\tstruct tf_rm_resc *resc;\n+\tuint32_t hcapi_type;\n+\tuint32_t base_index;\n+\n+\tif (dir == TF_DIR_RX)\n+\t\tresc = &tfs->resc.rx;\n+\telse if (dir == TF_DIR_TX)\n+\t\tresc = &tfs->resc.tx;\n+\telse\n+\t\treturn -EOPNOTSUPP;\n+\n+\trc = tf_rm_convert_tbl_type(type, &hcapi_type);\n+\tif (rc)\n+\t\treturn -1;\n+\n+\tswitch (type) {\n+\tcase TF_TBL_TYPE_FULL_ACT_RECORD:\n+\tcase TF_TBL_TYPE_MCAST_GROUPS:\n+\tcase TF_TBL_TYPE_ACT_ENCAP_8B:\n+\tcase TF_TBL_TYPE_ACT_ENCAP_16B:\n+\tcase TF_TBL_TYPE_ACT_ENCAP_32B:\n+\tcase TF_TBL_TYPE_ACT_ENCAP_64B:\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC:\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV4:\n+\tcase TF_TBL_TYPE_ACT_SP_SMAC_IPV6:\n+\tcase TF_TBL_TYPE_ACT_STATS_64:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_SPORT:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_DPORT:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV4_SRC:\n+\tcase TF_TBL_TYPE_ACT_MODIFY_IPV4_DEST:\n+\t\tbase_index = resc->sram_entry[hcapi_type].start;\n+\t\tbreak;\n+\tcase TF_TBL_TYPE_MIRROR_CONFIG:\n+\tcase TF_TBL_TYPE_METER_PROF:\n+\tcase TF_TBL_TYPE_METER_INST:\n+\tcase TF_TBL_TYPE_UPAR:\n+\tcase TF_TBL_TYPE_EPOCH0:\n+\tcase TF_TBL_TYPE_EPOCH1:\n+\tcase TF_TBL_TYPE_METADATA:\n+\tcase TF_TBL_TYPE_CT_STATE:\n+\tcase TF_TBL_TYPE_RANGE_PROF:\n+\tcase TF_TBL_TYPE_RANGE_ENTRY:\n+\tcase TF_TBL_TYPE_LAG:\n+\t\tbase_index = resc->hw_entry[hcapi_type].start;\n+\t\tbreak;\n+\t/* Not yet supported */\n+\tcase TF_TBL_TYPE_VNIC_SVIF:\n+\tcase TF_TBL_TYPE_EXT:   /* No pools for this type */\n+\tcase TF_TBL_TYPE_EXT_0: /* No pools for this type */\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\tswitch (c_type) {\n+\tcase TF_RM_CONVERT_RM_BASE:\n+\t\t*convert_index = index - base_index;\n+\t\tbreak;\n+\tcase TF_RM_CONVERT_ADD_BASE:\n+\t\t*convert_index = index + base_index;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/net/bnxt/tf_core/tf_rm.h b/drivers/net/bnxt/tf_core/tf_rm.h\nindex 57ce19b..e69d443 100644\n--- a/drivers/net/bnxt/tf_core/tf_rm.h\n+++ b/drivers/net/bnxt/tf_core/tf_rm.h\n@@ -107,6 +107,54 @@ struct tf_rm_sram_alloc {\n };\n \n /**\n+ * Resource Manager arrays for a single direction\n+ */\n+struct tf_rm_resc {\n+\t/** array of HW resource entries */\n+\tstruct tf_rm_entry hw_entry[TF_RESC_TYPE_HW_MAX];\n+\t/** array of SRAM resource entries */\n+\tstruct tf_rm_entry sram_entry[TF_RESC_TYPE_SRAM_MAX];\n+};\n+\n+/**\n+ * Resource Manager Database\n+ */\n+struct tf_rm_db {\n+\tstruct tf_rm_resc rx;\n+\tstruct tf_rm_resc tx;\n+};\n+\n+/**\n+ * Helper function converting direction to text string\n+ */\n+const char\n+*tf_dir_2_str(enum tf_dir dir);\n+\n+/**\n+ * Helper function converting identifier to text string\n+ */\n+const char\n+*tf_ident_2_str(enum tf_identifier_type id_type);\n+\n+/**\n+ * Helper function converting tcam type to text string\n+ */\n+const char\n+*tf_tcam_tbl_2_str(enum tf_tcam_tbl_type tcam_type);\n+\n+/**\n+ * Helper function used to convert HW HCAPI resource type to a string.\n+ */\n+const char\n+*tf_hcapi_hw_2_str(enum tf_resource_type_hw hw_type);\n+\n+/**\n+ * Helper function used to convert SRAM HCAPI resource type to a string.\n+ */\n+const char\n+*tf_hcapi_sram_2_str(enum tf_resource_type_sram sram_type);\n+\n+/**\n  * Initializes the Resource Manager and the associated database\n  * entries for HW and SRAM resources. Must be called before any other\n  * Resource Manager functions.\n@@ -143,4 +191,131 @@ int tf_rm_allocate_validate(struct tf *tfp);\n  *   - (-ENOTEMPTY) if resources are not cleaned up before close\n  */\n int tf_rm_close(struct tf *tfp);\n+\n+#if (TF_SHADOW == 1)\n+/**\n+ * Initializes Shadow DB of configuration elements\n+ *\n+ * [in] tfs\n+ *   Pointer to TF Session\n+ *\n+ * Returns:\n+ *  0  - Success\n+ */\n+int tf_rm_shadow_db_init(struct tf_session *tfs);\n+#endif /* TF_SHADOW */\n+\n+/**\n+ * Perform a Session Pool lookup using the Tcam table type.\n+ *\n+ * Function will print error msg if tcam type is unsupported or lookup\n+ * failed.\n+ *\n+ * [in] tfs\n+ *   Pointer to TF Session\n+ *\n+ * [in] type\n+ *   Type of the object\n+ *\n+ * [in] dir\n+ *    Receive or transmit direction\n+ *\n+ * [in/out]  session_pool\n+ *   Session pool\n+ *\n+ * Returns:\n+ *  0           - Success will set the **pool\n+ *  -EOPNOTSUPP - Type is not supported\n+ */\n+int\n+tf_rm_lookup_tcam_type_pool(struct tf_session *tfs,\n+\t\t\t    enum tf_dir dir,\n+\t\t\t    enum tf_tcam_tbl_type type,\n+\t\t\t    struct bitalloc **pool);\n+\n+/**\n+ * Perform a Session Pool lookup using the Table type.\n+ *\n+ * Function will print error msg if table type is unsupported or\n+ * lookup failed.\n+ *\n+ * [in] tfs\n+ *   Pointer to TF Session\n+ *\n+ * [in] type\n+ *   Type of the object\n+ *\n+ * [in] dir\n+ *    Receive or transmit direction\n+ *\n+ * [in/out]  session_pool\n+ *   Session pool\n+ *\n+ * Returns:\n+ *  0           - Success will set the **pool\n+ *  -EOPNOTSUPP - Type is not supported\n+ */\n+int\n+tf_rm_lookup_tbl_type_pool(struct tf_session *tfs,\n+\t\t\t   enum tf_dir dir,\n+\t\t\t   enum tf_tbl_type type,\n+\t\t\t   struct bitalloc **pool);\n+\n+/**\n+ * Converts the TF Table Type to internal HCAPI_TYPE\n+ *\n+ * [in] type\n+ *   Type to be converted\n+ *\n+ * [in/out] hcapi_type\n+ *   Converted type\n+ *\n+ * Returns:\n+ *  0           - Success will set the *hcapi_type\n+ *  -EOPNOTSUPP - Type is not supported\n+ */\n+int\n+tf_rm_convert_tbl_type(enum tf_tbl_type type,\n+\t\t       uint32_t *hcapi_type);\n+\n+/**\n+ * TF RM Convert of index methods.\n+ */\n+enum tf_rm_convert_type {\n+\t/** Adds the base of the Session Pool to the index */\n+\tTF_RM_CONVERT_ADD_BASE,\n+\t/** Removes the Session Pool base from the index */\n+\tTF_RM_CONVERT_RM_BASE\n+};\n+\n+/**\n+ * Provides conversion of the Table Type index in relation to the\n+ * Session Pool base.\n+ *\n+ * [in] tfs\n+ *   Pointer to TF Session\n+ *\n+ * [in] dir\n+ *    Receive or transmit direction\n+ *\n+ * [in] type\n+ *   Type of the object\n+ *\n+ * [in] c_type\n+ *   Type of conversion to perform\n+ *\n+ * [in] index\n+ *   Index to be converted\n+ *\n+ * [in/out]  convert_index\n+ *   Pointer to the converted index\n+ */\n+int\n+tf_rm_convert_index(struct tf_session *tfs,\n+\t\t    enum tf_dir dir,\n+\t\t    enum tf_tbl_type type,\n+\t\t    enum tf_rm_convert_type c_type,\n+\t\t    uint32_t index,\n+\t\t    uint32_t *convert_index);\n+\n #endif /* TF_RM_H_ */\ndiff --git a/drivers/net/bnxt/tf_core/tf_session.h b/drivers/net/bnxt/tf_core/tf_session.h\nindex 651d3ee..34b6c41 100644\n--- a/drivers/net/bnxt/tf_core/tf_session.h\n+++ b/drivers/net/bnxt/tf_core/tf_session.h\n@@ -76,11 +76,215 @@ struct tf_session {\n \t */\n \tuint8_t ref_count;\n \n+\t/** Session HW and SRAM resources */\n+\tstruct tf_rm_db resc;\n+\n+\t/* Session HW resource pools */\n+\n+\t/** RX L2 CTXT TCAM Pool */\n+\tBITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);\n+\t/** TX L2 CTXT TCAM Pool */\n+\tBITALLOC_INST(TF_L2_CTXT_TCAM_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);\n+\n+\t/** RX Profile Func Pool */\n+\tBITALLOC_INST(TF_PROF_FUNC_POOL_NAME_RX, TF_NUM_PROF_FUNC);\n+\t/** TX Profile Func Pool */\n+\tBITALLOC_INST(TF_PROF_FUNC_POOL_NAME_TX, TF_NUM_PROF_FUNC);\n+\n+\t/** RX Profile TCAM Pool */\n+\tBITALLOC_INST(TF_PROF_TCAM_POOL_NAME_RX, TF_NUM_PROF_TCAM);\n+\t/** TX Profile TCAM Pool */\n+\tBITALLOC_INST(TF_PROF_TCAM_POOL_NAME_TX, TF_NUM_PROF_TCAM);\n+\n+\t/** RX EM Profile ID Pool */\n+\tBITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_RX, TF_NUM_EM_PROF_ID);\n+\t/** TX EM Key Pool */\n+\tBITALLOC_INST(TF_EM_PROF_ID_POOL_NAME_TX, TF_NUM_EM_PROF_ID);\n+\n+\t/** RX WC Profile Pool */\n+\tBITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_RX, TF_NUM_WC_PROF_ID);\n+\t/** TX WC Profile Pool */\n+\tBITALLOC_INST(TF_WC_TCAM_PROF_ID_POOL_NAME_TX, TF_NUM_WC_PROF_ID);\n+\n+\t/* TBD, how do we want to handle EM records ?*/\n+\t/* EM Records are not controlled by way of a pool */\n+\n+\t/** RX WC TCAM Pool */\n+\tBITALLOC_INST(TF_WC_TCAM_POOL_NAME_RX, TF_NUM_WC_TCAM_ROW);\n+\t/** TX WC TCAM Pool */\n+\tBITALLOC_INST(TF_WC_TCAM_POOL_NAME_TX, TF_NUM_WC_TCAM_ROW);\n+\n+\t/** RX Meter Profile Pool */\n+\tBITALLOC_INST(TF_METER_PROF_POOL_NAME_RX, TF_NUM_METER_PROF);\n+\t/** TX Meter Profile Pool */\n+\tBITALLOC_INST(TF_METER_PROF_POOL_NAME_TX, TF_NUM_METER_PROF);\n+\n+\t/** RX Meter Instance Pool */\n+\tBITALLOC_INST(TF_METER_INST_POOL_NAME_RX, TF_NUM_METER);\n+\t/** TX Meter Pool */\n+\tBITALLOC_INST(TF_METER_INST_POOL_NAME_TX, TF_NUM_METER);\n+\n+\t/** RX Mirror Configuration Pool*/\n+\tBITALLOC_INST(TF_MIRROR_POOL_NAME_RX, TF_NUM_MIRROR);\n+\t/** RX Mirror Configuration Pool */\n+\tBITALLOC_INST(TF_MIRROR_POOL_NAME_TX, TF_NUM_MIRROR);\n+\n+\t/** RX UPAR Pool */\n+\tBITALLOC_INST(TF_UPAR_POOL_NAME_RX, TF_NUM_UPAR);\n+\t/** TX UPAR Pool */\n+\tBITALLOC_INST(TF_UPAR_POOL_NAME_TX, TF_NUM_UPAR);\n+\n+\t/** RX SP TCAM Pool */\n+\tBITALLOC_INST(TF_SP_TCAM_POOL_NAME_RX, TF_NUM_SP_TCAM);\n+\t/** TX SP TCAM Pool */\n+\tBITALLOC_INST(TF_SP_TCAM_POOL_NAME_TX, TF_NUM_SP_TCAM);\n+\n+\t/** RX FKB Pool */\n+\tBITALLOC_INST(TF_FKB_POOL_NAME_RX, TF_NUM_FKB);\n+\t/** TX FKB Pool */\n+\tBITALLOC_INST(TF_FKB_POOL_NAME_TX, TF_NUM_FKB);\n+\n+\t/** RX Table Scope Pool */\n+\tBITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_RX, TF_NUM_TBL_SCOPE);\n+\t/** TX Table Scope Pool */\n+\tBITALLOC_INST(TF_TBL_SCOPE_POOL_NAME_TX, TF_NUM_TBL_SCOPE);\n+\n+\t/** RX L2 Func Pool */\n+\tBITALLOC_INST(TF_L2_FUNC_POOL_NAME_RX, TF_NUM_L2_FUNC);\n+\t/** TX L2 Func Pool */\n+\tBITALLOC_INST(TF_L2_FUNC_POOL_NAME_TX, TF_NUM_L2_FUNC);\n+\n+\t/** RX Epoch0 Pool */\n+\tBITALLOC_INST(TF_EPOCH0_POOL_NAME_RX, TF_NUM_EPOCH0);\n+\t/** TX Epoch0 Pool */\n+\tBITALLOC_INST(TF_EPOCH0_POOL_NAME_TX, TF_NUM_EPOCH0);\n+\n+\t/** TX Epoch1 Pool */\n+\tBITALLOC_INST(TF_EPOCH1_POOL_NAME_RX, TF_NUM_EPOCH1);\n+\t/** TX Epoch1 Pool */\n+\tBITALLOC_INST(TF_EPOCH1_POOL_NAME_TX, TF_NUM_EPOCH1);\n+\n+\t/** RX MetaData Profile Pool */\n+\tBITALLOC_INST(TF_METADATA_POOL_NAME_RX, TF_NUM_METADATA);\n+\t/** TX MetaData Profile Pool */\n+\tBITALLOC_INST(TF_METADATA_POOL_NAME_TX, TF_NUM_METADATA);\n+\n+\t/** RX Connection Tracking State Pool */\n+\tBITALLOC_INST(TF_CT_STATE_POOL_NAME_RX, TF_NUM_CT_STATE);\n+\t/** TX Connection Tracking State Pool */\n+\tBITALLOC_INST(TF_CT_STATE_POOL_NAME_TX, TF_NUM_CT_STATE);\n+\n+\t/** RX Range Profile Pool */\n+\tBITALLOC_INST(TF_RANGE_PROF_POOL_NAME_RX, TF_NUM_RANGE_PROF);\n+\t/** TX Range Profile Pool */\n+\tBITALLOC_INST(TF_RANGE_PROF_POOL_NAME_TX, TF_NUM_RANGE_PROF);\n+\n+\t/** RX Range Pool */\n+\tBITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_RX, TF_NUM_RANGE_ENTRY);\n+\t/** TX Range Pool */\n+\tBITALLOC_INST(TF_RANGE_ENTRY_POOL_NAME_TX, TF_NUM_RANGE_ENTRY);\n+\n+\t/** RX LAG Pool */\n+\tBITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_RX, TF_NUM_LAG_ENTRY);\n+\t/** TX LAG Pool */\n+\tBITALLOC_INST(TF_LAG_ENTRY_POOL_NAME_TX, TF_NUM_LAG_ENTRY);\n+\n+\t/* Session SRAM pools */\n+\n+\t/** RX Full Action Record Pool */\n+\tBITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_FULL_ACTION_RX);\n+\t/** TX Full Action Record Pool */\n+\tBITALLOC_INST(TF_SRAM_FULL_ACTION_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_FULL_ACTION_TX);\n+\n+\t/** RX Multicast Group Pool, only RX is supported */\n+\tBITALLOC_INST(TF_SRAM_MCG_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_MCG_RX);\n+\n+\t/** RX Encap 8B Pool*/\n+\tBITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_ENCAP_8B_RX);\n+\t/** TX Encap 8B Pool*/\n+\tBITALLOC_INST(TF_SRAM_ENCAP_8B_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_ENCAP_8B_TX);\n+\n+\t/** RX Encap 16B Pool */\n+\tBITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_ENCAP_16B_RX);\n+\t/** TX Encap 16B Pool */\n+\tBITALLOC_INST(TF_SRAM_ENCAP_16B_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_ENCAP_16B_TX);\n+\n+\t/** TX Encap 64B Pool, only TX is supported */\n+\tBITALLOC_INST(TF_SRAM_ENCAP_64B_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_ENCAP_64B_TX);\n+\n+\t/** RX Source Properties SMAC Pool */\n+\tBITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_SP_SMAC_RX);\n+\t/** TX Source Properties SMAC Pool */\n+\tBITALLOC_INST(TF_SRAM_SP_SMAC_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_SP_SMAC_TX);\n+\n+\t/** TX Source Properties SMAC IPv4 Pool, only TX is supported */\n+\tBITALLOC_INST(TF_SRAM_SP_SMAC_IPV4_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_SP_SMAC_IPV4_TX);\n+\n+\t/** TX Source Properties SMAC IPv6 Pool, only TX is supported */\n+\tBITALLOC_INST(TF_SRAM_SP_SMAC_IPV6_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_SP_SMAC_IPV6_TX);\n+\n+\t/** RX Counter 64B Pool */\n+\tBITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_COUNTER_64B_RX);\n+\t/** TX Counter 64B Pool */\n+\tBITALLOC_INST(TF_SRAM_STATS_64B_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_COUNTER_64B_TX);\n+\n+\t/** RX NAT Source Port Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_NAT_SPORT_RX);\n+\t/** TX NAT Source Port Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_SPORT_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_NAT_SPORT_TX);\n+\n+\t/** RX NAT Destination Port Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_NAT_DPORT_RX);\n+\t/** TX NAT Destination Port Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_DPORT_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_NAT_DPORT_TX);\n+\n+\t/** RX NAT Source IPv4 Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_NAT_S_IPV4_RX);\n+\t/** TX NAT Source IPv4 Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_S_IPV4_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_NAT_S_IPV4_TX);\n+\n+\t/** RX NAT Destination IPv4 Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_RX,\n+\t\t      TF_RSVD_SRAM_NAT_D_IPV4_RX);\n+\t/** TX NAT IPv4 Destination Pool */\n+\tBITALLOC_INST(TF_SRAM_NAT_D_IPV4_POOL_NAME_TX,\n+\t\t      TF_RSVD_SRAM_NAT_D_IPV4_TX);\n+\n+\t/**\n+\t * Pools not allocated from HCAPI RM\n+\t */\n+\n+\t/** RX L2 Ctx Remap ID  Pool */\n+\tBITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_RX, TF_NUM_L2_CTXT_TCAM);\n+\t/** TX L2 Ctx Remap ID Pool */\n+\tBITALLOC_INST(TF_L2_CTXT_REMAP_POOL_NAME_TX, TF_NUM_L2_CTXT_TCAM);\n+\n \t/** CRC32 seed table */\n #define TF_LKUP_SEED_MEM_SIZE 512\n \tuint32_t lkup_em_seed_mem[TF_DIR_MAX][TF_LKUP_SEED_MEM_SIZE];\n+\n \t/** Lookup3 init values */\n \tuint32_t lkup_lkup3_init_cfg[TF_DIR_MAX];\n-\n };\n+\n #endif /* _TF_SESSION_H_ */\n",
    "prefixes": [
        "v4",
        "07/34"
    ]
}