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{
    "id": 68488,
    "url": "https://patches.dpdk.org/api/patches/68488/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1586938751-32808-2-git-send-email-venkatkumar.duvvuru@broadcom.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1586938751-32808-2-git-send-email-venkatkumar.duvvuru@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1586938751-32808-2-git-send-email-venkatkumar.duvvuru@broadcom.com",
    "date": "2020-04-15T08:18:38",
    "name": "[v4,01/34] net/bnxt: add updated dpdk hsi structure",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "0445cf1b54d618ead15df44591f10dba54419be3",
    "submitter": {
        "id": 1635,
        "url": "https://patches.dpdk.org/api/people/1635/?format=api",
        "name": "Venkat Duvvuru",
        "email": "venkatkumar.duvvuru@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "https://patches.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1586938751-32808-2-git-send-email-venkatkumar.duvvuru@broadcom.com/mbox/",
    "series": [
        {
            "id": 9386,
            "url": "https://patches.dpdk.org/api/series/9386/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9386",
            "date": "2020-04-15T08:18:37",
            "name": "add support for host based flow table management",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/9386/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/68488/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/68488/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>,\n Randy Schacher <stuart.schacher@broadcom.com>",
        "Date": "Wed, 15 Apr 2020 13:48:38 +0530",
        "Message-Id": "\n <1586938751-32808-2-git-send-email-venkatkumar.duvvuru@broadcom.com>",
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        "References": "\n <1586852011-37536-1-git-send-email-venkatkumar.duvvuru@broadcom.com>\n <1586938751-32808-1-git-send-email-venkatkumar.duvvuru@broadcom.com>",
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        "Subject": "[dpdk-dev] [PATCH v4 01/34] net/bnxt: add updated dpdk hsi structure",
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    "content": "From: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n\n- Add most recent bnxt dpdk header.\n- HWRM version updated to 1.10.1.30\n\nSigned-off-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\nSigned-off-by: Randy Schacher <stuart.schacher@broadcom.com>\nReviewed-by: Lance Richardson <lance.richardson@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 3786 +++++++++++++++++++++++++++++---\n 1 file changed, 3436 insertions(+), 350 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex c2bae0f..cde96e7 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (c) 2014-2019 Broadcom Inc.\n+ * Copyright (c) 2014-2020 Broadcom Inc.\n  * All rights reserved.\n  *\n  * DO NOT MODIFY!!! This file is automatically generated.\n@@ -386,6 +386,8 @@ struct cmd_nums {\n \t#define HWRM_PORT_PHY_MDIO_READ                   UINT32_C(0xb6)\n \t#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            UINT32_C(0xb7)\n \t#define HWRM_PORT_PHY_MDIO_BUS_RELEASE            UINT32_C(0xb8)\n+\t#define HWRM_PORT_QSTATS_EXT_PFC_WD               UINT32_C(0xb9)\n+\t#define HWRM_PORT_ECN_QSTATS                      UINT32_C(0xba)\n \t#define HWRM_FW_RESET                             UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS                           UINT32_C(0xc1)\n \t#define HWRM_FW_HEALTH_CHECK                      UINT32_C(0xc2)\n@@ -404,6 +406,8 @@ struct cmd_nums {\n \t#define HWRM_FW_GET_STRUCTURED_DATA               UINT32_C(0xcb)\n \t/* Experimental */\n \t#define HWRM_FW_IPC_MAILBOX                       UINT32_C(0xcc)\n+\t#define HWRM_FW_ECN_CFG                           UINT32_C(0xcd)\n+\t#define HWRM_FW_ECN_QCFG                          UINT32_C(0xce)\n \t#define HWRM_EXEC_FWD_RESP                        UINT32_C(0xd0)\n \t#define HWRM_REJECT_FWD_RESP                      UINT32_C(0xd1)\n \t#define HWRM_FWD_RESP                             UINT32_C(0xd2)\n@@ -419,6 +423,7 @@ struct cmd_nums {\n \t#define HWRM_TEMP_MONITOR_QUERY                   UINT32_C(0xe0)\n \t#define HWRM_REG_POWER_QUERY                      UINT32_C(0xe1)\n \t#define HWRM_CORE_FREQUENCY_QUERY                 UINT32_C(0xe2)\n+\t#define HWRM_REG_POWER_HISTOGRAM                  UINT32_C(0xe3)\n \t#define HWRM_WOL_FILTER_ALLOC                     UINT32_C(0xf0)\n \t#define HWRM_WOL_FILTER_FREE                      UINT32_C(0xf1)\n \t#define HWRM_WOL_FILTER_QCFG                      UINT32_C(0xf2)\n@@ -510,7 +515,7 @@ struct cmd_nums {\n \t#define HWRM_CFA_EEM_OP                           UINT32_C(0x123)\n \t/* Experimental */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              UINT32_C(0x124)\n-\t/* Experimental */\n+\t/* Experimental - DEPRECATED */\n \t#define HWRM_CFA_TFLIB                            UINT32_C(0x125)\n \t/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */\n \t#define HWRM_ENGINE_CKV_STATUS                    UINT32_C(0x12e)\n@@ -629,6 +634,56 @@ struct cmd_nums {\n \t * to the host test.\n \t */\n \t#define HWRM_MFG_HDMA_TEST                        UINT32_C(0x209)\n+\t/* Tells the fw to program the fru memory */\n+\t#define HWRM_MFG_FRU_EEPROM_WRITE                 UINT32_C(0x20a)\n+\t/* Tells the fw to read the fru memory */\n+\t#define HWRM_MFG_FRU_EEPROM_READ                  UINT32_C(0x20b)\n+\t/* Experimental */\n+\t#define HWRM_TF                                   UINT32_C(0x2bc)\n+\t/* Experimental */\n+\t#define HWRM_TF_VERSION_GET                       UINT32_C(0x2bd)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_OPEN                      UINT32_C(0x2c6)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_ATTACH                    UINT32_C(0x2c7)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_CLOSE                     UINT32_C(0x2c8)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_QCFG                      UINT32_C(0x2c9)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS                UINT32_C(0x2ca)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_RESC_ALLOC                UINT32_C(0x2cb)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_RESC_FREE                 UINT32_C(0x2cc)\n+\t/* Experimental */\n+\t#define HWRM_TF_SESSION_RESC_FLUSH                UINT32_C(0x2cd)\n+\t/* Experimental */\n+\t#define HWRM_TF_TBL_TYPE_GET                      UINT32_C(0x2d0)\n+\t/* Experimental */\n+\t#define HWRM_TF_TBL_TYPE_SET                      UINT32_C(0x2d1)\n+\t/* Experimental */\n+\t#define HWRM_TF_CTXT_MEM_RGTR                     UINT32_C(0x2da)\n+\t/* Experimental */\n+\t#define HWRM_TF_CTXT_MEM_UNRGTR                   UINT32_C(0x2db)\n+\t/* Experimental */\n+\t#define HWRM_TF_EXT_EM_QCAPS                      UINT32_C(0x2dc)\n+\t/* Experimental */\n+\t#define HWRM_TF_EXT_EM_OP                         UINT32_C(0x2dd)\n+\t/* Experimental */\n+\t#define HWRM_TF_EXT_EM_CFG                        UINT32_C(0x2de)\n+\t/* Experimental */\n+\t#define HWRM_TF_EXT_EM_QCFG                       UINT32_C(0x2df)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_SET                          UINT32_C(0x2ee)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_GET                          UINT32_C(0x2ef)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_MOVE                         UINT32_C(0x2f0)\n+\t/* Experimental */\n+\t#define HWRM_TF_TCAM_FREE                         UINT32_C(0x2f1)\n+\t/* Experimental */\n+\t#define HWRM_SV                                   UINT32_C(0x400)\n \t/* Experimental */\n \t#define HWRM_DBG_READ_DIRECT                      UINT32_C(0xff10)\n \t/* Experimental */\n@@ -658,6 +713,8 @@ struct cmd_nums {\n \t#define HWRM_DBG_CRASHDUMP_HEADER                 UINT32_C(0xff1d)\n \t/* Experimental */\n \t#define HWRM_DBG_CRASHDUMP_ERASE                  UINT32_C(0xff1e)\n+\t/* Send driver debug information to firmware */\n+\t#define HWRM_DBG_DRV_TRACE                        UINT32_C(0xff1f)\n \t/* Experimental */\n \t#define HWRM_NVM_FACTORY_DEFAULTS                 UINT32_C(0xffee)\n \t#define HWRM_NVM_VALIDATE_OPTION                  UINT32_C(0xffef)\n@@ -857,8 +914,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 10\n #define HWRM_VERSION_UPDATE 1\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 6\n-#define HWRM_VERSION_STR \"1.10.1.6\"\n+#define HWRM_VERSION_RSVD 30\n+#define HWRM_VERSION_STR \"1.10.1.30\"\n \n /****************\n  * hwrm_ver_get *\n@@ -1143,6 +1200,7 @@ struct hwrm_ver_get_output {\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \\\n \t\tUINT32_C(0x1000)\n \t/*\n+\t * Deprecated and replaced with cfa_truflow_supported.\n \t * If set to 1, the firmware is able to support TFLIB features.\n \t * If set to 0, then the firmware doesn’t support TFLIB features.\n \t * By default, this flag should be 0 for older version of core firmware.\n@@ -1150,6 +1208,14 @@ struct hwrm_ver_get_output {\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \\\n \t\tUINT32_C(0x2000)\n \t/*\n+\t * If set to 1, the firmware is able to support TruFlow features.\n+\t * If set to 0, then the firmware doesn’t support TruFlow features.\n+\t * By default, this flag should be 0 for older version of\n+\t * core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n \t * This field represents the major version of RoCE firmware.\n \t * A change in major version represents a major release.\n \t */\n@@ -4508,10 +4574,16 @@ struct hwrm_async_event_cmpl {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \\\n \t\tUINT32_C(0x3c)\n-\t/* TFLIB unique default VNIC Configuration Change */\n+\t/*\n+\t * Deprecated.\n+\t * TFLIB unique default VNIC Configuration Change\n+\t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \\\n \t\tUINT32_C(0x3d)\n-\t/* TFLIB unique link status changed */\n+\t/*\n+\t * Deprecated.\n+\t * TFLIB unique link status changed\n+\t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \\\n \t\tUINT32_C(0x3e)\n \t/*\n@@ -4521,6 +4593,19 @@ struct hwrm_async_event_cmpl {\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE \\\n \t\tUINT32_C(0x3f)\n \t/*\n+\t * An event signifying a HWRM command is in progress and its\n+\t * response will be deferred. This event is used on crypto controllers\n+\t * only.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * An event signifying that a PFC WatchDog configuration\n+\t * has changed on any port / cos.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \\\n+\t\tUINT32_C(0x41)\n+\t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n \t * event, not meant for production use at this time.\n@@ -6393,6 +6478,36 @@ struct hwrm_async_event_cmpl_quiesce_done {\n \t\tUINT32_C(0x2)\n \t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_LAST \\\n \t\tHWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR\n+\t/* opaque is 8 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_SFT \\\n+\t\t8\n+\t/*\n+\t * Additional information about internal hardware state related to\n+\t * idle/quiesce state.  QUIESCE may succeed per quiesce_status\n+\t * regardless of idle_state_flags.  If QUIESCE fails, the host may\n+\t * inspect idle_state_flags to determine whether a retry is warranted.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK \\\n+\t\tUINT32_C(0xff0000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_SFT \\\n+\t\t16\n+\t/*\n+\t * Failure to quiesce is caused by host not updating the NQ consumer\n+\t * index.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ \\\n+\t\tUINT32_C(0x10000)\n+\t/* Flag 1 indicating partial non-idle state. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 \\\n+\t\tUINT32_C(0x20000)\n+\t/* Flag 2 indicating partial non-idle state. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 \\\n+\t\tUINT32_C(0x40000)\n+\t/* Flag 3 indicating partial non-idle state. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 \\\n+\t\tUINT32_C(0x80000)\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n@@ -6414,6 +6529,152 @@ struct hwrm_async_event_cmpl_quiesce_done {\n \t\tUINT32_C(0x1)\n } __attribute__((packed));\n \n+/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */\n+struct hwrm_async_event_cmpl_deferred_response {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT             0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * An event signifying a HWRM command is in progress and its\n+\t * response will be deferred\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE \\\n+\t\tUINT32_C(0x40)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\t/*\n+\t * The PF's mailbox is clear to issue another command.\n+\t * A command with this seq_id is still in progress\n+\t * and will return a regualr HWRM completion when done.\n+\t * 'event_data1' field, if non-zero, contains the estimated\n+\t * execution time for the command.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT \\\n+\t\t0\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Estimated remaining time of command execution in ms (if not zero) */\n+\tuint32_t\tevent_data1;\n+} __attribute__((packed));\n+\n+/* hwrm_async_event_cmpl_pfc_watchdog_cfg_change (size:128b/16B) */\n+struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT \\\n+\t\t0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* PFC watchdog configuration change for given port/cos */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \\\n+\t\tUINT32_C(0x41)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V \\\n+\t\tUINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK \\\n+\t\tUINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/*\n+\t * 1 in bit position X indicates PFC watchdog should\n+\t * be on for COSX\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT \\\n+\t\t0\n+\t/* 1 means PFC WD for COS0 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 \\\n+\t\tUINT32_C(0x1)\n+\t/* 1 means PFC WD for COS1 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 \\\n+\t\tUINT32_C(0x2)\n+\t/* 1 means PFC WD for COS2 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 \\\n+\t\tUINT32_C(0x4)\n+\t/* 1 means PFC WD for COS3 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 \\\n+\t\tUINT32_C(0x8)\n+\t/* 1 means PFC WD for COS4 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 \\\n+\t\tUINT32_C(0x10)\n+\t/* 1 means PFC WD for COS5 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 \\\n+\t\tUINT32_C(0x20)\n+\t/* 1 means PFC WD for COS6 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 \\\n+\t\tUINT32_C(0x40)\n+\t/* 1 means PFC WD for COS7 is on, 0 - off. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 \\\n+\t\tUINT32_C(0x80)\n+\t/* PORT ID */\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK \\\n+\t\tUINT32_C(0xffff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT \\\n+\t\t8\n+} __attribute__((packed));\n+\n /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */\n struct hwrm_async_event_cmpl_fw_trace_msg {\n \tuint16_t\ttype;\n@@ -7220,7 +7481,7 @@ struct hwrm_func_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_func_qcaps_output (size:640b/80B) */\n+/* hwrm_func_qcaps_output (size:704b/88B) */\n struct hwrm_func_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -7441,6 +7702,33 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED \\\n \t\tUINT32_C(0x4000000)\n+\t/* If set to 1, then the vlan acceleration for TX is disabled. */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED \\\n+\t\tUINT32_C(0x8000000)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware supports\n+\t * DBG_COREDUMP_XXX commands.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED \\\n+\t\tUINT32_C(0x10000000)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware supports\n+\t * DBG_CRASHDUMP_XXX commands.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED \\\n+\t\tUINT32_C(0x20000000)\n+\t/*\n+\t * If the query is for a VF, then this flag should be ignored.\n+\t * If the query is for a PF and this flag is set to 1, then\n+\t * the PF has the capability to support retrieval of\n+\t * rx_port_stats_ext_pfc_wd statistics (supported by the PFC\n+\t * WatchDog feature) via the hwrm_port_qstats_ext_pfc_wd command.\n+\t * If this flag is set to 1, only that (supported) command should\n+\t * be used for retrieval of PFC related statistics (rather than\n+\t * hwrm_port_qstats_ext command, which could previously be used).\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x40000000)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -7551,7 +7839,22 @@ struct hwrm_func_qcaps_output {\n \t * (max_tx_rings) to the function.\n \t */\n \tuint16_t\tmax_sp_tx_rings;\n-\tuint8_t\tunused_0;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tflags_ext;\n+\t/*\n+\t * If 1, the device can be configured to set the ECN bits in the\n+\t * IP header of received packets if the receive queue length\n+\t * exceeds a given threshold.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If 1, the device can report the number of received packets\n+\t * that it marked as having experienced congestion.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -7606,7 +7909,7 @@ struct hwrm_func_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_func_qcfg_output (size:704b/88B) */\n+/* hwrm_func_qcfg_output (size:768b/96B) */\n struct hwrm_func_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -8016,7 +8319,17 @@ struct hwrm_func_qcfg_output {\n \t * this value to find out the doorbell page offset from the BAR.\n \t */\n \tuint16_t\tlegacy_l2_db_size_kb;\n-\tuint8_t\tunused_2[1];\n+\tuint16_t\tsvif_info;\n+\t/*\n+\t * This field specifies the source virtual interface of the function being\n+\t * queried. Drivers can use this to program svif field in the L2 context\n+\t * table\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK      UINT32_C(0x7fff)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT       0\n+\t/* This field specifies whether svif is valid or not */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID     UINT32_C(0x8000)\n+\tuint8_t\tunused_2[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -9862,8 +10175,12 @@ struct hwrm_func_backing_store_qcaps_output {\n \tuint32_t\trsvd;\n \t/* Reserved for future. */\n \tuint16_t\trsvd1;\n-\t/* Reserved for future. */\n-\tuint8_t\trsvd2;\n+\t/*\n+\t * Count of TQM fastpath rings to be used for allocating backing store.\n+\t * Backing store configuration must be specified for each TQM ring from\n+\t * this count in `backing_store_cfg`.\n+\t */\n+\tuint8_t\ttqm_fp_rings_count;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -12178,116 +12495,163 @@ struct hwrm_error_recovery_qcfg_output {\n \t * this much time after writing reset_reg_val in reset_reg.\n \t */\n \tuint8_t\tdelay_after_reset[16];\n-\tuint8_t\tunused_1[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal\n-\t * processor, the order of writes has to be such that this field\n-\t * is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n-\n-\n-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n-struct hwrm_func_vlan_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n+\t * Error recovery counter.\n+\t * Lower 2 bits indicates address space location and upper 30 bits\n+\t * indicates actual address.\n+\t * A value of 0xFFFF-FFFF indicates this register does not exist.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint32_t\terr_recovery_cnt_reg;\n+\t/* Lower 2 bits indicates address space location. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT \\\n+\t\t0\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * If value is 0, this register is located in PCIe config space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n \t */\n-\tuint64_t\tresp_addr;\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG \\\n+\t\tUINT32_C(0x0)\n \t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n+\t * If value is 1, this register is located in GRC address space.\n+\t * Drivers have to map appropriate window to access this\n+\t * register.\n \t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n-struct hwrm_func_vlan_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint64_t\tunused_0;\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * If value is 2, this register is located in first BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n \t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n+\t * If value is 3, this register is located in second BAR address\n+\t * space. Drivers have to map appropriate window to access this\n+\t * register.\n \t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\t/* Future use. */\n-\tuint32_t\trsvd3;\n-\tuint8_t\tunused_3[3];\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST \\\n+\t\tHWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1\n+\t/* Upper 30bits of the register address. */\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK \\\n+\t\tUINT32_C(0xfffffffc)\n+\t#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SFT \\\n+\t\t2\n+\tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_func_vlan_cfg *\n- **********************/\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n \n \n-/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n-struct hwrm_func_vlan_cfg_input {\n+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n+struct hwrm_func_vlan_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n+struct hwrm_func_vlan_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint64_t\tunused_0;\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\t/* Future use. */\n+\tuint32_t\trsvd3;\n+\tuint8_t\tunused_3[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_func_vlan_cfg *\n+ **********************/\n+\n+\n+/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n+struct hwrm_func_vlan_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -14039,6 +14403,9 @@ struct hwrm_port_phy_qcfg_output {\n \t/* Module is not inserted. */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \\\n \t\tUINT32_C(0x4)\n+\t/* Module is powered down becuase of over current fault. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT \\\n+\t\tUINT32_C(0x5)\n \t/* Module status is not applicable. */\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \\\n \t\tUINT32_C(0xff)\n@@ -15010,7 +15377,7 @@ struct hwrm_port_mac_qcfg_input {\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_port_mac_qcfg_output (size:192b/24B) */\n+/* hwrm_port_mac_qcfg_output (size:256b/32B) */\n struct hwrm_port_mac_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -15250,6 +15617,20 @@ struct hwrm_port_mac_qcfg_output {\n \t\tUINT32_C(0xe0)\n \t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \\\n \t\t5\n+\tuint8_t\tunused_1;\n+\tuint16_t\tport_svif_info;\n+\t/*\n+\t * This field specifies the source virtual interface of the port being\n+\t * queried. Drivers can use this to program port svif field in the\n+\t * L2 context table\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK \\\n+\t\tUINT32_C(0x7fff)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT       0\n+\t/* This field specifies whether port_svif is valid or not */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID \\\n+\t\tUINT32_C(0x8000)\n+\tuint8_t\tunused_2[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -15322,17 +15703,17 @@ struct hwrm_port_mac_ptp_qcfg_output {\n \t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', the PTP information is accessible\n-\t * via HWRM commands.\n-\t */\n-\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \\\n-\t\tUINT32_C(0x2)\n-\t/*\n \t * When this bit is set to '1', the device supports one-step\n \t * Tx timestamping.\n \t */\n \t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \\\n \t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is set to '1', the PTP information is accessible\n+\t * via HWRM commands.\n+\t */\n+\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \\\n+\t\tUINT32_C(0x8)\n \tuint8_t\tunused_0[3];\n \t/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */\n \tuint32_t\trx_ts_reg_off_lower;\n@@ -15375,7 +15756,7 @@ struct hwrm_port_mac_ptp_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/* Port Tx Statistics Formats */\n+/* Port Tx Statistics Format */\n /* tx_port_stats (size:3264b/408B) */\n struct tx_port_stats {\n \t/* Total Number of 64 Bytes frames transmitted */\n@@ -15516,7 +15897,7 @@ struct tx_port_stats {\n \tuint64_t\ttx_stat_error;\n } __attribute__((packed));\n \n-/* Port Rx Statistics Formats */\n+/* Port Rx Statistics Format */\n /* rx_port_stats (size:4224b/528B) */\n struct rx_port_stats {\n \t/* Total Number of 64 Bytes frames received */\n@@ -15806,7 +16187,7 @@ struct hwrm_port_qstats_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/* Port Tx Statistics extended Formats */\n+/* Port Tx Statistics extended Format */\n /* tx_port_stats_ext (size:2048b/256B) */\n struct tx_port_stats_ext {\n \t/* Total number of tx bytes count on cos queue 0 */\n@@ -15875,7 +16256,7 @@ struct tx_port_stats_ext {\n \tuint64_t\tpfc_pri7_tx_transitions;\n } __attribute__((packed));\n \n-/* Port Rx Statistics extended Formats */\n+/* Port Rx Statistics extended Format */\n /* rx_port_stats_ext (size:3648b/456B) */\n struct rx_port_stats_ext {\n \t/* Number of times link state changed to down */\n@@ -15997,6 +16378,424 @@ struct rx_port_stats_ext {\n \tuint64_t\trx_discard_packets_cos7;\n } __attribute__((packed));\n \n+/*\n+ * Port Rx Statistics extended PFC WatchDog Format.\n+ * StormDetect and StormRevert event determination is based\n+ * on an integration period and a percentage threshold.\n+ * StormDetect event - when percentage of XOFF frames receieved\n+ * within an integration period exceeds the configured threshold.\n+ * StormRevert event - when percentage of XON frames received\n+ * within an integration period exceeds the configured threshold.\n+ * Actual number of XOFF/XON frames for the events to be triggered\n+ * depends on both configured integration period and sampling rate.\n+ * The statistics in this structure represent counts of specified\n+ * events from the moment the feature (PFC WatchDog) is enabled via\n+ * hwrm_queue_pfc_enable_cfg call.\n+ */\n+/* rx_port_stats_ext_pfc_wd (size:5120b/640B) */\n+struct rx_port_stats_ext_pfc_wd {\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri0;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri1;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri2;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri3;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri4;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri5;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri6;\n+\t/*\n+\t * Total number of PFC WatchDog StormDetect events detected\n+\t * for Pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_detected_pri7;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri0;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri1;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri2;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri3;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri4;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri5;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri6;\n+\t/*\n+\t * Total number of PFC WatchDog StormRevert events detected\n+\t * for Pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_reverted_pri7;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri0;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri1;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri2;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri3;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri4;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri5;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri6;\n+\t/*\n+\t * Total number of packets received during PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_pri7;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri0;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri1;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri2;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri3;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri4;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri5;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri6;\n+\t/*\n+\t * Total number of bytes received during PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_pri7;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri0;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri1;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri2;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri3;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri4;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri5;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri6;\n+\t/*\n+\t * Total number of packets dropped on rx during PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_packets_dropped_pri7;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri0;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri1;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri2;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri3;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri4;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri5;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri6;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_storms_rx_bytes_dropped_pri7;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri0;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri1;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri2;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri3;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri4;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri5;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri6;\n+\t/*\n+\t * Number of packets received during last PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_pri7;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri0;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri1;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri2;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri3;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri4;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri5;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri6;\n+\t/*\n+\t * Number of bytes received during last PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_pri7;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri0;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri1;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri2;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri3;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri4;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri5;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri6;\n+\t/*\n+\t * Number of packets dropped on rx during last PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_packets_dropped_pri7;\n+\t/*\n+\t * Total number of bytes dropped on rx during PFC watchdog storm\n+\t * for pri 0\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri0;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t * for pri 1\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri1;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 2\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri2;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 3\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri3;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 4\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri4;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 5\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri5;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 6\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri6;\n+\t/*\n+\t * Number of bytes dropped on rx during last PFC watchdog storm\n+\t *  for pri 7\n+\t */\n+\tuint64_t\trx_pfc_watchdog_last_storm_rx_bytes_dropped_pri7;\n+} __attribute__((packed));\n+\n /************************\n  * hwrm_port_qstats_ext *\n  ************************/\n@@ -16090,6 +16889,83 @@ struct hwrm_port_qstats_ext_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/*******************************\n+ * hwrm_port_qstats_ext_pfc_wd *\n+ *******************************/\n+\n+\n+/* hwrm_port_qstats_ext_pfc_wd_input (size:256b/32B) */\n+struct hwrm_port_qstats_ext_pfc_wd_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is being queried. */\n+\tuint16_t\tport_id;\n+\t/*\n+\t * The size of rx_port_stats_ext_pfc_wd\n+\t * block in bytes\n+\t */\n+\tuint16_t\tpfc_wd_stat_size;\n+\tuint8_t\tunused_0[4];\n+\t/*\n+\t * This is the host address where\n+\t * rx_port_stats_ext_pfc_wd will be stored\n+\t */\n+\tuint64_t\tpfc_wd_stat_host_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_port_qstats_ext_pfc_wd_output (size:128b/16B) */\n+struct hwrm_port_qstats_ext_pfc_wd_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * The size of rx_port_stats_ext_pfc_wd\n+\t * statistics block in bytes.\n+\t */\n+\tuint16_t\tpfc_wd_stat_size;\n+\tuint8_t\tflags;\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n /*************************\n  * hwrm_port_lpbk_qstats *\n  *************************/\n@@ -16168,6 +17044,91 @@ struct hwrm_port_lpbk_qstats_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/************************\n+ * hwrm_port_ecn_qstats *\n+ ************************/\n+\n+\n+/* hwrm_port_ecn_qstats_input (size:192b/24B) */\n+struct hwrm_port_ecn_qstats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port that is being queried. Unused if NIC is in\n+\t * multi-host mode.\n+\t */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_port_ecn_qstats_output (size:384b/48B) */\n+struct hwrm_port_ecn_qstats_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of packets marked in CoS queue 0. */\n+\tuint32_t\tmark_cnt_cos0;\n+\t/* Number of packets marked in CoS queue 1. */\n+\tuint32_t\tmark_cnt_cos1;\n+\t/* Number of packets marked in CoS queue 2. */\n+\tuint32_t\tmark_cnt_cos2;\n+\t/* Number of packets marked in CoS queue 3. */\n+\tuint32_t\tmark_cnt_cos3;\n+\t/* Number of packets marked in CoS queue 4. */\n+\tuint32_t\tmark_cnt_cos4;\n+\t/* Number of packets marked in CoS queue 5. */\n+\tuint32_t\tmark_cnt_cos5;\n+\t/* Number of packets marked in CoS queue 6. */\n+\tuint32_t\tmark_cnt_cos6;\n+\t/* Number of packets marked in CoS queue 7. */\n+\tuint32_t\tmark_cnt_cos7;\n+\t/*\n+\t * Bitmask that indicates which CoS queues have ECN marking enabled.\n+\t * Bit i corresponds to CoS queue i.\n+\t */\n+\tuint8_t\tmark_en;\n+\tuint8_t\tunused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /***********************\n  * hwrm_port_clr_stats *\n  ***********************/\n@@ -18322,7 +19283,7 @@ struct hwrm_port_phy_mdio_bus_acquire_input {\n \t * Timeout in milli seconds, MDIO BUS will be released automatically\n \t * after this time, if another mdio acquire command is not received\n \t * within the timeout window from the same client.\n-\t * A 0xFFFF will hold the bus until this bus is released.\n+\t * A 0xFFFF will hold the bus untill this bus is released.\n \t */\n \tuint16_t\tmdio_bus_timeout;\n \tuint8_t\tunused_0[2];\n@@ -19158,6 +20119,30 @@ struct hwrm_queue_pfcenable_qcfg_output {\n \t/* If set to 1, then PFC is enabled on PRI 7. */\n \t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \\\n \t\tUINT32_C(0x80)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x100)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x200)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x400)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x800)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x1000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x2000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x4000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x8000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -19229,6 +20214,30 @@ struct hwrm_queue_pfcenable_cfg_input {\n \t/* If set to 1, then PFC is requested to be enabled on PRI 7. */\n \t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \\\n \t\tUINT32_C(0x80)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI0. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x100)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI1. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x200)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI2. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x400)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI3. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x800)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI4. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x1000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI5. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x2000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI6. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x4000)\n+\t/* If set to 1, then PFC WatchDog is requested to be enabled on PRI7. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED \\\n+\t\tUINT32_C(0x8000)\n \t/*\n \t * Port ID of port for which the table is being configured.\n \t * The HWRM needs to check whether this function is allowed\n@@ -31831,15 +32840,2172 @@ struct hwrm_cfa_eem_qcfg_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* When set to 1, indicates the configuration is the TX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)\n-\t/* When set to 1, indicates the configuration is the RX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)\n-\tuint32_t\tunused_0;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)\n+\tuint32_t\tunused_0;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */\n+struct hwrm_cfa_eem_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/* When set to 1, indicates the configuration is the TX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x1)\n+\t/* When set to 1, indicates the configuration is the RX flow. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, all offloaded flows will be sent to EEM. */\n+\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x4)\n+\t/* The number of entries the FW has configured for EEM. */\n+\tuint32_t\tnum_entries;\n+\t/* Configured EEM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EEM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EEM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EEM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\tuint8_t\tunused_2[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************\n+ * hwrm_cfa_eem_op *\n+ *******************/\n+\n+\n+/* hwrm_cfa_eem_op_input (size:192b/24B) */\n+struct hwrm_cfa_eem_op_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the TX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_rx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the host memory which is passed will be\n+\t * used for the RX flow offload function specified in fid.\n+\t * Note if this bit is set then the path_tx bit can't be set.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)\n+\tuint16_t\tunused_0;\n+\t/* The number of EEM key table entries to be configured. */\n+\tuint16_t\top;\n+\t/* This value is reserved and should not be used. */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED    UINT32_C(0x0)\n+\t/*\n+\t * To properly stop EEM and ensure there are no DMA's, the caller\n+\t * must disable EEM for the given PF, using this call. This will\n+\t * safely disable EEM and ensure that all DMA'ed to the\n+\t * keys/records/efc have been completed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)\n+\t/*\n+\t * Once the EEM host memory has been configured, EEM options have\n+\t * been configured. Then the caller should enable EEM for the given\n+\t * PF. Note once this call has been made, then the EEM mechanism\n+\t * will be active and DMA's will occur as packets are processed.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)\n+\t/*\n+\t * Clear EEM settings for the given PF so that the register values\n+\t * are reset back to there initial state.\n+\t */\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)\n+\t#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \\\n+\t\tHWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_eem_op_output (size:128b/16B) */\n+struct hwrm_cfa_eem_op_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************************\n+ * hwrm_cfa_adv_flow_mgnt_qcaps *\n+ ********************************/\n+\n+\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */\n+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Value of 1 to indicate firmware support 16-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 16-bit flow handle.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * Value of 1 to indicate firmware support 64-bit flow handle.\n+\t * Value of 0 to indicate firmware not support 64-bit flow handle.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Value of 1 to indicate firmware support flow batch delete operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 to indicate that the firmware does not support flow batch delete\n+\t * operation.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Value of 1 to indicate that the firmware support flow reset all operation through\n+\t * HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 indicates firmware does not support flow reset all operation.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n+\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n+\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports TX EEM flows.\n+\t * Value of 0 indicates firmware does not support TX EEM flows.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports RX EEM flows.\n+\t * Value of 0 indicates firmware does not support RX EEM flows.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports the dynamic allocation of an\n+\t * on-chip flow counter which can be used for EEM flows.\n+\t * Value of 0 indicates firmware does not support the dynamic allocation of an\n+\t * on-chip flow counter.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.\n+\t * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports untagged matching\n+\t * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0\n+\t * indicates firmware does not support untagged matching.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports XDP filter. Value\n+\t * of 0 indicates firmware does not support XDP filter.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * Value of 1 to indicate that the firmware support L2 header source\n+\t * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.\n+\t * Value of 0 indicates firmware does not support L2 header source\n+\t * fields matching.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting ARP ethertype as\n+\t * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the\n+\t * RX direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * Value of 1 to indicate that firmware supports setting of\n+\t * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC\n+\t * command. Value of 0 indicates firmware does not support\n+\t * rfs_ring_tbl_idx in dst_id field.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting IPv4/IPv6 as\n+\t * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX\n+\t * direction. By default, this flag should be 0 for older version\n+\t * of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************\n+ * hwrm_cfa_tflib *\n+ ******************/\n+\n+\n+/* hwrm_cfa_tflib_input (size:1024b/128B) */\n+struct hwrm_cfa_tflib_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* TFLIB message type. */\n+\tuint16_t\ttf_type;\n+\t/* TFLIB message subtype. */\n+\tuint16_t\ttf_subtype;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/* TFLIB request data. */\n+\tuint32_t\ttf_req[26];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_tflib_output (size:5632b/704B) */\n+struct hwrm_cfa_tflib_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* TFLIB message type. */\n+\tuint16_t\ttf_type;\n+\t/* TFLIB message subtype. */\n+\tuint16_t\ttf_subtype;\n+\t/* TFLIB response code */\n+\tuint32_t\ttf_resp_code;\n+\t/* TFLIB response data. */\n+\tuint32_t\ttf_resp[170];\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********\n+ * hwrm_tf *\n+ ***********/\n+\n+\n+/* hwrm_tf_input (size:1024b/128B) */\n+struct hwrm_tf_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* TF message type. */\n+\tuint16_t\ttype;\n+\t/* TF message subtype. */\n+\tuint16_t\tsubtype;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/* TF request data. */\n+\tuint32_t\treq[26];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_output (size:5632b/704B) */\n+struct hwrm_tf_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* TF message type. */\n+\tuint16_t\ttype;\n+\t/* TF message subtype. */\n+\tuint16_t\tsubtype;\n+\t/* TF response code */\n+\tuint32_t\tresp_code;\n+\t/* TF response data. */\n+\tuint32_t\tresp[170];\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_tf_version_get *\n+ ***********************/\n+\n+\n+/* hwrm_tf_version_get_input (size:128b/16B) */\n+struct hwrm_tf_version_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_version_get_output (size:128b/16B) */\n+struct hwrm_tf_version_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Version Major number. */\n+\tuint8_t\tmajor;\n+\t/* Version Minor number. */\n+\tuint8_t\tminor;\n+\t/* Version Update number. */\n+\tuint8_t\tupdate;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_tf_session_open *\n+ ************************/\n+\n+\n+/* hwrm_tf_session_open_input (size:640b/80B) */\n+struct hwrm_tf_session_open_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Name of the session. */\n+\tuint8_t\tsession_name[64];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_open_output (size:128b/16B) */\n+struct hwrm_tf_session_open_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. It includes PCIe bus info to distinguish the PF\n+\t * and session info to identify the associated TruFlow\n+\t * session.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**************************\n+ * hwrm_tf_session_attach *\n+ **************************/\n+\n+\n+/* hwrm_tf_session_attach_input (size:704b/88B) */\n+struct hwrm_tf_session_attach_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Unique session identifier for the session that the attach\n+\t * request want to attach to. This value originates from the\n+\t * shared session memory that the attach request opened by\n+\t * way of the 'attach name' that was passed in to the core\n+\t * attach API.\n+\t * The fw_session_id of the attach session includes PCIe bus\n+\t * info to distinguish the PF and session info to identify\n+\t * the associated TruFlow session.\n+\t */\n+\tuint32_t\tattach_fw_session_id;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Name of the session it self. */\n+\tuint8_t\tsession_name[64];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_attach_output (size:128b/16B) */\n+struct hwrm_tf_session_attach_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Unique session identifier for the session created by the\n+\t * firmware. It includes PCIe bus info to distinguish the PF\n+\t * and session info to identify the associated TruFlow\n+\t * session. This fw_session_id is unique to the attach\n+\t * request.\n+\t */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_tf_session_close *\n+ *************************/\n+\n+\n+/* hwrm_tf_session_close_input (size:192b/24B) */\n+struct hwrm_tf_session_close_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_close_output (size:128b/16B) */\n+struct hwrm_tf_session_close_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_tf_session_qcfg *\n+ ************************/\n+\n+\n+/* hwrm_tf_session_qcfg_input (size:192b/24B) */\n+struct hwrm_tf_session_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_qcfg_output (size:128b/16B) */\n+struct hwrm_tf_session_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* RX action control settings flags. */\n+\tuint8_t\trx_act_flags;\n+\t/*\n+\t * A value of 1 in this field indicates that Global Flow ID\n+\t * reporting into cfa_code and cfa_metadata is enabled.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * A value of 1 in this field indicates that both inner and outer\n+\t * are stripped and inner tag is passed.\n+\t * Enabled.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * A value of 1 in this field indicates that the re-use of\n+\t * existing tunnel L2 header SMAC is enabled for\n+\t * Non-tunnel L2, L2-L3 and IP-IP tunnel.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 \\\n+\t\tUINT32_C(0x4)\n+\t/* TX Action control settings flags. */\n+\tuint8_t\ttx_act_flags;\n+\t/* Disabled. */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1 any GRE tunnels will include the\n+\t * optional Key field.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When set to 1, for GRE tunnels, the IPV6 Traffic Class (TC)\n+\t * field of the outer header is inherited from the inner header\n+\t * (if present) or the fixed value as taken from the encap\n+\t * record.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When set to 1, for GRE tunnels, the IPV4 Type Of Service (TOS)\n+\t * field of the outer header is inherited from the inner header\n+\t * (if present) or the fixed value as taken from the encap record.\n+\t */\n+\t#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH \\\n+\t\tUINT32_C(0x8)\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_tf_session_resc_qcaps *\n+ ******************************/\n+\n+\n+/* hwrm_tf_session_resc_qcaps_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided qcaps_addr\n+\t * buffer. The size should be set to the Resource Manager\n+\t * provided max qcaps value that is device specific. This is\n+\t * the max size possible.\n+\t */\n+\tuint16_t\tsize;\n+\t/*\n+\t * This is the DMA address for the qcaps output data\n+\t * array. Array is of tf_rm_cap type and is device specific.\n+\t */\n+\tuint64_t\tqcaps_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_resc_qcaps_output (size:192b/24B) */\n+struct hwrm_tf_session_resc_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Session reservation strategy. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_MASK \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_SFT \\\n+\t\t0\n+\t/* Static partitioning. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_STATIC \\\n+\t\tUINT32_C(0x0)\n+\t/* Strategy 1. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_1 \\\n+\t\tUINT32_C(0x1)\n+\t/* Strategy 2. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_2 \\\n+\t\tUINT32_C(0x2)\n+\t/* Strategy 3. */\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3 \\\n+\t\tUINT32_C(0x3)\n+\t#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RES_STRATEGY_3\n+\t/*\n+\t * Size of the returned tf_rm_cap data array. The value\n+\t * cannot exceed the size defined by the input msg. The data\n+\t * array is returned using the qcaps_addr specified DMA\n+\t * address also provided by the input msg.\n+\t */\n+\tuint16_t\tsize;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_tf_session_resc_alloc *\n+ ******************************/\n+\n+\n+/* hwrm_tf_session_resc_alloc_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided num_addr\n+\t * buffer.\n+\t */\n+\tuint16_t\tsize;\n+\t/*\n+\t * This is the DMA address for the num input data array\n+\t * buffer. Array is of tf_rm_num type. Size of the buffer is\n+\t * provided by the 'size' field in this message.\n+\t */\n+\tuint64_t\tnum_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_resc_alloc_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*****************************\n+ * hwrm_tf_session_resc_free *\n+ *****************************/\n+\n+\n+/* hwrm_tf_session_resc_free_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_FREE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided free_addr\n+\t * buffer.\n+\t */\n+\tuint16_t\tsize;\n+\t/*\n+\t * This is the DMA address for the free input data array\n+\t * buffer.  Array of tf_rm_res type. Size of the buffer is\n+\t * provided by the 'size field of this message.\n+\t */\n+\tuint64_t\tfree_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_resc_free_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_tf_session_resc_flush *\n+ ******************************/\n+\n+\n+/* hwrm_tf_session_resc_flush_input (size:256b/32B) */\n+struct hwrm_tf_session_resc_flush_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Defines the size, in bytes, of the provided flush_addr\n+\t * buffer.\n+\t */\n+\tuint16_t\tsize;\n+\t/*\n+\t * This is the DMA address for the flush input data array\n+\t * buffer.  Array of tf_rm_res type. Size of the buffer is\n+\t * provided by the 'size' field in this message.\n+\t */\n+\tuint64_t\tflush_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_session_resc_flush_output (size:128b/16B) */\n+struct hwrm_tf_session_resc_flush_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/* TruFlow RM capability of a resource. */\n+/* tf_rm_cap (size:64b/8B) */\n+struct tf_rm_cap {\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Minimum value. */\n+\tuint16_t\tmin;\n+\t/* Maximum value. */\n+\tuint16_t\tmax;\n+} __attribute__((packed));\n+\n+/* TruFlow RM number of a resource. */\n+/* tf_rm_num (size:64b/8B) */\n+struct tf_rm_num {\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Number of resources. */\n+\tuint32_t\tnum;\n+} __attribute__((packed));\n+\n+/* TruFlow RM reservation information. */\n+/* tf_rm_res (size:64b/8B) */\n+struct tf_rm_res {\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Start offset. */\n+\tuint16_t\tstart;\n+\t/* Number of resources. */\n+\tuint16_t\tstride;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_tf_tbl_type_get *\n+ ************************/\n+\n+\n+/* hwrm_tf_tbl_type_get_input (size:256b/32B) */\n+struct hwrm_tf_tbl_type_get_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */\n+struct hwrm_tf_tbl_type_get_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Response code. */\n+\tuint32_t\tresp_code;\n+\t/* Response size. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint16_t\tunused0;\n+\t/* Response data. */\n+\tuint8_t\tdata[128];\n+\t/* unused */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_tf_tbl_type_set *\n+ ************************/\n+\n+\n+/* hwrm_tf_tbl_type_set_input (size:1024b/128B) */\n+struct hwrm_tf_tbl_type_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint8_t\tunused0[2];\n+\t/*\n+\t * Type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of the type to retrieve. */\n+\tuint32_t\tindex;\n+\t/* Size of the data to set. */\n+\tuint16_t\tsize;\n+\t/* unused */\n+\tuint8_t\tunused1[6];\n+\t/* Data to be set. */\n+\tuint8_t\tdata[88];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_tbl_type_set_output (size:128b/16B) */\n+struct hwrm_tf_tbl_type_set_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field\n+\t * is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_tf_ctxt_mem_rgtr *\n+ *************************/\n+\n+\n+/* hwrm_tf_ctxt_mem_rgtr_input (size:256b/32B) */\n+struct hwrm_tf_ctxt_mem_rgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Counter PBL indirect levels. */\n+\tuint8_t\tpage_level;\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing\n+\t * to PTE tables.\n+\t */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n+\t/* Page size. */\n+\tuint8_t\tpage_size;\n+\t/* 4KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)\n+\t/* 8KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)\n+\t/* 64KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)\n+\t/* 256KB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)\n+\t/* 1MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)\n+\t/* 2MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)\n+\t/* 4MB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)\n+\t/* 1GB page size. */\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)\n+\t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n+\t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ctxt_mem_rgtr_output (size:128b/16B) */\n+struct hwrm_tf_ctxt_mem_rgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This\n+\t * handle is passed to the TF session.\n+\t */\n+\tuint16_t\tctx_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_tf_ctxt_mem_unrgtr *\n+ ***************************/\n+\n+\n+/* hwrm_tf_ctxt_mem_unrgtr_input (size:192b/24B) */\n+struct hwrm_tf_ctxt_mem_unrgtr_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Id/Handle to the recently register context memory. This\n+\t * handle is passed to the TF session.\n+\t */\n+\tuint16_t\tctx_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */\n+struct hwrm_tf_ctxt_mem_unrgtr_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_tf_ext_em_qcaps *\n+ ************************/\n+\n+\n+/* hwrm_tf_ext_em_qcaps_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ext_em_qcaps_output (size:320b/40B) */\n+struct hwrm_tf_ext_em_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Centralized\n+\t * Memory Model. The concept designates one entity for the\n+\t * memory allocation while all others ‘subscribe’ to it.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When set to 1, indicates the the FW supports the Detached\n+\t * Centralized Memory Model. The memory is allocated and managed\n+\t * as a separate entity. All PFs and VFs will be granted direct\n+\t * or semi-direct access to the allocated memory while none of\n+\t * which can interfere with the management of the memory.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+\t/* Support flags. */\n+\tuint32_t\tsupported;\n+\t/*\n+\t * If set to 1, then EXT EM KEY0 table is supported using\n+\t * crc32 hash.\n+\t * If set to 0, EXT EM KEY0 table is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, then EXT EM KEY1 table is supported using\n+\t * lookup3 hash.\n+\t * If set to 0, EXT EM KEY1 table is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, then EXT EM External Record table is supported.\n+\t * If set to 0, EXT EM External Record table is not\n+\t * supported.  (This table includes action record, EFC\n+\t * pointers, encap pointers)\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, then EXT EM External Flow Counters table is\n+\t * supported.\n+\t * If set to 0, EXT EM External Flow Counters table is not\n+\t * supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, then FID table used for implicit flow flush\n+\t * is supported.\n+\t * If set to 0, then FID table used for implicit flow flush\n+\t * is not supported.\n+\t */\n+\t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * The maximum number of entries supported by EXT EM. When\n+\t * configuring the host memory the number of numbers of\n+\t * entries that can supported are -\n+\t *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M,\n+\t *      128M entries.\n+\t * Any value that are not these values, the FW will round\n+\t * down to the closest support number of entries.\n+\t */\n+\tuint32_t\tmax_entries_supported;\n+\t/*\n+\t * The entry size in bytes of each entry in the EXT EM\n+\t * KEY0/KEY1 tables.\n+\t */\n+\tuint16_t\tkey_entry_size;\n+\t/*\n+\t * The entry size in bytes of each entry in the EXT EM RECORD\n+\t * tables.\n+\t */\n+\tuint16_t\trecord_entry_size;\n+\t/* The entry size in bytes of each entry in the EXT EM EFC tables. */\n+\tuint16_t\tefc_entry_size;\n+\t/* The FID size in bytes of each entry in the EXT EM FID tables. */\n+\tuint16_t\tfid_entry_size;\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_tf_ext_em_op *\n+ *********************/\n+\n+\n+/* hwrm_tf_ext_em_op_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_op_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_OP_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* The number of EXT EM key table entries to be configured. */\n+\tuint16_t\top;\n+\t/* This value is reserved and should not be used. */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_RESERVED       UINT32_C(0x0)\n+\t/*\n+\t * To properly stop EXT EM and ensure there are no DMA's,\n+\t * the caller must disable EXT EM for the given PF, using\n+\t * this call. This will safely disable EXT EM and ensure\n+\t * that all DMA'ed to the keys/records/efc have been\n+\t * completed.\n+\t */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_DISABLE UINT32_C(0x1)\n+\t/*\n+\t * Once the EXT EM host memory has been configured, EXT EM\n+\t * options have been configured. Then the caller should\n+\t * enable EXT EM for the given PF. Note once this call has\n+\t * been made, then the EXT EM mechanism will be active and\n+\t * DMA's will occur as packets are processed.\n+\t */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_ENABLE  UINT32_C(0x2)\n+\t/*\n+\t * Clear EXT EM settings for the given PF so that the\n+\t * register values are reset back to their initial state.\n+\t */\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP UINT32_C(0x3)\n+\t#define HWRM_TF_EXT_EM_OP_INPUT_OP_LAST \\\n+\t\tHWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP\n+\t/* unused. */\n+\tuint16_t\tunused1;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ext_em_op_output (size:128b/16B) */\n+struct hwrm_tf_ext_em_op_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_tf_ext_em_cfg *\n+ **********************/\n+\n+\n+/* hwrm_tf_ext_em_cfg_input (size:384b/48B) */\n+struct hwrm_tf_ext_em_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_CFG_INPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n+\t/* When set to 1, secondary, 0 means primary. */\n+\t#define HWRM_TF_EXT_EM_CFG_INPUT_FLAGS_SECONDARY_PF \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Group_id which used by Firmware to identify memory pools belonging\n+\t * to certain group.\n+\t */\n+\tuint16_t\tgroup_id;\n+\t/*\n+\t * Dynamically reconfigure EEM pending cache every 1/10th of second.\n+\t * If set to 0 it will disable the EEM HW flush of the pending cache.\n+\t */\n+\tuint8_t\tflush_interval;\n+\t/* unused. */\n+\tuint8_t\tunused0;\n+\t/*\n+\t * Configured EXT EM with the given number of entries. All\n+\t * the EXT EM tables KEY0, KEY1, RECORD, EFC all have the\n+\t * same number of entries and all tables will be configured\n+\t * using this value. Current minimum value is 32k. Current\n+\t * maximum value is 128M.\n+\t */\n+\tuint32_t\tnum_entries;\n+\t/* unused. */\n+\tuint32_t\tunused1;\n+\t/* Configured EXT EM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EXT EM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EXT EM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\t/* unused. */\n+\tuint16_t\tunused2;\n+\t/* unused. */\n+\tuint32_t\tunused3;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ext_em_cfg_output (size:128b/16B) */\n+struct hwrm_tf_ext_em_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_tf_ext_em_qcfg *\n+ ***********************/\n+\n+\n+/* hwrm_tf_ext_em_qcfg_input (size:192b/24B) */\n+struct hwrm_tf_ext_em_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+} __attribute__((packed));\n+\n+/* hwrm_tf_ext_em_qcfg_output (size:256b/32B) */\n+struct hwrm_tf_ext_em_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR \\\n+\t\tUINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_RX \\\n+\t\tUINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_DIR_TX\n+\t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n+\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n+\t\tUINT32_C(0x2)\n+\t/* The number of entries the FW has configured for EXT EM. */\n+\tuint32_t\tnum_entries;\n+\t/* Configured EXT EM with the given context if for KEY0 table. */\n+\tuint16_t\tkey0_ctx_id;\n+\t/* Configured EXT EM with the given context if for KEY1 table. */\n+\tuint16_t\tkey1_ctx_id;\n+\t/* Configured EXT EM with the given context if for RECORD table. */\n+\tuint16_t\trecord_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tefc_ctx_id;\n+\t/* Configured EXT EM with the given context if for EFC table. */\n+\tuint16_t\tfid_ctx_id;\n+\t/* unused. */\n+\tuint8_t\tunused0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************\n+ * hwrm_tf_tcam_set *\n+ ********************/\n+\n+\n+/* hwrm_tf_tcam_set_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_set_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * Indicate device data is being sent via DMA, the device\n+\t * data is packing does not change.\n+\t */\n+\t#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA     UINT32_C(0x2)\n+\t/*\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Index of TCAM entry. */\n+\tuint16_t\tidx;\n+\t/* Number of bytes in the TCAM key. */\n+\tuint8_t\tkey_size;\n+\t/* Number of bytes in the TCAM result. */\n+\tuint8_t\tresult_size;\n+\t/*\n+\t * Offset from which the mask bytes start in the device data\n+\t * array, key offset is always 0.\n+\t */\n+\tuint8_t\tmask_offset;\n+\t/* Offset from which the result bytes start in the device data array. */\n+\tuint8_t\tresult_offset;\n+\t/* unused. */\n+\tuint8_t\tunused0[6];\n+\t/*\n+\t * TCAM key located at offset 0, mask located at mask_offsec\n+\t * and result at result_offsec for the device.\n+\t */\n+\tuint8_t\tdev_data[88];\n } __attribute__((packed));\n \n-/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */\n-struct hwrm_cfa_eem_qcfg_output {\n+/* hwrm_tf_tcam_set_output (size:128b/16B) */\n+struct hwrm_tf_tcam_set_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -31848,46 +35014,26 @@ struct hwrm_cfa_eem_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/* When set to 1, indicates the configuration is the TX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x1)\n-\t/* When set to 1, indicates the configuration is the RX flow. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x2)\n-\t/* When set to 1, all offloaded flows will be sent to EEM. */\n-\t#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \\\n-\t\tUINT32_C(0x4)\n-\t/* The number of entries the FW has configured for EEM. */\n-\tuint32_t\tnum_entries;\n-\t/* Configured EEM with the given context if for KEY0 table. */\n-\tuint16_t\tkey0_ctx_id;\n-\t/* Configured EEM with the given context if for KEY1 table. */\n-\tuint16_t\tkey1_ctx_id;\n-\t/* Configured EEM with the given context if for RECORD table. */\n-\tuint16_t\trecord_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tefc_ctx_id;\n-\t/* Configured EEM with the given context if for EFC table. */\n-\tuint16_t\tfid_ctx_id;\n-\tuint8_t\tunused_2[5];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_cfa_eem_op *\n- *******************/\n+/********************\n+ * hwrm_tf_tcam_get *\n+ ********************/\n \n \n-/* hwrm_cfa_eem_op_input (size:192b/24B) */\n-struct hwrm_cfa_eem_op_input {\n+/* hwrm_tf_tcam_get_input (size:256b/32B) */\n+struct hwrm_tf_tcam_get_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -31916,49 +35062,31 @@ struct hwrm_cfa_eem_op_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n \tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX\n \t/*\n-\t * When set to 1, indicates the host memory which is passed will be\n-\t * used for the TX flow offload function specified in fid.\n-\t * Note if this bit is set then the path_rx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX     UINT32_C(0x1)\n-\t/*\n-\t * When set to 1, indicates the host memory which is passed will be\n-\t * used for the RX flow offload function specified in fid.\n-\t * Note if this bit is set then the path_tx bit can't be set.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX     UINT32_C(0x2)\n-\tuint16_t\tunused_0;\n-\t/* The number of EEM key table entries to be configured. */\n-\tuint16_t\top;\n-\t/* This value is reserved and should not be used. */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED    UINT32_C(0x0)\n-\t/*\n-\t * To properly stop EEM and ensure there are no DMA's, the caller\n-\t * must disable EEM for the given PF, using this call. This will\n-\t * safely disable EEM and ensure that all DMA'ed to the\n-\t * keys/records/efc have been completed.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)\n-\t/*\n-\t * Once the EEM host memory has been configured, EEM options have\n-\t * been configured. Then the caller should enable EEM for the given\n-\t * PF. Note once this call has been made, then the EEM mechanism\n-\t * will be active and DMA's will occur as packets are processed.\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n \t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)\n-\t/*\n-\t * Clear EEM settings for the given PF so that the register values\n-\t * are reset back to there initial state.\n-\t */\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)\n-\t#define HWRM_CFA_EEM_OP_INPUT_OP_LAST \\\n-\t\tHWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP\n+\tuint32_t\ttype;\n+\t/* Index of a TCAM entry. */\n+\tuint16_t\tidx;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n } __attribute__((packed));\n \n-/* hwrm_cfa_eem_op_output (size:128b/16B) */\n-struct hwrm_cfa_eem_op_output {\n+/* hwrm_tf_tcam_get_output (size:2368b/296B) */\n+struct hwrm_tf_tcam_get_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -31967,24 +35095,41 @@ struct hwrm_cfa_eem_op_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* Number of bytes in the TCAM key. */\n+\tuint8_t\tkey_size;\n+\t/* Number of bytes in the TCAM entry. */\n+\tuint8_t\tresult_size;\n+\t/* Offset from which the mask bytes start in the device data array. */\n+\tuint8_t\tmask_offset;\n+\t/* Offset from which the result bytes start in the device data array. */\n+\tuint8_t\tresult_offset;\n+\t/* unused. */\n+\tuint8_t\tunused0[4];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * TCAM key located at offset 0, mask located at mask_offsec\n+\t * and result at result_offsec for the device.\n+\t */\n+\tuint8_t\tdev_data[272];\n+\t/* unused. */\n+\tuint8_t\tunused1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_adv_flow_mgnt_qcaps *\n- ********************************/\n+/*********************\n+ * hwrm_tf_tcam_move *\n+ *********************/\n \n \n-/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */\n-struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n+/* hwrm_tf_tcam_move_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_move_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -32013,11 +35158,33 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tunused_0[4];\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Number of TCAM index pairs to be swapped for the device. */\n+\tuint16_t\tcount;\n+\t/* unused. */\n+\tuint16_t\tunused0;\n+\t/* TCAM index pairs to be swapped for the device. */\n+\tuint16_t\tidx_pairs[48];\n } __attribute__((packed));\n \n-/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */\n-struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n+/* hwrm_tf_tcam_move_output (size:128b/16B) */\n+struct hwrm_tf_tcam_move_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -32026,131 +35193,26 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/*\n-\t * Value of 1 to indicate firmware support 16-bit flow handle.\n-\t * Value of 0 to indicate firmware not support 16-bit flow handle.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * Value of 1 to indicate firmware support 64-bit flow handle.\n-\t * Value of 0 to indicate firmware not support 64-bit flow handle.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Value of 1 to indicate firmware support flow batch delete operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 to indicate that the firmware does not support flow batch delete\n-\t * operation.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * Value of 1 to indicate that the firmware support flow reset all operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 indicates firmware does not support flow reset all operation.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n-\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n-\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports TX EEM flows.\n-\t * Value of 0 indicates firmware does not support TX EEM flows.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports RX EEM flows.\n-\t * Value of 0 indicates firmware does not support RX EEM flows.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports the dynamic allocation of an\n-\t * on-chip flow counter which can be used for EEM flows.\n-\t * Value of 0 indicates firmware does not support the dynamic allocation of an\n-\t * on-chip flow counter.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports setting of\n-\t * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.\n-\t * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports untagged matching\n-\t * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0\n-\t * indicates firmware does not support untagged matching.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports XDP filter. Value\n-\t * of 0 indicates firmware does not support XDP filter.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * Value of 1 to indicate that the firmware support L2 header source\n-\t * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.\n-\t * Value of 0 indicates firmware does not support L2 header source\n-\t * fields matching.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \\\n-\t\tUINT32_C(0x800)\n-\t/*\n-\t * If set to 1, firmware is capable of supporting ARP ethertype as\n-\t * matching criteria for HWRM_CFA_NTUPLE_FILTER_ALLOC command on the\n-\t * RX direction. By default, this flag should be 0 for older version\n-\t * of firmware.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED \\\n-\t\tUINT32_C(0x1000)\n-\t/*\n-\t * Value of 1 to indicate that firmware supports setting of\n-\t * rfs_ring_tbl_idx in dst_id field of the HWRM_CFA_NTUPLE_ALLOC\n-\t * command. Value of 0 indicates firmware does not support\n-\t * rfs_ring_tbl_idx in dst_id field.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED \\\n-\t\tUINT32_C(0x2000)\n-\t/*\n-\t * If set to 1, firmware is capable of supporting IPv4/IPv6 as\n-\t * ethertype in HWRM_CFA_NTUPLE_FILTER_ALLOC command on the RX\n-\t * direction. By default, this flag should be 0 for older version\n-\t * of firmware.\n-\t */\n-\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n-\t\tUINT32_C(0x4000)\n-\tuint8_t\tunused_0[3];\n+\t/* unused. */\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************\n- * hwrm_cfa_tflib *\n- ******************/\n+/*********************\n+ * hwrm_tf_tcam_free *\n+ *********************/\n \n \n-/* hwrm_cfa_tflib_input (size:1024b/128B) */\n-struct hwrm_cfa_tflib_input {\n+/* hwrm_tf_tcam_free_input (size:1024b/128B) */\n+struct hwrm_tf_tcam_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -32179,18 +35241,33 @@ struct hwrm_cfa_tflib_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* TFLIB message type. */\n-\tuint16_t\ttf_type;\n-\t/* TFLIB message subtype. */\n-\tuint16_t\ttf_subtype;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control flags. */\n+\tuint32_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX\n+\t/*\n+\t * TCAM type of the resource, defined globally in the\n+\t * hwrm_tf_resc_type enum.\n+\t */\n+\tuint32_t\ttype;\n+\t/* Number of TCAM index to be deleted for the device. */\n+\tuint16_t\tcount;\n \t/* unused. */\n-\tuint8_t\tunused0[4];\n-\t/* TFLIB request data. */\n-\tuint32_t\ttf_req[26];\n+\tuint16_t\tunused0;\n+\t/* TCAM index list to be deleted for the device. */\n+\tuint16_t\tidx_list[48];\n } __attribute__((packed));\n \n-/* hwrm_cfa_tflib_output (size:5632b/704B) */\n-struct hwrm_cfa_tflib_output {\n+/* hwrm_tf_tcam_free_output (size:128b/16B) */\n+struct hwrm_tf_tcam_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -32199,22 +35276,15 @@ struct hwrm_cfa_tflib_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* TFLIB message type. */\n-\tuint16_t\ttf_type;\n-\t/* TFLIB message subtype. */\n-\tuint16_t\ttf_subtype;\n-\t/* TFLIB response code */\n-\tuint32_t\ttf_resp_code;\n-\t/* TFLIB response data. */\n-\tuint32_t\ttf_resp[170];\n \t/* unused. */\n-\tuint8_t\tunused1[7];\n+\tuint8_t\tunused0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field is used in Output records to indicate that the\n+\t * output is completely written to RAM. This field should be\n+\t * read as '1' to indicate that the output has been\n+\t * completely written.  When writing a command completion or\n+\t * response to an internal processor, the order of writes has\n+\t * to be such that this field is written last.\n \t */\n \tuint8_t\tvalid;\n } __attribute__((packed));\n@@ -33155,9 +36225,9 @@ struct pcie_ctx_hw_stats {\n \tuint64_t\tpcie_tl_signal_integrity;\n \t/* Number of times LTSSM entered Recovery state */\n \tuint64_t\tpcie_link_integrity;\n-\t/* Number of TLP bytes that have been transmitted */\n+\t/* Report number of TLP bits that have been transmitted in Mbps */\n \tuint64_t\tpcie_tx_traffic_rate;\n-\t/* Number of TLP bytes that have been received */\n+\t/* Report number of TLP bits that have been received in Mbps */\n \tuint64_t\tpcie_rx_traffic_rate;\n \t/* Number of DLLP bytes that have been transmitted */\n \tuint64_t\tpcie_tx_dllp_statistics;\n@@ -33981,7 +37051,23 @@ struct hwrm_nvm_modify_input {\n \tuint64_t\thost_src_addr;\n \t/* 16-bit directory entry index. */\n \tuint16_t\tdir_idx;\n-\tuint8_t\tunused_0[2];\n+\tuint16_t\tflags;\n+\t/*\n+\t * This flag indicates the sender wants to modify a continuous NVRAM\n+\t * area using a batch of this HWRM requests. The offset of a request\n+\t * must be continuous to the end of previous request's. Firmware does\n+\t * not update the directory entry until receiving the last request,\n+\t * which is indicated by the batch_last flag.\n+\t * This flag is set usually when a sender does not have a block of\n+\t * memory that is big enough to hold the entire NVRAM data for send\n+\t * at one time.\n+\t */\n+\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE     UINT32_C(0x1)\n+\t/*\n+\t * This flag can be used only when the batch_mode flag is set.\n+\t * It indicates this request is the last of batch requests.\n+\t */\n+\t#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST     UINT32_C(0x2)\n \t/* 32-bit NVRAM byte-offset to modify content from. */\n \tuint32_t\toffset;\n \t/*\n",
    "prefixes": [
        "v4",
        "01/34"
    ]
}