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GET /api/patches/68250/?format=api
{ "id": 68250, "url": "https://patches.dpdk.org/api/patches/68250/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200413063037.13728-9-alvinx.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200413063037.13728-9-alvinx.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200413063037.13728-9-alvinx.zhang@intel.com", "date": "2020-04-13T06:30:34", "name": "[v3,08/11] net/igc: implement RSS API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6672555802e14ad6fc86459f6f5b76c99eb2d9f0", "submitter": { "id": 1398, "url": "https://patches.dpdk.org/api/people/1398/?format=api", "name": "Alvin Zhang", "email": "alvinx.zhang@intel.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200413063037.13728-9-alvinx.zhang@intel.com/mbox/", "series": [ { "id": 9328, "url": "https://patches.dpdk.org/api/series/9328/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9328", "date": "2020-04-13T06:30:26", "name": "igc pmd", "version": 3, "mbox": "https://patches.dpdk.org/series/9328/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/68250/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/68250/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D4D4FA0577;\n\tMon, 13 Apr 2020 08:33:35 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 507D61BF57;\n\tMon, 13 Apr 2020 08:31:48 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id 6C51E1BF57\n for <dev@dpdk.org>; Mon, 13 Apr 2020 08:31:43 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Apr 2020 23:31:43 -0700", "from shwdenpg235.ccr.corp.intel.com ([10.240.182.60])\n by orsmga002.jf.intel.com with ESMTP; 12 Apr 2020 23:31:41 -0700" ], "IronPort-SDR": [ "\n A12pgARc1/rckFo4sSCi4hNK3Mv2UyYX4L6snb7h2b2eBWlnKgw/iWLPywPiPUTaXIUGXF4s+/\n 4zJfJR9ri1lA==", "\n H8z7UjPzNzeyuo/Qvs39BvEegu76VOYf/WVQ4vtaaAAS2MNDpXbc469pIBopI9kylfa5K2nuBK\n +50UBV1fpESA==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,377,1580803200\"; d=\"scan'208\";a=\"270987690\"", "From": "alvinx.zhang@intel.com", "To": "dev@dpdk.org", "Cc": "xiaolong.ye@intel.com,\n\tAlvin Zhang <alvinx.zhang@intel.com>", "Date": "Mon, 13 Apr 2020 14:30:34 +0800", "Message-Id": "<20200413063037.13728-9-alvinx.zhang@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20200413063037.13728-1-alvinx.zhang@intel.com>", "References": "<20200413063037.13728-1-alvinx.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 08/11] net/igc: implement RSS API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Alvin Zhang <alvinx.zhang@intel.com>\n\nBelow ops are added:\nreta_update\nreta_query\nrss_hash_update\nrss_hash_conf_get\n\nSigned-off-by: Alvin Zhang <alvinx.zhang@intel.com>\n---\n doc/guides/nics/features/igc.ini | 2 +\n drivers/net/igc/igc_ethdev.c | 171 +++++++++++++++++++++++++++++++++++++++\n drivers/net/igc/igc_ethdev.h | 9 +++\n drivers/net/igc/igc_txrx.c | 2 +-\n drivers/net/igc/igc_txrx.h | 2 +\n 5 files changed, 185 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/igc.ini b/doc/guides/nics/features/igc.ini\nindex a364e04..23434af 100644\n--- a/doc/guides/nics/features/igc.ini\n+++ b/doc/guides/nics/features/igc.ini\n@@ -28,6 +28,8 @@ Extended stats = Y\n Stats per queue = Y\n Rx interrupt = Y\n Flow control = Y\n+RSS key update = Y\n+RSS reta update = Y\n Linux UIO = Y\n Linux VFIO = Y\n x86-64 = Y\ndiff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c\nindex a135176..554c809 100644\n--- a/drivers/net/igc/igc_ethdev.c\n+++ b/drivers/net/igc/igc_ethdev.c\n@@ -217,6 +217,16 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);\n static int\n eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);\n+static int eth_igc_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size);\n+static int eth_igc_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t uint16_t reta_size);\n+static int eth_igc_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_conf *rss_conf);\n+static int eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_conf *rss_conf);\n \n static const struct eth_dev_ops eth_igc_ops = {\n \t.dev_configure\t\t= eth_igc_configure,\n@@ -265,6 +275,10 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n \t.rx_queue_intr_disable\t= eth_igc_rx_queue_intr_disable,\n \t.flow_ctrl_get\t\t= eth_igc_flow_ctrl_get,\n \t.flow_ctrl_set\t\t= eth_igc_flow_ctrl_set,\n+\t.reta_update\t\t= eth_igc_rss_reta_update,\n+\t.reta_query\t\t= eth_igc_rss_reta_query,\n+\t.rss_hash_update\t= eth_igc_rss_hash_update,\n+\t.rss_hash_conf_get\t= eth_igc_rss_hash_conf_get,\n };\n \n /*\n@@ -2188,6 +2202,163 @@ static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,\n }\n \n static int\n+eth_igc_rss_reta_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint16_t i;\n+\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of RSS redirection table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* set redirection table */\n+\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {\n+\t\tunion igc_rss_reta_reg reta, reg;\n+\t\tuint16_t idx, shift;\n+\t\tuint8_t j, mask;\n+\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\tIGC_RSS_RDT_REG_SIZE_MASK);\n+\n+\t\t/* if no need to update the register */\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\t/* check mask whether need to read the register value first */\n+\t\tif (mask == IGC_RSS_RDT_REG_SIZE_MASK)\n+\t\t\treg.dword = 0;\n+\t\telse\n+\t\t\treg.dword = IGC_READ_REG_LE_VALUE(hw,\n+\t\t\t\t\tIGC_RETA(i / IGC_RSS_RDT_REG_SIZE));\n+\n+\t\t/* update the register */\n+\t\tfor (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {\n+\t\t\tif (mask & (1u << j))\n+\t\t\t\treta.bytes[j] =\n+\t\t\t\t\t(uint8_t)reta_conf[idx].reta[shift + j];\n+\t\t\telse\n+\t\t\t\treta.bytes[j] = reg.bytes[j];\n+\t\t}\n+\t\tIGC_WRITE_REG_LE_VALUE(hw,\n+\t\t\tIGC_RETA(i / IGC_RSS_RDT_REG_SIZE), reta.dword);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+eth_igc_rss_reta_query(struct rte_eth_dev *dev,\n+\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t uint16_t reta_size)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint16_t i;\n+\n+\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of RSS redirection table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\"(%d)\", reta_size, ETH_RSS_RETA_SIZE_128);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* read redirection table */\n+\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {\n+\t\tunion igc_rss_reta_reg reta;\n+\t\tuint16_t idx, shift;\n+\t\tuint8_t j, mask;\n+\n+\t\tidx = i / RTE_RETA_GROUP_SIZE;\n+\t\tshift = i % RTE_RETA_GROUP_SIZE;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\tIGC_RSS_RDT_REG_SIZE_MASK);\n+\n+\t\t/* if no need to read register */\n+\t\tif (!mask)\n+\t\t\tcontinue;\n+\n+\t\t/* read register and get the queue index */\n+\t\treta.dword = IGC_READ_REG_LE_VALUE(hw,\n+\t\t\t\tIGC_RETA(i / IGC_RSS_RDT_REG_SIZE));\n+\t\tfor (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {\n+\t\t\tif (mask & (1u << j))\n+\t\t\t\treta_conf[idx].reta[shift + j] = reta.bytes[j];\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+eth_igc_rss_hash_update(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tigc_hw_rss_hash_set(hw, rss_conf);\n+\treturn 0;\n+}\n+\n+static int\n+eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,\n+\t\t\tstruct rte_eth_rss_conf *rss_conf)\n+{\n+\tstruct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);\n+\tuint32_t *hash_key = (uint32_t *)rss_conf->rss_key;\n+\tuint32_t mrqc;\n+\tuint64_t rss_hf;\n+\n+\tif (hash_key != NULL) {\n+\t\tint i;\n+\n+\t\t/* if not enough space for store hash key */\n+\t\tif (rss_conf->rss_key_len != IGC_HKEY_SIZE) {\n+\t\t\tPMD_DRV_LOG(ERR, \"RSS hash key size %u in parameter \"\n+\t\t\t\t\"doesn't match the hardware hash key size %u\",\n+\t\t\t\trss_conf->rss_key_len, IGC_HKEY_SIZE);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\t/* read RSS key from register */\n+\t\tfor (i = 0; i < IGC_HKEY_MAX_INDEX; i++)\n+\t\t\thash_key[i] = IGC_READ_REG_LE_VALUE(hw, IGC_RSSRK(i));\n+\t}\n+\n+\t/* get RSS functions configured in MRQC register */\n+\tmrqc = IGC_READ_REG(hw, IGC_MRQC);\n+\tif ((mrqc & IGC_MRQC_ENABLE_RSS_4Q) == 0)\n+\t\treturn 0;\n+\n+\trss_hf = 0;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV4)\n+\t\trss_hf |= ETH_RSS_IPV4;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV4_TCP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6)\n+\t\trss_hf |= ETH_RSS_IPV6;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6_EX)\n+\t\trss_hf |= ETH_RSS_IPV6_EX;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP_EX)\n+\t\trss_hf |= ETH_RSS_IPV6_TCP_EX;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV4_UDP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP)\n+\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;\n+\tif (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP_EX)\n+\t\trss_hf |= ETH_RSS_IPV6_UDP_EX;\n+\n+\trss_conf->rss_hf |= rss_hf;\n+\treturn 0;\n+}\n+\n+static int\n eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \tstruct rte_pci_device *pci_dev)\n {\ndiff --git a/drivers/net/igc/igc_ethdev.h b/drivers/net/igc/igc_ethdev.h\nindex d63890f..e8fd1b1 100644\n--- a/drivers/net/igc/igc_ethdev.h\n+++ b/drivers/net/igc/igc_ethdev.h\n@@ -16,11 +16,20 @@\n extern \"C\" {\n #endif\n \n+#define IGC_RSS_RDT_SIZD\t\t128\n #define IGC_QUEUE_PAIRS_NUM\t\t4\n \n #define IGC_HKEY_MAX_INDEX\t\t10\n #define IGC_RSS_RDT_SIZD\t\t128\n \n+#define IGC_DEFAULT_REG_SIZE\t\t4\n+#define IGC_DEFAULT_REG_SIZE_MASK\t0xf\n+\n+#define IGC_RSS_RDT_REG_SIZE\t\tIGC_DEFAULT_REG_SIZE\n+#define IGC_RSS_RDT_REG_SIZE_MASK\tIGC_DEFAULT_REG_SIZE_MASK\n+#define IGC_HKEY_REG_SIZE\t\tIGC_DEFAULT_REG_SIZE\n+#define IGC_HKEY_SIZE\t\t\t(IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)\n+\n /*\n * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be\n * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.\ndiff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c\nindex 906fbcb..03998c0 100644\n--- a/drivers/net/igc/igc_txrx.c\n+++ b/drivers/net/igc/igc_txrx.c\n@@ -845,7 +845,7 @@ int eth_igc_rx_descriptor_status(void *rx_queue, uint16_t offset)\n \tIGC_WRITE_REG(hw, IGC_MRQC, mrqc);\n }\n \n-static void\n+void\n igc_hw_rss_hash_set(struct igc_hw *hw, struct rte_eth_rss_conf *rss_conf)\n {\n \tuint32_t *hash_key = (uint32_t *)rss_conf->rss_key;\ndiff --git a/drivers/net/igc/igc_txrx.h b/drivers/net/igc/igc_txrx.h\nindex 00ef512..82ca95e 100644\n--- a/drivers/net/igc/igc_txrx.h\n+++ b/drivers/net/igc/igc_txrx.h\n@@ -38,6 +38,8 @@ int eth_igc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \n int igc_rx_init(struct rte_eth_dev *dev);\n void igc_tx_init(struct rte_eth_dev *dev);\n+void\n+igc_hw_rss_hash_set(struct igc_hw *hw, struct rte_eth_rss_conf *rss_conf);\n void eth_igc_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tstruct rte_eth_rxq_info *qinfo);\n void eth_igc_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n", "prefixes": [ "v3", "08/11" ] }