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GET /api/patches/67992/?format=api
{ "id": 67992, "url": "https://patches.dpdk.org/api/patches/67992/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200408082921.31000-27-mk@semihalf.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200408082921.31000-27-mk@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200408082921.31000-27-mk@semihalf.com", "date": "2020-04-08T08:29:17", "name": "[v3,26/30] net/ena: use macros for ring idx operations", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c38cb4f82b3ad773446373404e3631de0fa89dcb", "submitter": { "id": 786, "url": "https://patches.dpdk.org/api/people/786/?format=api", "name": "Michal Krawczyk", "email": "mk@semihalf.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200408082921.31000-27-mk@semihalf.com/mbox/", "series": [ { "id": 9246, "url": "https://patches.dpdk.org/api/series/9246/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9246", "date": "2020-04-08T08:28:51", "name": "Update ENA driver to v2.1.0", "version": 3, "mbox": "https://patches.dpdk.org/series/9246/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67992/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/67992/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 036F5A0597;\n\tWed, 8 Apr 2020 10:33:56 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4F3C51C1E6;\n\tWed, 8 Apr 2020 10:30:05 +0200 (CEST)", "from mail-lf1-f66.google.com (mail-lf1-f66.google.com\n [209.85.167.66]) by dpdk.org (Postfix) with ESMTP id 7AEC21C1C9\n for <dev@dpdk.org>; Wed, 8 Apr 2020 10:29:59 +0200 (CEST)", "by mail-lf1-f66.google.com with SMTP id z23so4478487lfh.8\n for <dev@dpdk.org>; Wed, 08 Apr 2020 01:29:59 -0700 (PDT)", "from mkPC.semihalf.local (193-106-246-138.noc.fibertech.net.pl.\n [193.106.246.138])\n by smtp.gmail.com with ESMTPSA id e8sm765685lja.3.2020.04.08.01.29.57\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 08 Apr 2020 01:29:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20150623.gappssmtp.com; s=20150623;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=BslQqR8WPPTfYqe91WVQAV1nqvQPKZkv3Be+1cG2SRg=;\n b=xV0KTD97rGnZIzyLtpI/IzkU/qYRwF3dUZY5v8r/uCGWlAT+8ppkyFaKk+MvZnN7Cl\n leIxLnRj3CejW3UKWOOQImG9StMx8V3RNphxnx32TXs2GSwli6s2B0+kaVP+brX0FnMx\n M6B/L6xHGZ8OhwmAs/r6JlhRKFLslweElYEds0lzHuKOyiRRdse03z84C1i+zVNCys1V\n 3G+cryUybY9fBYALxSyNqNaED17o1VzmYv5ybT1up5mQ31DgScpv6roW6FadFTYWv3Y0\n +gj2AhIkU8Nc+pYIouXBeqNUzUTNSu7byLV3pgVzh/HrT4Ud5cWx6OitmDglINGnwLT2\n Bt5g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=BslQqR8WPPTfYqe91WVQAV1nqvQPKZkv3Be+1cG2SRg=;\n b=IbFWrj+JoppqWCP1u2Y4YNH3fDp3PKgVsB3Wa2LhVY+FtPvkCuTp3O1mhvb2dyUYhR\n ZIU7/4hWU7mbLFllBnS7YVaMSN23pLmroOR1Vxh3gmGLVlw50N488CCwFhuhqE8aFLNA\n Y2cySUxrpzge3mJIz6jQr4lg9ZXSqugZRPeGsT4Miyzj8eK8E5fkGtZa9o/1Jonha08j\n 5YChH9ndIEpODdHClnPVzHmOMh8ojd01xYljdELxum2RNwJZsK/qS/O6yAfEQolK0kBo\n lMnfMEGhzXrqZIwx4C13cCF0DZ56o1ge4LS8jU8p988+sus4nQPY6emH/1xKzau5Hik7\n Xxfg==", "X-Gm-Message-State": "AGi0PuYDQjsRsdVItnlvpr2OYo/+LeVPBNLirZSDjWXmCxDYJP0DQUCJ\n xMakMYyD/UXv/M/MKNeKsDPHTyItBBA=", "X-Google-Smtp-Source": "\n APiQypK+KZdP7WAgZ+8UC/RM7g8U9HrfilUos1ZLM2hLuHTNJ5GKcMuG/RCo+e0P5DqHcH10XrBtFw==", "X-Received": "by 2002:ac2:4112:: with SMTP id b18mr3871389lfi.106.1586334598731;\n Wed, 08 Apr 2020 01:29:58 -0700 (PDT)", "From": "Michal Krawczyk <mk@semihalf.com>", "To": "dev@dpdk.org", "Cc": "mw@semihalf.com, mba@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com,\n igorch@amazon.com, ferruh.yigit@intel.com, arybchenko@solarflare.com,\n Michal Krawczyk <mk@semihalf.com>", "Date": "Wed, 8 Apr 2020 10:29:17 +0200", "Message-Id": "<20200408082921.31000-27-mk@semihalf.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20200408082921.31000-1-mk@semihalf.com>", "References": "<20200408082921.31000-1-mk@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 26/30] net/ena: use macros for ring idx\n\toperations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "To improve code readability, abstraction was added for operating on IO\nrings indexes.\n\nDriver was defining local variable for ring mask in each function that\nneeded to operate on the ring indexes. Now it is being stored in the\nring as this value won't change unless size of the ring will change and\nmacros for advancing indexes using the mask has been added.\n\nSigned-off-by: Michal Krawczyk <mk@semihalf.com>\nReviewed-by: Igor Chauskin <igorch@amazon.com>\nReviewed-by: Guy Tzalik <gtzalik@amazon.com>\n---\n drivers/net/ena/ena_ethdev.c | 53 ++++++++++++++++++------------------\n drivers/net/ena/ena_ethdev.h | 4 +++\n 2 files changed, 30 insertions(+), 27 deletions(-)", "diff": "diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c\nindex 7804a5c85d..f6d0a75819 100644\n--- a/drivers/net/ena/ena_ethdev.c\n+++ b/drivers/net/ena/ena_ethdev.c\n@@ -1266,6 +1266,7 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev,\n \ttxq->next_to_clean = 0;\n \ttxq->next_to_use = 0;\n \ttxq->ring_size = nb_desc;\n+\ttxq->size_mask = nb_desc - 1;\n \ttxq->numa_socket_id = socket_id;\n \n \ttxq->tx_buffer_info = rte_zmalloc(\"txq->tx_buffer_info\",\n@@ -1361,6 +1362,7 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev,\n \trxq->next_to_clean = 0;\n \trxq->next_to_use = 0;\n \trxq->ring_size = nb_desc;\n+\trxq->size_mask = nb_desc - 1;\n \trxq->numa_socket_id = socket_id;\n \trxq->mb_pool = mp;\n \n@@ -1409,8 +1411,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)\n {\n \tunsigned int i;\n \tint rc;\n-\tuint16_t ring_size = rxq->ring_size;\n-\tuint16_t ring_mask = ring_size - 1;\n \tuint16_t next_to_use = rxq->next_to_use;\n \tuint16_t in_use, req_id;\n \tstruct rte_mbuf **mbufs = rxq->rx_refill_buffer;\n@@ -1418,9 +1418,10 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)\n \tif (unlikely(!count))\n \t\treturn 0;\n \n-\tin_use = ring_size - ena_com_free_q_entries(rxq->ena_com_io_sq) - 1;\n-\n-\tena_assert_msg(((in_use + count) < ring_size), \"bad ring state\\n\");\n+\tin_use = rxq->ring_size - 1 -\n+\t\tena_com_free_q_entries(rxq->ena_com_io_sq);\n+\tena_assert_msg(((in_use + count) < rxq->ring_size),\n+\t\t\"bad ring state\\n\");\n \n \t/* get resources for incoming packets */\n \trc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count);\n@@ -1432,7 +1433,6 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)\n \t}\n \n \tfor (i = 0; i < count; i++) {\n-\t\tuint16_t next_to_use_masked = next_to_use & ring_mask;\n \t\tstruct rte_mbuf *mbuf = mbufs[i];\n \t\tstruct ena_com_buf ebuf;\n \t\tstruct ena_rx_buffer *rx_info;\n@@ -1440,7 +1440,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)\n \t\tif (likely((i + 4) < count))\n \t\t\trte_prefetch0(mbufs[i + 4]);\n \n-\t\treq_id = rxq->empty_rx_reqs[next_to_use_masked];\n+\t\treq_id = rxq->empty_rx_reqs[next_to_use];\n \t\trc = validate_rx_req_id(rxq, req_id);\n \t\tif (unlikely(rc))\n \t\t\tbreak;\n@@ -1458,7 +1458,7 @@ static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count)\n \t\t\tbreak;\n \t\t}\n \t\trx_info->mbuf = mbuf;\n-\t\tnext_to_use++;\n+\t\tnext_to_use = ENA_IDX_NEXT_MASKED(next_to_use, rxq->size_mask);\n \t}\n \n \tif (unlikely(i < count)) {\n@@ -2072,7 +2072,6 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,\n \tstruct rte_mbuf *mbuf;\n \tstruct rte_mbuf *mbuf_head;\n \tstruct ena_rx_buffer *rx_info;\n-\tunsigned int ring_mask = rx_ring->ring_size - 1;\n \tuint16_t ntc, len, req_id, buf = 0;\n \n \tif (unlikely(descs == 0))\n@@ -2100,8 +2099,8 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,\n \tmbuf_head->data_off += offset;\n \n \trx_info->mbuf = NULL;\n-\trx_ring->empty_rx_reqs[ntc & ring_mask] = req_id;\n-\t++ntc;\n+\trx_ring->empty_rx_reqs[ntc] = req_id;\n+\tntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);\n \n \twhile (--descs) {\n \t\t++buf;\n@@ -2123,8 +2122,8 @@ static struct rte_mbuf *ena_rx_mbuf(struct ena_ring *rx_ring,\n \t\tmbuf_head->pkt_len += len;\n \n \t\trx_info->mbuf = NULL;\n-\t\trx_ring->empty_rx_reqs[ntc & ring_mask] = req_id;\n-\t\t++ntc;\n+\t\trx_ring->empty_rx_reqs[ntc] = req_id;\n+\t\tntc = ENA_IDX_NEXT_MASKED(ntc, rx_ring->size_mask);\n \t}\n \n \t*next_to_clean = ntc;\n@@ -2136,8 +2135,6 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t uint16_t nb_pkts)\n {\n \tstruct ena_ring *rx_ring = (struct ena_ring *)(rx_queue);\n-\tunsigned int ring_size = rx_ring->ring_size;\n-\tunsigned int ring_mask = ring_size - 1;\n \tunsigned int free_queue_entries;\n \tunsigned int refill_threshold;\n \tuint16_t next_to_clean = rx_ring->next_to_clean;\n@@ -2154,7 +2151,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\treturn 0;\n \t}\n \n-\tdescs_in_use = ring_size -\n+\tdescs_in_use = rx_ring->ring_size -\n \t\tena_com_free_q_entries(rx_ring->ena_com_io_sq) - 1;\n \tnb_pkts = RTE_MIN(descs_in_use, nb_pkts);\n \n@@ -2183,9 +2180,10 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\tena_rx_ctx.pkt_offset);\n \t\tif (unlikely(mbuf == NULL)) {\n \t\t\tfor (i = 0; i < ena_rx_ctx.descs; ++i) {\n-\t\t\t\trx_ring->empty_rx_reqs[next_to_clean & ring_mask] =\n+\t\t\t\trx_ring->empty_rx_reqs[next_to_clean] =\n \t\t\t\t\trx_ring->ena_bufs[i].req_id;\n-\t\t\t\t++next_to_clean;\n+\t\t\t\tnext_to_clean = ENA_IDX_NEXT_MASKED(\n+\t\t\t\t\tnext_to_clean, rx_ring->size_mask);\n \t\t\t}\n \t\t\tbreak;\n \t\t}\n@@ -2210,7 +2208,7 @@ static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \tfree_queue_entries = ena_com_free_q_entries(rx_ring->ena_com_io_sq);\n \trefill_threshold =\n-\t\tRTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER,\n+\t\tRTE_MIN(rx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,\n \t\t(unsigned int)ENA_REFILL_THRESH_PACKET);\n \n \t/* Burst refill to save doorbells, memory barriers, const interval */\n@@ -2353,8 +2351,6 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint16_t next_to_clean = tx_ring->next_to_clean;\n \tstruct rte_mbuf *mbuf;\n \tuint16_t seg_len;\n-\tunsigned int ring_size = tx_ring->ring_size;\n-\tunsigned int ring_mask = ring_size - 1;\n \tunsigned int cleanup_budget;\n \tstruct ena_com_tx_ctx ena_tx_ctx;\n \tstruct ena_tx_buffer *tx_info;\n@@ -2384,7 +2380,7 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tif (unlikely(rc))\n \t\t\tbreak;\n \n-\t\treq_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask];\n+\t\treq_id = tx_ring->empty_tx_reqs[next_to_use];\n \t\ttx_info = &tx_ring->tx_buffer_info[req_id];\n \t\ttx_info->mbuf = mbuf;\n \t\ttx_info->num_of_bufs = 0;\n@@ -2428,7 +2424,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads,\n \t\t\ttx_ring->disable_meta_caching);\n \n-\t\trte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]);\n+\t\trte_prefetch0(tx_pkts[ENA_IDX_ADD_MASKED(\n+\t\t\tsent_idx, 4, tx_ring->size_mask)]);\n \n \t\t/* Process first segment taking into\n \t\t * consideration pushed header\n@@ -2480,7 +2477,8 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t}\n \t\ttx_info->tx_descs = nb_hw_desc;\n \n-\t\tnext_to_use++;\n+\t\tnext_to_use = ENA_IDX_NEXT_MASKED(next_to_use,\n+\t\t\ttx_ring->size_mask);\n \t\ttx_ring->tx_stats.cnt++;\n \t\ttx_ring->tx_stats.bytes += total_length;\n \t}\n@@ -2511,10 +2509,11 @@ static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\ttx_info->mbuf = NULL;\n \n \t\t/* Put back descriptor to the ring for reuse */\n-\t\ttx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id;\n-\t\tnext_to_clean++;\n+\t\ttx_ring->empty_tx_reqs[next_to_clean] = req_id;\n+\t\tnext_to_clean = ENA_IDX_NEXT_MASKED(next_to_clean,\n+\t\t\ttx_ring->size_mask);\n \t\tcleanup_budget =\n-\t\t\tRTE_MIN(ring_size / ENA_REFILL_THRESH_DIVIDER,\n+\t\t\tRTE_MIN(tx_ring->ring_size / ENA_REFILL_THRESH_DIVIDER,\n \t\t\t(unsigned int)ENA_REFILL_THRESH_PACKET);\n \n \t\t/* If too many descs to clean, leave it for another run */\ndiff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h\nindex 13d87d48f0..6e24a4e582 100644\n--- a/drivers/net/ena/ena_ethdev.h\n+++ b/drivers/net/ena/ena_ethdev.h\n@@ -40,6 +40,9 @@\n #define ENA_REFILL_THRESH_DIVIDER 8\n #define ENA_REFILL_THRESH_PACKET 256\n \n+#define ENA_IDX_NEXT_MASKED(idx, mask) (((idx) + 1) & (mask))\n+#define ENA_IDX_ADD_MASKED(idx, n, mask) (((idx) + (n)) & (mask))\n+\n struct ena_adapter;\n \n enum ena_ring_type {\n@@ -109,6 +112,7 @@ struct ena_ring {\n \t};\n \tstruct rte_mbuf **rx_refill_buffer;\n \tunsigned int ring_size; /* number of tx/rx_buffer_info's entries */\n+\tunsigned int size_mask;\n \n \tstruct ena_com_io_cq *ena_com_io_cq;\n \tstruct ena_com_io_sq *ena_com_io_sq;\n", "prefixes": [ "v3", "26/30" ] }