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GET /api/patches/67373/?format=api
{ "id": 67373, "url": "https://patches.dpdk.org/api/patches/67373/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-4-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1585526580-113508-4-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1585526580-113508-4-git-send-email-nicolas.chautru@intel.com", "date": "2020-03-30T00:02:50", "name": "[v2,03/13] drivers/baseband: add PMD for FPGA 5GNR FEC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7ed63d9278d19f9471d1cf07b20288884d13f117", "submitter": { "id": 1314, "url": "https://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1585526580-113508-4-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 9086, "url": "https://patches.dpdk.org/api/series/9086/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=9086", "date": "2020-03-30T00:02:47", "name": "drivers/baseband: add PMD for FPGA 5GNR FEC", "version": 2, "mbox": "https://patches.dpdk.org/series/9086/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/67373/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/67373/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D47A2A0562;\n\tMon, 30 Mar 2020 02:04:40 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 875141C08E;\n\tMon, 30 Mar 2020 02:04:02 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by dpdk.org (Postfix) with ESMTP id 05D65FFA\n for <dev@dpdk.org>; Mon, 30 Mar 2020 02:03:52 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 29 Mar 2020 17:03:50 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by orsmga003.jf.intel.com with ESMTP; 29 Mar 2020 17:03:50 -0700" ], "IronPort-SDR": [ "\n CHtR/4JP0S+psteuog+4vbiefcTGm3Pb1C6FrP0vL9Is0d+Mml6izYAZclBguMEk72jn3opvWR\n hEoMESXtzVnA==", "\n HySZRHbCDCd2IG5uIX05iLjer15u8zb1FgfT/CI+dxwJOls/SFT0w3cBjHPy5I4qP409Whf45W\n K1b1yKyqUguQ==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.72,322,1580803200\"; d=\"scan'208\";a=\"248455336\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com", "Cc": "bruce.richardson@intel.com,\n\tNicolas Chautru <nicolas.chautru@intel.com>", "Date": "Sun, 29 Mar 2020 17:02:50 -0700", "Message-Id": "<1585526580-113508-4-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1585526580-113508-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 03/13] drivers/baseband: add PMD for FPGA 5GNR\n\tFEC", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add stubs for the FPGA 5GNR FEC PMD\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n config/common_base | 5 +\n doc/guides/bbdevs/fpga_5gnr_fec.rst | 146 ++++++++++++++++\n doc/guides/bbdevs/index.rst | 1 +\n doc/guides/rel_notes/release_20_05.rst | 5 +\n drivers/baseband/Makefile | 2 +\n drivers/baseband/fpga_5gnr_fec/Makefile | 26 +++\n drivers/baseband/fpga_5gnr_fec/meson.build | 6 +\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 193 +++++++++++++++++++++\n drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h | 41 +++++\n .../rte_pmd_bbdev_fpga_5gnr_fec_version.map | 3 +\n drivers/baseband/meson.build | 2 +-\n mk/rte.app.mk | 1 +\n 12 files changed, 430 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/bbdevs/fpga_5gnr_fec.rst\n create mode 100644 drivers/baseband/fpga_5gnr_fec/Makefile\n create mode 100644 drivers/baseband/fpga_5gnr_fec/meson.build\n create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h\n create mode 100644 drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map", "diff": "diff --git a/config/common_base b/config/common_base\nindex c31175f..9ec689d 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -577,6 +577,11 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y\n CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC=y\n \n #\n+# Compile PMD for Intel FPGA 5GNR FEC bbdev device\n+#\n+CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC=y\n+\n+#\n # Compile generic crypto device library\n #\n CONFIG_RTE_LIBRTE_CRYPTODEV=y\ndiff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst\nnew file mode 100644\nindex 0000000..007ace0\n--- /dev/null\n+++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst\n@@ -0,0 +1,146 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Intel Corporation\n+\n+Intel(R) FPGA 5GNR FEC Poll Mode Driver\n+======================================\n+\n+The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN\n+LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA\n+based Vista Creek device.\n+\n+Features\n+--------\n+\n+FPGA 5GNR FEC PMD supports the following features:\n+\n+- 8 VFs per PF (physical device)\n+- Maximum of 32 UL queues per VF\n+- Maximum of 32 DL queues per VF\n+- PCIe Gen-3 x8 Interface\n+- MSI-X\n+- SR-IOV\n+\n+Limitations\n+-----------\n+\n+FPGA 5GNR FEC does not support the following:\n+\n+- Scatter-Gather function\n+\n+\n+Installation\n+--------------\n+\n+Section 3 of the DPDK manual provides instuctions on installing and compiling DPDK. The\n+default set of bbdev compile flags may be found in config/common_base, where for example\n+the flag to build the FPGA 5GNR FEC device, ``CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC``,\n+is already set. It is assumed DPDK has been compiled using for instance:\n+\n+.. code-block:: console\n+\n+ make install T=x86_64-native-linuxapp-gcc\n+\n+\n+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.\n+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The\n+hugepage configuration of a server may be examined using:\n+\n+.. code-block:: console\n+\n+ grep Huge* /proc/meminfo\n+\n+\n+Initialization\n+--------------\n+\n+When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:\n+\n+.. code-block:: console\n+\n+ sudo lspci -vd8086:0d8f\n+\n+The physical and virtual functions are compatible with Linux UIO drivers:\n+``vfio`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs\n+to be bound to one of these linux drivers through DPDK.\n+\n+\n+Bind PF UIO driver(s)\n+~~~~~~~~~~~~~~~~~~~~~\n+\n+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use\n+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.\n+\n+The igb_uio driver may be bound to the PF PCI device using one of three methods:\n+\n+\n+1. PCI functions (physical or virtual, depending on the use case) can be bound to\n+the UIO driver by repeating this command for every function.\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ insmod ./build/kmod/igb_uio.ko\n+ echo \"8086 0d8f\" > /sys/bus/pci/drivers/igb_uio/new_id\n+ lspci -vd8086:0d8f\n+\n+\n+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ ./usertools/dpdk-devbind.py -b igb_uio 0000:06:00.0\n+\n+where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d8f\n+\n+\n+3. A third way to bind is to use ``dpdk-setup.sh`` tool\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ ./usertools/dpdk-setup.sh\n+\n+ select 'Bind Ethernet/Crypto/Baseband device to IGB UIO module'\n+ or\n+ select 'Bind Ethernet/Crypto/Baseband device to VFIO module' depending on driver required\n+ enter PCI device ID\n+ select 'Display current Ethernet/Crypto/Baseband device settings' to confirm binding\n+\n+\n+In the same way the FPGA 5GNR FEC PF can be bound with vfio, but vfio driver does not\n+support SR-IOV configuration right out of the box, so it will need to be patched.\n+\n+\n+Enable Virtual Functions\n+~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Now, it should be visible in the printouts that PCI PF is under igb_uio control\n+\"``Kernel driver in use: igb_uio``\"\n+\n+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..\n+\n+.. code-block:: console\n+\n+ cat /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_totalvfs\n+\n+ where 0000\\:<b>\\:<d>.<f> is the PCI device ID\n+\n+\n+To enable VFs via igb_uio, echo the number of virtual functions intended to\n+enable to ``max_vfs`` file..\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/max_vfs\n+\n+\n+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same\n+way it was done with the physical function previously.\n+\n+Enabling SR-IOV via vfio driver is pretty much the same, except that the file\n+name is different:\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_numvfs\ndiff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst\nindex 005b95e..1a79343 100644\n--- a/doc/guides/bbdevs/index.rst\n+++ b/doc/guides/bbdevs/index.rst\n@@ -11,3 +11,4 @@ Baseband Device Drivers\n null\n turbo_sw\n fpga_lte_fec\n+ fpga_5gnr_fec\ndiff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst\nindex 1dfcfcc..e76b50c 100644\n--- a/doc/guides/rel_notes/release_20_05.rst\n+++ b/doc/guides/rel_notes/release_20_05.rst\n@@ -70,6 +70,11 @@ New Features\n by making use of the event device capabilities. The event mode currently supports\n only inline IPsec protocol offload.\n \n+* **Added Intel FPGA_5GNR_FEC bbdev PMD.**\n+\n+ Added a new ``fpga_5gnr_fec`` bbdev driver for the Intel\\ |reg| FPGA PAC\n+ (Programmable Acceleration Card) N3000. See the\n+ :doc:`../bbdevs/fpga_5gnr_fec` BBDEV guide for more details on this new driver.\n \n Removed Items\n -------------\ndiff --git a/drivers/baseband/Makefile b/drivers/baseband/Makefile\nindex 91048be..dcc0969 100644\n--- a/drivers/baseband/Makefile\n+++ b/drivers/baseband/Makefile\n@@ -12,5 +12,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += turbo_sw\n DEPDIRS-turbo_sw = $(core-libs)\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += fpga_lte_fec\n DEPDIRS-fpga_lte_fec = $(core-libs)\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += fpga_5gnr_fec\n+DEPDIRS-fpga_5gnr_fec = $(core-libs)\n \n include $(RTE_SDK)/mk/rte.subdir.mk\ndiff --git a/drivers/baseband/fpga_5gnr_fec/Makefile b/drivers/baseband/fpga_5gnr_fec/Makefile\nnew file mode 100644\nindex 0000000..3f5c511\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/Makefile\n@@ -0,0 +1,26 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2019 Intel Corporation\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_bbdev_fpga_5gnr_fec.a\n+\n+# build flags\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_bbdev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_bbdev_fpga_5gnr_fec_version.map\n+\n+# library version\n+LIBABIVER := 1\n+\n+# library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += rte_fpga_5gnr_fec.c\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/baseband/fpga_5gnr_fec/meson.build b/drivers/baseband/fpga_5gnr_fec/meson.build\nnew file mode 100644\nindex 0000000..c148ea9\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/meson.build\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Intel Corporation\n+\n+deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']\n+allow_experimental_apis = true\n+sources = files('rte_fpga_5gnr_fec.c')\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\nnew file mode 100644\nindex 0000000..ee9577d\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c\n@@ -0,0 +1,193 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include <unistd.h>\n+\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_malloc.h>\n+#include <rte_mempool.h>\n+#include <rte_errno.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#include <rte_byteorder.h>\n+\n+#include <rte_bbdev.h>\n+#include <rte_bbdev_pmd.h>\n+\n+#include \"rte_fpga_5gnr_fec.h\"\n+\n+/* 5GNR SW PMD logging ID */\n+static int fpga_5gnr_fec_logtype;\n+\n+static int\n+fpga_dev_close(struct rte_bbdev *dev __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+static const struct rte_bbdev_ops fpga_ops = {\n+\t.close = fpga_dev_close,\n+};\n+\n+/* Initialization Function */\n+static void\n+fpga_5gnr_fec_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n+\n+\tdev->dev_ops = &fpga_ops;\n+\n+\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->pf_device =\n+\t\t\t!strcmp(drv->driver.name,\n+\t\t\t\t\tRTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME));\n+\t((struct fpga_5gnr_fec_device *) dev->data->dev_private)->mmio_base =\n+\t\t\tpci_dev->mem_resource[0].addr;\n+\n+\trte_bbdev_log_debug(\n+\t\t\t\"Init device %s [%s] @ virtaddr %p phyaddr %#\"PRIx64,\n+\t\t\tdev->device->driver->name, dev->data->name,\n+\t\t\t(void *)pci_dev->mem_resource[0].addr,\n+\t\t\tpci_dev->mem_resource[0].phys_addr);\n+}\n+\n+static int\n+fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,\n+\tstruct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_bbdev *bbdev = NULL;\n+\tchar dev_name[RTE_BBDEV_NAME_MAX_LEN];\n+\n+\tif (pci_dev == NULL) {\n+\t\trte_bbdev_log(ERR, \"NULL PCI device\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));\n+\n+\t/* Allocate memory to be used privately by drivers */\n+\tbbdev = rte_bbdev_allocate(pci_dev->device.name);\n+\tif (bbdev == NULL)\n+\t\treturn -ENODEV;\n+\n+\t/* allocate device private memory */\n+\tbbdev->data->dev_private = rte_zmalloc_socket(dev_name,\n+\t\t\tsizeof(struct fpga_5gnr_fec_device),\n+\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\tpci_dev->device.numa_node);\n+\n+\tif (bbdev->data->dev_private == NULL) {\n+\t\trte_bbdev_log(CRIT,\n+\t\t\t\t\"Allocate of %zu bytes for device \\\"%s\\\" failed\",\n+\t\t\t\tsizeof(struct fpga_5gnr_fec_device), dev_name);\n+\t\t\t\trte_bbdev_release(bbdev);\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Fill HW specific part of device structure */\n+\tbbdev->device = &pci_dev->device;\n+\tbbdev->intr_handle = &pci_dev->intr_handle;\n+\tbbdev->data->socket_id = pci_dev->device.numa_node;\n+\n+\t/* Invoke FEC FPGA device initialization function */\n+\tfpga_5gnr_fec_init(bbdev, pci_drv);\n+\n+\trte_bbdev_log_debug(\"bbdev id = %u [%s]\",\n+\t\t\tbbdev->data->dev_id, dev_name);\n+\n+\treturn 0;\n+}\n+\n+static int\n+fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_bbdev *bbdev;\n+\tint ret;\n+\tuint8_t dev_id;\n+\n+\tif (pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Find device */\n+\tbbdev = rte_bbdev_get_named_dev(pci_dev->device.name);\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(CRIT,\n+\t\t\t\t\"Couldn't find HW dev \\\"%s\\\" to uninitialise it\",\n+\t\t\t\tpci_dev->device.name);\n+\t\treturn -ENODEV;\n+\t}\n+\tdev_id = bbdev->data->dev_id;\n+\n+\t/* free device private memory before close */\n+\trte_free(bbdev->data->dev_private);\n+\n+\t/* Close device */\n+\tret = rte_bbdev_close(dev_id);\n+\tif (ret < 0)\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Device %i failed to close during uninit: %i\",\n+\t\t\t\tdev_id, ret);\n+\n+\t/* release bbdev from library */\n+\tret = rte_bbdev_release(bbdev);\n+\tif (ret)\n+\t\trte_bbdev_log(ERR, \"Device %i failed to uninit: %i\", dev_id,\n+\t\t\t\tret);\n+\n+\trte_bbdev_log_debug(\"Destroyed bbdev = %u\", dev_id);\n+\n+\treturn 0;\n+}\n+\n+/* FPGA 5GNR FEC PCI PF address map */\n+static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,\n+\t\t\t\tFPGA_5GNR_FEC_PF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = {\n+\t.probe = fpga_5gnr_fec_probe,\n+\t.remove = fpga_5gnr_fec_remove,\n+\t.id_table = pci_id_fpga_5gnr_fec_pf_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+/* FPGA 5GNR FEC PCI VF address map */\n+static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID,\n+\t\t\t\tFPGA_5GNR_FEC_VF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+static struct rte_pci_driver fpga_5gnr_fec_pci_vf_driver = {\n+\t.probe = fpga_5gnr_fec_probe,\n+\t.remove = fpga_5gnr_fec_remove,\n+\t.id_table = pci_id_fpga_5gnr_fec_vf_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+\n+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_PF_DRIVER_NAME, fpga_5gnr_fec_pci_pf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME,\n+\t\tpci_id_fpga_5gnr_fec_pf_map);\n+RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME,\n+\t\tpci_id_fpga_5gnr_fec_vf_map);\n+\n+RTE_INIT(fpga_5gnr_fec_init_log)\n+{\n+\tfpga_5gnr_fec_logtype = rte_log_register(\"pmd.bb.fpga_5gnr_fec\");\n+\tif (fpga_5gnr_fec_logtype >= 0)\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+\t\trte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG);\n+#else\n+\t\trte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE);\n+#endif\n+}\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h\nnew file mode 100644\nindex 0000000..aeb1e94\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.h\n@@ -0,0 +1,41 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _RTE_FPGA_5GNR_FEC_H_\n+#define _RTE_FPGA_5GNR_FEC_H_\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+\n+/* Helper macro for logging */\n+#define rte_bbdev_log(level, fmt, ...) \\\n+\trte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt \"\\n\", \\\n+\t\t##__VA_ARGS__)\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+#define rte_bbdev_log_debug(fmt, ...) \\\n+\t\trte_bbdev_log(DEBUG, \"fpga_5gnr_fec: \" fmt, \\\n+\t\t##__VA_ARGS__)\n+#else\n+#define rte_bbdev_log_debug(fmt, ...)\n+#endif\n+\n+/* FPGA 5GNR FEC driver names */\n+#define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf\n+#define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf\n+\n+/* FPGA 5GNR FEC PCI vendor & device IDs */\n+#define FPGA_5GNR_FEC_VENDOR_ID (0x8086)\n+#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F)\n+#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90)\n+\n+/* Private data structure for each FPGA FEC device */\n+struct fpga_5gnr_fec_device {\n+\t/** Base address of MMIO registers (BAR0) */\n+\tvoid *mmio_base;\n+\t/** True if this is a PF FPGA FEC device */\n+\tbool pf_device;\n+};\n+\n+#endif /* _RTE_FPGA_5GNR_FEC_H_ */\ndiff --git a/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map\nnew file mode 100644\nindex 0000000..f9f17e4\n--- /dev/null\n+++ b/drivers/baseband/fpga_5gnr_fec/rte_pmd_bbdev_fpga_5gnr_fec_version.map\n@@ -0,0 +1,3 @@\n+DPDK_20.0 {\n+\tlocal: *;\n+};\ndiff --git a/drivers/baseband/meson.build b/drivers/baseband/meson.build\nindex be7677f..4d909f9 100644\n--- a/drivers/baseband/meson.build\n+++ b/drivers/baseband/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2018 Luca Boccassi <bluca@debian.org>\n \n-drivers = ['null', 'turbo_sw', 'fpga_lte_fec']\n+drivers = ['null', 'turbo_sw', 'fpga_lte_fec', 'fpga_5gnr_fec']\n \n config_flag_fmt = 'RTE_LIBRTE_PMD_BBDEV_@0@'\n driver_name_fmt = 'rte_pmd_bbdev_@0@'\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex d295ca0..da12b9e 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -246,6 +246,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_NETVSC_PMD) += -lrte_pmd_netvsc\n ifeq ($(CONFIG_RTE_LIBRTE_BBDEV),y)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL) += -lrte_pmd_bbdev_null\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC) += -lrte_pmd_bbdev_fpga_lte_fec\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) += -lrte_pmd_bbdev_fpga_5gnr_fec\n \n # TURBO SOFTWARE PMD is dependent on the FLEXRAN library\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW) += -lrte_pmd_bbdev_turbo_sw\n", "prefixes": [ "v2", "03/13" ] }