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GET /api/patches/6653/?format=api
{ "id": 6653, "url": "https://patches.dpdk.org/api/patches/6653/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1438151900-27849-1-git-send-email-xuelin.shi@freescale.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1438151900-27849-1-git-send-email-xuelin.shi@freescale.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1438151900-27849-1-git-send-email-xuelin.shi@freescale.com", "date": "2015-07-29T06:38:20", "name": "[dpdk-dev,v4] ixgbe: fix data access on big endian cpu.", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7718d15c44682fb717493f740b6e2e71f5ff4ba3", "submitter": { "id": 168, "url": "https://patches.dpdk.org/api/people/168/?format=api", "name": "", "email": "xuelin.shi@freescale.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1438151900-27849-1-git-send-email-xuelin.shi@freescale.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/6653/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/6653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 4A8CBC4C4;\n\tWed, 29 Jul 2015 09:38:54 +0200 (CEST)", "from na01-by2-obe.outbound.protection.outlook.com\n\t(mail-by2on0103.outbound.protection.outlook.com [207.46.100.103])\n\tby dpdk.org (Postfix) with ESMTP id 5D089C494\n\tfor <dev@dpdk.org>; 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\n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "<xuelin.shi@freescale.com>", "To": "<konstantin.ananyev@intel.com>", "Date": "Wed, 29 Jul 2015 14:38:20 +0800", "Message-ID": "<1438151900-27849-1-git-send-email-xuelin.shi@freescale.com>", "X-Mailer": "git-send-email 1.8.4", "X-EOPAttributedMessage": "0", "X-Microsoft-Exchange-Diagnostics": [ "1; BY2FFO11FD050;\n\t1:U91+bVSOZIk7C1kS+umVmaDqT+hn0QbFc7ibL9WswuVLSrx4lWHJ/+oJQBazbXZO0r3vuCM+6vWSQusg6HBkAuN0RlqKgjqmImgVyBZ0SRnGnzN/kGO2tItxMo+6QyFhqxUFPKxBAQ0smparIc8xX8Me6LQQ2rvW+zrNxPkJgJYywW+wY27+AAsvjNu+R0KW2WVB+KkQ+6y85OSuzAlE9urovw57c3EZMqv6MR/qKljmmasGI86/3WmTk1Y8xARrqVRC2vil2dla2TNAj77pTDHTObMK8Zxvx0cbU+FMPF8U39lBwhZhV44P7qxUYF9NvJl1226sgMo1XQ+dRYu1Kw==", "1; BN3PR03MB1336;\n\t2:AwvswgB1/7Lq8GB6qtCQWsZUcGojplE0xq9kbRkKlR21zygF6u15ClU4tpxgEVKdvb5tAFxzwGCVpN9tJF9ehkbH+RQA9hxRdClJ5SKf4jWwxCqeB6Wejuzm1/Khy+Sdb6B0S9x8GDNBfnY0mGC/jUbyZFCg/Pr6tte+eLZnpNI=;\n\t3:E6EgwfFTURkM/yIYn4XBbKo1vavwTsnTG/XFI3KFBJxOduDn9jgiHUVQH7k/gkwD+rleL1IXUvbgUtru+Z65GK/yttiDby4bisUBMYSRo1p0XwflGgDS5tk12qD6Rn0S4uJWc+yEfakVRGD39zs/7PaUZP3rabPylIF6lcPNkMQzuwYTENI6y5lQnDQOBaX3V93Sw0nvbpkzvvF0c8H1IQ3pgnwGhItQuPO6LjP6RRQ=;\n\t25:9Z51iv7dJRcLyXAFmbeDw5rEscwURtJV8PERqOE5LxNJeBLRm+8yDfzUNCIk+ZFtJKA94txeux2vyrO8nWKGmxJ29XbbkRzPcgp2LBevVPvOuZFEsXbQRY+9rSP3nrrKnfRhMbihUh0alHl20plHjnlkckE3V6HANn54SLs6zOG6CCYGa88fJ9jRYwoqpZn2ABZBfww8SRzIp6PhfrZV5By9rNLuIUDby+uBuMONJfIRhFimHALNcDDn5HyMY2/y", "1; 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BN3PR03MB1336;\n\t5:BTPa1txHPkXxrK0exvXmRcI/gGgBfG+QErCUPAgpkRGv9GCiPdNvPPNGKxn88r9clcRGJtHod04l98zjvRMUMuMKwP+mZ+rp1Iw4srfP/+P7cW74c/UhIHNBlmSP6Ns0AhTO53nmd+X2tG5MmcIXcg==;\n\t24:DhGtUtXiDlAW74MoP/eG52bgztSZ4A53FJdfxKOjewo/goZqx/Sj0S9Y52/rxRIsETJraNO3V2cXz5ym7nPEHo1kPKoclVBruQIX6P6mCqo=;\n\t20:YK++fXa5M9lle7hP8gqOd30y8NO60UH9Ju9HQnnYh0ubDC2qWLB+1dd5tTuC2C0DQaByM/kyzsu7b8WJ2Uo3BA==" ], "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(57986006)(110136002)(5001960100002)(19580395003)(86152002)(104016003)(19580405001)(86362001)(107886002)(85426001)(92566002)(62966003)(36756003)(105606002)(87936001)(47776003)(106466001)(33646002)(76506005)(77156002)(46102003)(189998001)(6806004)(2351001)(48376002)(229853001)(77096005)(50986999)(4001430100001);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR03MB1336;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; ", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1336;", "BN3PR03MB1336": "X-MS-Exchange-Organization-RulesExecuted", "X-Microsoft-Antispam-PRVS": "<BN3PR03MB13368757955F1999D9CC3075868C0@BN3PR03MB1336.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(5005006)(3002001); SRVR:BN3PR03MB1336; BCL:0; PCL:0;\n\tRULEID:; SRVR:BN3PR03MB1336; ", "X-Forefront-PRVS": "0652EA5565", "X-OriginatorOrg": "freescale.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Jul 2015 07:38:49.0532\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "710a03f5-10f6-4d38-9ff4-a80b81da590d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR03MB1336", "Cc": "dev@dpdk.org, Xuelin Shi <xuelin.shi@freescale.com>", "Subject": "[dpdk-dev] [PATCH v4] ixgbe: fix data access on big endian cpu.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Xuelin Shi <xuelin.shi@freescale.com>\n\n1. cpu use data owned by ixgbe must use rte_le_to_cpu_xx(...)\n2. cpu fill data to ixgbe must use rte_cpu_to_le_xx(...)\n3. checking pci status with converted constant\n\nSigned-off-by: Xuelin Shi <xuelin.shi@freescale.com>\n---\nchanges for v4:\n fix compiling error: cpu16 to cpu_16\n fix issues reported by checkpatch\n\n drivers/net/ixgbe/ixgbe_rxtx.c | 78 ++++++++++++++++++++++++++++--------------\n 1 file changed, 52 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex a7c94a9..f904b40 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -130,7 +130,7 @@ ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)\n \n \t/* check DD bit on threshold descriptor */\n \tstatus = txq->tx_ring[txq->tx_next_dd].wb.status;\n-\tif (! (status & IXGBE_ADVTXD_STAT_DD))\n+\tif (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))\n \t\treturn 0;\n \n \t/*\n@@ -175,11 +175,14 @@ tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)\n \t\tpkt_len = (*pkts)->data_len;\n \n \t\t/* write data to descriptor */\n-\t\ttxdp->read.buffer_addr = buf_dma_addr;\n+\t\ttxdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n+\n \t\ttxdp->read.cmd_type_len =\n-\t\t\t\t((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n+\t\t\trte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n+\n \t\ttxdp->read.olinfo_status =\n-\t\t\t\t(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n+\t\t\trte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n+\n \t\trte_prefetch0(&(*pkts)->pool);\n \t}\n }\n@@ -195,11 +198,14 @@ tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)\n \tpkt_len = (*pkts)->data_len;\n \n \t/* write data to descriptor */\n-\ttxdp->read.buffer_addr = buf_dma_addr;\n+\ttxdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n+\n \ttxdp->read.cmd_type_len =\n-\t\t\t((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n+\t\t\trte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n+\n \ttxdp->read.olinfo_status =\n-\t\t\t(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n+\t\t\trte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n+\n \trte_prefetch0(&(*pkts)->pool);\n }\n \n@@ -511,6 +517,7 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)\n \tuint16_t nb_tx_desc = txq->nb_tx_desc;\n \tuint16_t desc_to_clean_to;\n \tuint16_t nb_tx_to_clean;\n+\tuint32_t stat;\n \n \t/* Determine the last descriptor needing to be cleaned */\n \tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);\n@@ -519,7 +526,9 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)\n \n \t/* Check to make sure the last descriptor to clean is done */\n \tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n-\tif (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))\n+\n+\tstat = txr[desc_to_clean_to].wb.status;\n+\tif (!(stat & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD)))\n \t{\n \t\tPMD_TX_FREE_LOG(DEBUG,\n \t\t\t\t\"TX descriptor %4u is not done\"\n@@ -806,12 +815,14 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t */\n \t\t\tslen = m_seg->data_len;\n \t\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n+\n \t\t\ttxd->read.buffer_addr =\n \t\t\t\trte_cpu_to_le_64(buf_dma_addr);\n \t\t\ttxd->read.cmd_type_len =\n \t\t\t\trte_cpu_to_le_32(cmd_type_len | slen);\n \t\t\ttxd->read.olinfo_status =\n \t\t\t\trte_cpu_to_le_32(olinfo_status);\n+\n \t\t\ttxe->last_id = tx_last;\n \t\t\ttx_id = txe->next_id;\n \t\t\ttxe = txn;\n@@ -1062,14 +1073,16 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n \tint s[LOOK_AHEAD], nb_dd;\n #endif /* RTE_NEXT_ABI */\n \tint i, j, nb_rx = 0;\n+\tuint32_t stat;\n \n \n \t/* get references to current descriptor and S/W ring entry */\n \trxdp = &rxq->rx_ring[rxq->rx_tail];\n \trxep = &rxq->sw_ring[rxq->rx_tail];\n \n+\tstat = rxdp->wb.upper.status_error;\n \t/* check to make sure there is at least 1 packet to receive */\n-\tif (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))\n+\tif (!(stat & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n \t\treturn 0;\n \n \t/*\n@@ -1081,7 +1094,7 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n \t{\n \t\t/* Read desc statuses backwards to avoid race condition */\n \t\tfor (j = LOOK_AHEAD-1; j >= 0; --j)\n-\t\t\ts[j] = rxdp[j].wb.upper.status_error;\n+\t\t\ts[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);\n \n #ifdef RTE_NEXT_ABI\n \t\tfor (j = LOOK_AHEAD - 1; j >= 0; --j)\n@@ -1099,7 +1112,9 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n \t\t/* Translate descriptor info to mbuf format */\n \t\tfor (j = 0; j < nb_dd; ++j) {\n \t\t\tmb = rxep[j].mbuf;\n-\t\t\tpkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);\n+\t\t\tpkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -\n+\t\t\t\t rxq->crc_len;\n+\n \t\t\tmb->data_len = pkt_len;\n \t\t\tmb->pkt_len = pkt_len;\n \t\t\tmb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);\n@@ -1115,7 +1130,9 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n \t\t\t\tixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);\n #else /* RTE_NEXT_ABI */\n \t\t\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(\n-\t\t\t\t\trxdp[j].wb.lower.lo_dword.data);\n+\t\t\t\t\trte_le_to_cpu_32(\n+\t\t\t\t\trxdp[j].wb.lower.lo_dword.data));\n+\n \t\t\t/* reuse status field from scan list */\n \t\t\tpkt_flags |= rx_desc_status_to_pkt_flags(s[j]);\n \t\t\tpkt_flags |= rx_desc_error_to_pkt_flags(s[j]);\n@@ -1123,12 +1140,16 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n #endif /* RTE_NEXT_ABI */\n \n \t\t\tif (likely(pkt_flags & PKT_RX_RSS_HASH))\n-\t\t\t\tmb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;\n+\t\t\t\tmb->hash.rss = rte_le_to_cpu_32(\n+\t\t\t\t rxdp[j].wb.lower.hi_dword.rss);\n+\n \t\t\telse if (pkt_flags & PKT_RX_FDIR) {\n-\t\t\t\tmb->hash.fdir.hash =\n-\t\t\t\t\t(uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)\n-\t\t\t\t\t\t& IXGBE_ATR_HASH_MASK);\n-\t\t\t\tmb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;\n+\t\t\t\tmb->hash.fdir.hash = rte_le_to_cpu_16(\n+\t\t\t\t rxdp[j].wb.lower.hi_dword.csum_ip.csum) &\n+\t\t\t\t IXGBE_ATR_HASH_MASK;\n+\n+\t\t\t\tmb->hash.fdir.id = rte_le_to_cpu_16(\n+\t\t\t\t rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);\n \t\t\t}\n \t\t}\n \n@@ -1365,7 +1386,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t */\n \t\trxdp = &rx_ring[rx_id];\n \t\tstaterr = rxdp->wb.upper.status_error;\n-\t\tif (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n+\t\tif (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n \t\t\tbreak;\n \t\trxd = *rxdp;\n \n@@ -1483,12 +1504,15 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n #endif /* RTE_NEXT_ABI */\n \n \t\tif (likely(pkt_flags & PKT_RX_RSS_HASH))\n-\t\t\trxm->hash.rss = rxd.wb.lower.hi_dword.rss;\n+\t\t\trxm->hash.rss = rte_le_to_cpu_32(\n+\t\t\t\t\t\trxd.wb.lower.hi_dword.rss);\n \t\telse if (pkt_flags & PKT_RX_FDIR) {\n-\t\t\trxm->hash.fdir.hash =\n-\t\t\t\t(uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)\n-\t\t\t\t\t & IXGBE_ATR_HASH_MASK);\n-\t\t\trxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;\n+\t\t\trxm->hash.fdir.hash = rte_le_to_cpu_16(\n+\t\t\t\t\trxd.wb.lower.hi_dword.csum_ip.csum) &\n+\t\t\t\t\tIXGBE_ATR_HASH_MASK;\n+\n+\t\t\trxm->hash.fdir.id = rte_le_to_cpu_16(\n+\t\t\t\t\trxd.wb.lower.hi_dword.csum_ip.ip_id);\n \t\t}\n \t\t/*\n \t\t * Store the mbuf address into the next entry of the array\n@@ -1998,7 +2022,7 @@ ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)\n \tprev = (uint16_t) (txq->nb_tx_desc - 1);\n \tfor (i = 0; i < txq->nb_tx_desc; i++) {\n \t\tvolatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];\n-\t\ttxd->wb.status = IXGBE_TXD_STAT_DD;\n+\t\ttxd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);\n \t\ttxe[i].mbuf = NULL;\n \t\ttxe[i].last_id = i;\n \t\ttxe[prev].next_id = i;\n@@ -2604,7 +2628,8 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \trxdp = &(rxq->rx_ring[rxq->rx_tail]);\n \n \twhile ((desc < rxq->nb_rx_desc) &&\n-\t\t(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {\n+\t\t(rxdp->wb.upper.status_error &\n+\t\t\trte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {\n \t\tdesc += IXGBE_RXQ_SCAN_INTERVAL;\n \t\trxdp += IXGBE_RXQ_SCAN_INTERVAL;\n \t\tif (rxq->rx_tail + desc >= rxq->nb_rx_desc)\n@@ -2629,7 +2654,8 @@ ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)\n \t\tdesc -= rxq->nb_rx_desc;\n \n \trxdp = &rxq->rx_ring[desc];\n-\treturn !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);\n+\treturn !!(rxdp->wb.upper.status_error &\n+\t\t\trte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));\n }\n \n void __attribute__((cold))\n", "prefixes": [ "dpdk-dev", "v4" ] }