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GET /api/patches/65240/?format=api
{ "id": 65240, "url": "https://patches.dpdk.org/api/patches/65240/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20200128142220.16644-9-marcinx.smoczynski@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200128142220.16644-9-marcinx.smoczynski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200128142220.16644-9-marcinx.smoczynski@intel.com", "date": "2020-01-28T14:22:20", "name": "[v5,8/8] doc: add cpu crypto related documentation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "dcaf623f8e34555a288982a7c2b44e7e56a3fb82", "submitter": { "id": 1293, "url": "https://patches.dpdk.org/api/people/1293/?format=api", "name": "Marcin Smoczynski", "email": "marcinx.smoczynski@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20200128142220.16644-9-marcinx.smoczynski@intel.com/mbox/", "series": [ { "id": 8323, "url": "https://patches.dpdk.org/api/series/8323/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=8323", "date": "2020-01-28T14:22:12", "name": "Introduce CPU crypto mode", "version": 5, "mbox": "https://patches.dpdk.org/series/8323/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/65240/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/65240/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4DAF4A04B3;\n\tTue, 28 Jan 2020 15:24:13 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 29DCC1D152;\n\tTue, 28 Jan 2020 15:22:54 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n by dpdk.org (Postfix) with ESMTP id 3A50A1D149\n for <dev@dpdk.org>; Tue, 28 Jan 2020 15:22:49 +0100 (CET)", "from orsmga001.jf.intel.com ([10.7.209.18])\n by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 28 Jan 2020 06:22:48 -0800", "from msmoczyx-mobl.ger.corp.intel.com ([10.103.102.190])\n by orsmga001.jf.intel.com with ESMTP; 28 Jan 2020 06:22:45 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,374,1574150400\"; d=\"scan'208\";a=\"309092880\"", "From": "Marcin Smoczynski <marcinx.smoczynski@intel.com>", "To": "akhil.goyal@nxp.com, konstantin.ananyev@intel.com,\n roy.fan.zhang@intel.com,\n declan.doherty@intel.com, radu.nicolau@intel.com,\n pablo.de.lara.guarch@intel.com", "Cc": "dev@dpdk.org,\n\tMarcin Smoczynski <marcinx.smoczynski@intel.com>", "Date": "Tue, 28 Jan 2020 15:22:20 +0100", "Message-Id": "<20200128142220.16644-9-marcinx.smoczynski@intel.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20200128142220.16644-1-marcinx.smoczynski@intel.com>", "References": "<20200128031642.15256-1-marcinx.smoczynski@intel.com>\n <20200128142220.16644-1-marcinx.smoczynski@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 8/8] doc: add cpu crypto related documentation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update documentation with a description of cpu crypto in cryptodev,\nipsec and security libraries.\n\nAdd release notes for 20.02.\n\nSigned-off-by: Marcin Smoczynski <marcinx.smoczynski@intel.com>\n---\n doc/guides/cryptodevs/aesni_gcm.rst | 7 +++++-\n doc/guides/prog_guide/cryptodev_lib.rst | 33 ++++++++++++++++++++++++-\n doc/guides/prog_guide/ipsec_lib.rst | 10 +++++++-\n doc/guides/prog_guide/rte_security.rst | 15 ++++++++---\n doc/guides/rel_notes/release_20_02.rst | 8 ++++++\n 5 files changed, 66 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/aesni_gcm.rst b/doc/guides/cryptodevs/aesni_gcm.rst\nindex 151aa3060..a25b63109 100644\n--- a/doc/guides/cryptodevs/aesni_gcm.rst\n+++ b/doc/guides/cryptodevs/aesni_gcm.rst\n@@ -1,5 +1,5 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2016-2019 Intel Corporation.\n+ Copyright(c) 2016-2020 Intel Corporation.\n \n AES-NI GCM Crypto Poll Mode Driver\n ==================================\n@@ -9,6 +9,11 @@ The AES-NI GCM PMD (**librte_pmd_aesni_gcm**) provides poll mode crypto driver\n support for utilizing Intel multi buffer library (see AES-NI Multi-buffer PMD documentation\n to learn more about it, including installation).\n \n+The AES-NI GCM PMD supports synchronous mode of operation with\n+``rte_cryptodev_sym_cpu_crypto_process`` function call for both AES-GCM and\n+GMAC, however GMAC support is limited to one segment per operation. Please\n+refer to ``rte_crypto`` programmer's guide for more detail.\n+\n Features\n --------\n \ndiff --git a/doc/guides/prog_guide/cryptodev_lib.rst b/doc/guides/prog_guide/cryptodev_lib.rst\nindex ac1643774..b91f7c8b7 100644\n--- a/doc/guides/prog_guide/cryptodev_lib.rst\n+++ b/doc/guides/prog_guide/cryptodev_lib.rst\n@@ -1,5 +1,5 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2016-2017 Intel Corporation.\n+ Copyright(c) 2016-2020 Intel Corporation.\n \n Cryptography Device Library\n ===========================\n@@ -600,6 +600,37 @@ chain.\n };\n };\n \n+Synchronous mode\n+----------------\n+\n+Some cryptodevs support synchronous mode alongside with a standard asynchronous\n+mode. In that case operations are performed directly when calling\n+``rte_cryptodev_sym_cpu_crypto_process`` method instead of enqueuing and\n+dequeuing an operation before. This mode of operation allows cryptodevs which\n+utilize CPU cryptographic acceleration to have significant performance boost\n+comparing to standard asynchronous approach. Cryptodevs supporting synchronous\n+mode have ``RTE_CRYPTODEV_FF_SYM_CPU_CRYPTO`` feature flag set.\n+\n+To perform a synchronous operation a call to\n+``rte_cryptodev_sym_cpu_crypto_process`` has to be made with vectorized\n+operation descriptor (``struct rte_crypto_sym_vec``) containing:\n+\n+- ``num`` - number of operations to perform,\n+- pointer to an array of size ``num`` containing a scatter-gather list\n+ descriptors of performed operations (``struct rte_crypto_sgl``). Each instance\n+ of ``struct rte_crypto_sgl`` consists of a number of segments and a pointer to\n+ an array of segment descriptors ``struct rte_crypto_vec``;\n+- pointers to arrays of size ``num`` containing IV, AAD and digest information,\n+- pointer to an array of size ``num`` where status information will be stored\n+ for each operation.\n+\n+Function returns a number of successfully completed operations and sets\n+appropriate status number for each operation in the status array provided as\n+a call argument. Status different than zero must be treated as error.\n+\n+For more details, e.g. how to convert an mbuf to an SGL, please refer to an\n+example usage in the IPsec library implementation.\n+\n Sample code\n -----------\n \ndiff --git a/doc/guides/prog_guide/ipsec_lib.rst b/doc/guides/prog_guide/ipsec_lib.rst\nindex 1ce0db453..0a860eb47 100644\n--- a/doc/guides/prog_guide/ipsec_lib.rst\n+++ b/doc/guides/prog_guide/ipsec_lib.rst\n@@ -1,5 +1,5 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2018 Intel Corporation.\n+ Copyright(c) 2018-2020 Intel Corporation.\n \n IPsec Packet Processing Library\n ===============================\n@@ -81,6 +81,14 @@ In that mode the library functions perform\n - verify that crypto device operations (encryption, ICV generation)\n were completed successfully\n \n+RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+In that mode the library functions perform same operations as in\n+``RTE_SECURITY_ACTION_TYPE_NONE``. The only differnce is that crypto operations\n+are performed with CPU crypto synchronous API.\n+\n+\n RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n \ndiff --git a/doc/guides/prog_guide/rte_security.rst b/doc/guides/prog_guide/rte_security.rst\nindex f77fb89dc..a911c676b 100644\n--- a/doc/guides/prog_guide/rte_security.rst\n+++ b/doc/guides/prog_guide/rte_security.rst\n@@ -511,13 +511,20 @@ Offload.\n /**< No security actions */\n RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO,\n /**< Crypto processing for security protocol is processed inline\n- * during transmission */\n+ * during transmission\n+ */\n RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,\n /**< All security protocol processing is performed inline during\n- * transmission */\n- RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL\n+ * transmission\n+ */\n+ RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\n /**< All security protocol processing including crypto is performed\n- * on a lookaside accelerator */\n+ * on a lookaside accelerator\n+ */\n+ RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO\n+ /**< Crypto processing for security protocol is processed by CPU\n+ * synchronously\n+ */\n };\n \n The ``rte_security_session_protocol`` is defined as\ndiff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst\nindex 50e2c1484..b6cf0c4d1 100644\n--- a/doc/guides/rel_notes/release_20_02.rst\n+++ b/doc/guides/rel_notes/release_20_02.rst\n@@ -143,6 +143,14 @@ New Features\n Added a new OCTEON TX2 rawdev PMD for End Point mode of operation.\n See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.\n \n+* **Added synchronous Crypto burst API.**\n+\n+ A new API is introduced in crypto library to handle synchronous cryptographic\n+ operations allowing to achieve performance gain for cryptodevs which use\n+ CPU based acceleration, such as Intel AES-NI. An example implementation\n+ for aesni_gcm cryptodev is provided including unit tests. The IPsec example\n+ application and ipsec library itself were changed to allow utilization of this\n+ new feature.\n \n Removed Items\n -------------\n", "prefixes": [ "v5", "8/8" ] }